Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T16
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T16
1	0	Covered	T3,T7,T16
1	1	Covered	T3,T7,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T16,T119,T120
1	0	Covered	T16,T93,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T35
0	1	Covered	T3,T7,T35
1	0	Covered	T109

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T35
1	-	Covered	T3,T7,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T16
DetectSt	168	Covered	T3,T7,T16
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T7,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T16
DebounceSt->IdleSt	163	Covered	T105,T268,T67
DetectSt->IdleSt	186	Covered	T16,T93,T97
DetectSt->StableSt	191	Covered	T3,T7,T35
IdleSt->DebounceSt	148	Covered	T3,T7,T16
StableSt->IdleSt	206	Covered	T3,T7,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T16
0	1	Covered	T3,T7,T16
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T16
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T16
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T105,T268,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T93,T97
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T35
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T16
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T35
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	3481	0	0
CntIncr_A	5916283	112462	0	0
CntNoWrap_A	5916283	5437994	0	0
DetectStDropOut_A	5916283	486	0	0
DetectedOut_A	5916283	78978	0	0
DetectedPulseOut_A	5916283	943	0	0
DisabledIdleSt_A	5916283	4993365	0	0
DisabledNoDetection_A	5916283	4995159	0	0
EnterDebounceSt_A	5916283	1751	0	0
EnterDetectSt_A	5916283	1730	0	0
EnterStableSt_A	5916283	943	0	0
PulseIsPulse_A	5916283	943	0	0
StayInStableSt	5916283	77928	0	0
gen_high_event_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	831	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3481	0	0
T3	25937	14	0	0
T4	746	0	0	0
T7	17991	18	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	18	0	0
T17	402	0	0	0
T35	0	64	0	0
T51	0	46	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	22	0	0
T94	0	46	0	0
T95	0	2	0	0
T96	0	34	0	0
T97	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	112462	0	0
T3	25937	385	0	0
T4	746	0	0	0
T7	17991	612	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	747	0	0
T17	402	0	0	0
T35	0	1568	0	0
T51	0	1426	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	821	0	0
T94	0	1334	0	0
T95	0	21	0	0
T96	0	1037	0	0
T97	0	824	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5437994	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25504	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17564	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	486	0	0
T8	612	0	0	0
T9	1451	0	0	0
T16	10468	6	0	0
T17	402	0	0	0
T25	526	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T62	405	0	0	0
T68	653	0	0	0
T76	404	0	0	0
T119	0	11	0	0
T120	0	12	0	0
T121	0	18	0	0
T122	0	21	0	0
T123	0	3	0	0
T124	0	13	0	0
T125	0	26	0	0
T126	0	12	0	0
T269	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	78978	0	0
T3	25937	138	0	0
T4	746	0	0	0
T7	17991	500	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	5475	0	0
T51	0	2113	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	2083	0	0
T95	0	84	0	0
T96	0	1846	0	0
T98	0	120	0	0
T270	0	727	0	0
T271	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	943	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	23	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	23	0	0
T95	0	1	0	0
T96	0	17	0	0
T98	0	5	0	0
T270	0	25	0	0
T271	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4993365	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	22388	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	11891	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4995159	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	22396	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	11895	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1751	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	9	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	23	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	11	0	0
T94	0	23	0	0
T95	0	1	0	0
T96	0	17	0	0
T97	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1730	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	9	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	23	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	11	0	0
T94	0	23	0	0
T95	0	1	0	0
T96	0	17	0	0
T97	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	943	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	23	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	23	0	0
T95	0	1	0	0
T96	0	17	0	0
T98	0	5	0	0
T270	0	25	0	0
T271	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	943	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	23	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	23	0	0
T95	0	1	0	0
T96	0	17	0	0
T98	0	5	0	0
T270	0	25	0	0
T271	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	77928	0	0
T3	25937	130	0	0
T4	746	0	0	0
T7	17991	491	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	5439	0	0
T51	0	2087	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	2059	0	0
T95	0	82	0	0
T96	0	1829	0	0
T98	0	115	0	0
T270	0	702	0	0
T271	0	34	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	831	0	0
T3	25937	6	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	28	0	0
T51	0	20	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	22	0	0
T96	0	17	0	0
T98	0	5	0	0
T251	0	20	0	0
T270	0	25	0	0
T272	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T52
1	0	Covered	T105,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T37
0	1	Covered	T3,T12,T37
1	0	Covered	T105,T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T37
1	-	Covered	T3,T12,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T12,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T1,T2,T52
DetectSt->IdleSt	186	Covered	T1,T2,T52
DetectSt->StableSt	191	Covered	T3,T12,T37
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T3,T12,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T52
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T2,T52
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T37
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T3,T12,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	805	0	0
CntIncr_A	5916283	40646	0	0
CntNoWrap_A	5916283	5440670	0	0
DetectStDropOut_A	5916283	76	0	0
DetectedOut_A	5916283	11892	0	0
DetectedPulseOut_A	5916283	297	0	0
DisabledIdleSt_A	5916283	5100027	0	0
DisabledNoDetection_A	5916283	5101370	0	0
EnterDebounceSt_A	5916283	430	0	0
EnterDetectSt_A	5916283	377	0	0
EnterStableSt_A	5916283	297	0	0
PulseIsPulse_A	5916283	297	0	0
StayInStableSt	5916283	11563	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	263	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	805	0	0
T1	20180	20	0	0
T2	28487	5	0	0
T3	25937	2	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	12	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	8	0	0
T36	0	8	0	0
T37	0	16	0	0
T51	0	6	0	0
T52	0	8	0	0
T54	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	40646	0	0
T1	20180	1073	0	0
T2	28487	161	0	0
T3	25937	55	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	942	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	288	0	0
T36	0	624	0	0
T37	0	1104	0	0
T51	0	240	0	0
T52	0	738	0	0
T54	0	908	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5440670	0	0
T1	20180	19745	0	0
T2	28487	28057	0	0
T3	25937	25516	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17582	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	76	0	0
T1	20180	9	0	0
T2	28487	2	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T52	0	3	0	0
T54	0	8	0	0
T127	0	11	0	0
T128	0	3	0	0
T129	0	3	0	0
T130	0	6	0	0
T131	0	10	0	0
T132	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	11892	0	0
T3	25937	59	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	61	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	1230	0	0
T36	0	170	0	0
T37	0	44	0	0
T51	0	178	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	64	0	0
T95	0	3	0	0
T96	0	77	0	0
T144	0	451	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	297	0	0
T3	25937	1	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T51	0	3	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T144	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5100027	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	25381	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17082	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5101370	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	25390	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17087	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	430	0	0
T1	20180	11	0	0
T2	28487	3	0	0
T3	25937	1	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T51	0	3	0	0
T52	0	5	0	0
T54	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	377	0	0
T1	20180	9	0	0
T2	28487	2	0	0
T3	25937	1	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T51	0	3	0	0
T52	0	3	0	0
T54	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	297	0	0
T3	25937	1	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T51	0	3	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T144	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	297	0	0
T3	25937	1	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T51	0	3	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T144	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	11563	0	0
T3	25937	58	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	55	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	1226	0	0
T36	0	166	0	0
T37	0	36	0	0
T51	0	173	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	63	0	0
T95	0	2	0	0
T96	0	76	0	0
T144	0	442	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	263	0	0
T3	25937	1	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	8	0	0
T51	0	1	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T144	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T16
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T16
1	0	Covered	T3,T7,T16
1	1	Covered	T3,T7,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T35,T93,T96
1	0	Covered	T35,T93,T96

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T3,T7,T16
1	0	Covered	T111

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T16
1	-	Covered	T3,T7,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T16
DetectSt	168	Covered	T3,T7,T16
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T7,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T16
DebounceSt->IdleSt	163	Covered	T105,T268,T67
DetectSt->IdleSt	186	Covered	T35,T93,T96
DetectSt->StableSt	191	Covered	T3,T7,T16
IdleSt->DebounceSt	148	Covered	T3,T7,T16
StableSt->IdleSt	206	Covered	T3,T7,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T16
0	1	Covered	T3,T7,T16
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T16
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T16
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T105,T268,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T16
DetectSt	-	-	-	-	1	-	-	Covered	T35,T93,T96
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T16
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T16
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T16
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T16
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	3011	0	0
CntIncr_A	5916283	93655	0	0
CntNoWrap_A	5916283	5438464	0	0
DetectStDropOut_A	5916283	430	0	0
DetectedOut_A	5916283	61967	0	0
DetectedPulseOut_A	5916283	785	0	0
DisabledIdleSt_A	5916283	5008431	0	0
DisabledNoDetection_A	5916283	5010246	0	0
EnterDebounceSt_A	5916283	1515	0	0
EnterDetectSt_A	5916283	1497	0	0
EnterStableSt_A	5916283	785	0	0
PulseIsPulse_A	5916283	785	0	0
StayInStableSt	5916283	61096	0	0
gen_high_event_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	698	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3011	0	0
T3	25937	14	0	0
T4	746	0	0	0
T7	17991	20	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	30	0	0
T17	402	0	0	0
T35	0	52	0	0
T51	0	44	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	30	0	0
T94	0	12	0	0
T96	0	24	0	0
T97	0	68	0	0
T98	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	93655	0	0
T3	25937	238	0	0
T4	746	0	0	0
T7	17991	610	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	855	0	0
T17	402	0	0	0
T35	0	1292	0	0
T51	0	1122	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	1119	0	0
T94	0	534	0	0
T96	0	772	0	0
T97	0	1904	0	0
T98	0	1364	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5438464	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25504	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17562	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	430	0	0
T35	18631	8	0	0
T80	500	0	0	0
T87	533	0	0	0
T88	502	0	0	0
T89	522	0	0	0
T93	0	4	0	0
T96	0	2	0	0
T98	0	15	0	0
T119	0	25	0	0
T120	0	27	0	0
T121	0	12	0	0
T122	0	26	0	0
T123	0	25	0	0
T124	0	6	0	0
T209	871	0	0	0
T210	402	0	0	0
T211	402	0	0	0
T273	405	0	0	0
T274	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	61967	0	0
T3	25937	286	0	0
T4	746	0	0	0
T7	17991	1138	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1006	0	0
T17	402	0	0	0
T51	0	1632	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	181	0	0
T97	0	2280	0	0
T251	0	188	0	0
T270	0	1219	0	0
T272	0	542	0	0
T275	0	330	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	785	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	10	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	15	0	0
T17	402	0	0	0
T51	0	22	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	6	0	0
T97	0	34	0	0
T251	0	15	0	0
T270	0	22	0	0
T272	0	15	0	0
T275	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5008431	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	22389	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	11374	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5010246	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	22397	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	11376	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1515	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	10	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	15	0	0
T17	402	0	0	0
T35	0	26	0	0
T51	0	22	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	15	0	0
T94	0	6	0	0
T96	0	12	0	0
T97	0	34	0	0
T98	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1497	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	10	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	15	0	0
T17	402	0	0	0
T35	0	26	0	0
T51	0	22	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	15	0	0
T94	0	6	0	0
T96	0	12	0	0
T97	0	34	0	0
T98	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	785	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	10	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	15	0	0
T17	402	0	0	0
T51	0	22	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	6	0	0
T97	0	34	0	0
T251	0	15	0	0
T270	0	22	0	0
T272	0	15	0	0
T275	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	785	0	0
T3	25937	7	0	0
T4	746	0	0	0
T7	17991	10	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	15	0	0
T17	402	0	0	0
T51	0	22	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	6	0	0
T97	0	34	0	0
T251	0	15	0	0
T270	0	22	0	0
T272	0	15	0	0
T275	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	61096	0	0
T3	25937	278	0	0
T4	746	0	0	0
T7	17991	1126	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	990	0	0
T17	402	0	0	0
T51	0	1608	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	175	0	0
T97	0	2234	0	0
T251	0	173	0	0
T270	0	1196	0	0
T272	0	526	0	0
T275	0	321	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	698	0	0
T3	25937	6	0	0
T4	746	0	0	0
T7	17991	8	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	14	0	0
T17	402	0	0	0
T51	0	20	0	0
T62	405	0	0	0
T68	653	0	0	0
T94	0	6	0	0
T97	0	22	0	0
T251	0	15	0	0
T270	0	21	0	0
T272	0	14	0	0
T275	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T12,T53,T39
1	0	Covered	T105,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T1,T2,T52
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T7
1	-	Covered	T1,T2,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T1,T2,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T2,T52,T36
DetectSt->IdleSt	186	Covered	T12,T53,T39
DetectSt->StableSt	191	Covered	T1,T2,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T52,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T12,T53,T39
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T52
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	731	0	0
CntIncr_A	5916283	41174	0	0
CntNoWrap_A	5916283	5440744	0	0
DetectStDropOut_A	5916283	33	0	0
DetectedOut_A	5916283	10991	0	0
DetectedPulseOut_A	5916283	306	0	0
DisabledIdleSt_A	5916283	5118691	0	0
DisabledNoDetection_A	5916283	5120067	0	0
EnterDebounceSt_A	5916283	388	0	0
EnterDetectSt_A	5916283	343	0	0
EnterStableSt_A	5916283	306	0	0
PulseIsPulse_A	5916283	306	0	0
StayInStableSt	5916283	10643	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	262	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	731	0	0
T1	20180	6	0	0
T2	28487	20	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	4	0	0
T12	0	8	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T37	0	4	0	0
T38	0	10	0	0
T51	0	4	0	0
T52	0	23	0	0
T53	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	41174	0	0
T1	20180	315	0	0
T2	28487	532	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	162	0	0
T12	0	670	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	72	0	0
T17	402	0	0	0
T37	0	272	0	0
T38	0	635	0	0
T51	0	144	0	0
T52	0	2102	0	0
T53	0	109	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5440744	0	0
T1	20180	19759	0	0
T2	28487	28042	0	0
T3	25937	25518	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17578	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	33	0	0
T12	21456	4	0	0
T23	494	0	0	0
T24	492	0	0	0
T28	672	0	0	0
T39	0	3	0	0
T52	27581	0	0	0
T53	28178	1	0	0
T63	8402	0	0	0
T64	674	0	0	0
T65	980	0	0	0
T66	502	0	0	0
T127	0	5	0	0
T131	0	6	0	0
T276	0	1	0	0
T277	0	7	0	0
T278	0	5	0	0
T279	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	10991	0	0
T1	20180	14	0	0
T2	28487	121	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	97	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	70	0	0
T17	402	0	0	0
T36	0	123	0	0
T37	0	14	0	0
T38	0	303	0	0
T51	0	139	0	0
T52	0	63	0	0
T97	0	446	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	306	0	0
T1	20180	3	0	0
T2	28487	8	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1	0	0
T17	402	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	5	0	0
T51	0	2	0	0
T52	0	10	0	0
T97	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5118691	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	25233	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	16446	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5120067	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	25242	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	16449	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	388	0	0
T1	20180	3	0	0
T2	28487	12	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	4	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1	0	0
T17	402	0	0	0
T37	0	2	0	0
T38	0	5	0	0
T51	0	2	0	0
T52	0	13	0	0
T53	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	343	0	0
T1	20180	3	0	0
T2	28487	8	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	4	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1	0	0
T17	402	0	0	0
T37	0	2	0	0
T38	0	5	0	0
T51	0	2	0	0
T52	0	10	0	0
T53	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	306	0	0
T1	20180	3	0	0
T2	28487	8	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1	0	0
T17	402	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	5	0	0
T51	0	2	0	0
T52	0	10	0	0
T97	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	306	0	0
T1	20180	3	0	0
T2	28487	8	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1	0	0
T17	402	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	5	0	0
T51	0	2	0	0
T52	0	10	0	0
T97	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	10643	0	0
T1	20180	11	0	0
T2	28487	113	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	93	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	68	0	0
T17	402	0	0	0
T36	0	119	0	0
T37	0	12	0	0
T38	0	298	0	0
T51	0	137	0	0
T52	0	53	0	0
T97	0	426	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	262	0	0
T1	20180	3	0	0
T2	28487	8	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	5	0	0
T51	0	2	0	0
T52	0	10	0	0
T144	0	4	0	0
T280	0	6	0	0
T281	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T16
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T16
1	0	Covered	T3,T7,T16
1	1	Covered	T3,T7,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T16,T35,T119
1	0	Covered	T16,T35,T270

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T51
0	1	Covered	T3,T7,T51
1	0	Covered	T110

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T51
1	-	Covered	T3,T7,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T16
DetectSt	168	Covered	T3,T7,T16
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T7,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T16
DebounceSt->IdleSt	163	Covered	T105,T268,T67
DetectSt->IdleSt	186	Covered	T16,T35,T119
DetectSt->StableSt	191	Covered	T3,T7,T51
IdleSt->DebounceSt	148	Covered	T3,T7,T16
StableSt->IdleSt	206	Covered	T3,T7,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T16
0	1	Covered	T3,T7,T16
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T16
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T16
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T105,T268,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T35,T119
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T51
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T16
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T51
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T51
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	3108	0	0
CntIncr_A	5916283	98297	0	0
CntNoWrap_A	5916283	5438367	0	0
DetectStDropOut_A	5916283	351	0	0
DetectedOut_A	5916283	73639	0	0
DetectedPulseOut_A	5916283	974	0	0
DisabledIdleSt_A	5916283	4996390	0	0
DisabledNoDetection_A	5916283	4998201	0	0
EnterDebounceSt_A	5916283	1567	0	0
EnterDetectSt_A	5916283	1542	0	0
EnterStableSt_A	5916283	974	0	0
PulseIsPulse_A	5916283	974	0	0
StayInStableSt	5916283	72574	0	0
gen_high_event_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	878	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3108	0	0
T3	25937	30	0	0
T4	746	0	0	0
T7	17991	22	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	62	0	0
T17	402	0	0	0
T35	0	38	0	0
T51	0	64	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	62	0	0
T94	0	18	0	0
T96	0	14	0	0
T97	0	30	0	0
T98	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	98297	0	0
T3	25937	450	0	0
T4	746	0	0	0
T7	17991	649	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2593	0	0
T17	402	0	0	0
T35	0	940	0	0
T51	0	2560	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	1891	0	0
T94	0	477	0	0
T96	0	392	0	0
T97	0	600	0	0
T98	0	1025	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5438367	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25488	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17560	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	351	0	0
T8	612	0	0	0
T9	1451	0	0	0
T16	10468	15	0	0
T17	402	0	0	0
T25	526	0	0	0
T26	510	0	0	0
T34	1679	0	0	0
T35	0	6	0	0
T62	405	0	0	0
T68	653	0	0	0
T76	404	0	0	0
T119	0	10	0	0
T120	0	27	0	0
T121	0	19	0	0
T122	0	9	0	0
T123	0	6	0	0
T125	0	12	0	0
T126	0	13	0	0
T270	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	73639	0	0
T3	25937	1490	0	0
T4	746	0	0	0
T7	17991	1207	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T51	0	2397	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	1300	0	0
T94	0	402	0	0
T96	0	255	0	0
T97	0	1418	0	0
T98	0	1878	0	0
T251	0	1090	0	0
T272	0	2006	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	974	0	0
T3	25937	15	0	0
T4	746	0	0	0
T7	17991	11	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T51	0	32	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	31	0	0
T94	0	9	0	0
T96	0	7	0	0
T97	0	15	0	0
T98	0	25	0	0
T251	0	15	0	0
T272	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4996390	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	21421	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	11364	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4998201	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	21426	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	11366	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1567	0	0
T3	25937	15	0	0
T4	746	0	0	0
T7	17991	11	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	31	0	0
T17	402	0	0	0
T35	0	19	0	0
T51	0	32	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	31	0	0
T94	0	9	0	0
T96	0	7	0	0
T97	0	15	0	0
T98	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1542	0	0
T3	25937	15	0	0
T4	746	0	0	0
T7	17991	11	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	31	0	0
T17	402	0	0	0
T35	0	19	0	0
T51	0	32	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	31	0	0
T94	0	9	0	0
T96	0	7	0	0
T97	0	15	0	0
T98	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	974	0	0
T3	25937	15	0	0
T4	746	0	0	0
T7	17991	11	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T51	0	32	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	31	0	0
T94	0	9	0	0
T96	0	7	0	0
T97	0	15	0	0
T98	0	25	0	0
T251	0	15	0	0
T272	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	974	0	0
T3	25937	15	0	0
T4	746	0	0	0
T7	17991	11	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T51	0	32	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	31	0	0
T94	0	9	0	0
T96	0	7	0	0
T97	0	15	0	0
T98	0	25	0	0
T251	0	15	0	0
T272	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	72574	0	0
T3	25937	1471	0	0
T4	746	0	0	0
T7	17991	1194	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T51	0	2361	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	1269	0	0
T94	0	393	0	0
T96	0	247	0	0
T97	0	1401	0	0
T98	0	1852	0	0
T251	0	1072	0	0
T272	0	1984	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	878	0	0
T3	25937	11	0	0
T4	746	0	0	0
T7	17991	9	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T51	0	28	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	31	0	0
T94	0	9	0	0
T96	0	6	0	0
T97	0	13	0	0
T98	0	24	0	0
T251	0	12	0	0
T272	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T37,T39,T280
1	0	Covered	T105,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T67,T106

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T51,T93
DetectSt->IdleSt	186	Covered	T37,T39,T280
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T51,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T37,T39,T280
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	723	0	0
CntIncr_A	5916283	36744	0	0
CntNoWrap_A	5916283	5440752	0	0
DetectStDropOut_A	5916283	34	0	0
DetectedOut_A	5916283	13145	0	0
DetectedPulseOut_A	5916283	302	0	0
DisabledIdleSt_A	5916283	5104503	0	0
DisabledNoDetection_A	5916283	5105882	0	0
EnterDebounceSt_A	5916283	383	0	0
EnterDetectSt_A	5916283	340	0	0
EnterStableSt_A	5916283	302	0	0
PulseIsPulse_A	5916283	302	0	0
StayInStableSt	5916283	12817	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	723	0	0
T1	20180	2	0	0
T2	28487	13	0	0
T3	25937	8	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	4	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T37	0	6	0	0
T38	0	20	0	0
T52	0	2	0	0
T53	0	12	0	0
T54	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	36744	0	0
T1	20180	64	0	0
T2	28487	331	0	0
T3	25937	156	0	0
T4	746	0	0	0
T7	17991	69	0	0
T12	0	240	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T37	0	431	0	0
T38	0	1300	0	0
T52	0	97	0	0
T53	0	558	0	0
T54	0	395	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5440752	0	0
T1	20180	19763	0	0
T2	28487	28049	0	0
T3	25937	25510	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17580	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	34	0	0
T35	18631	0	0	0
T37	22727	3	0	0
T38	37173	0	0	0
T39	0	2	0	0
T41	649	0	0	0
T42	968	0	0	0
T54	15540	0	0	0
T87	533	0	0	0
T147	628	0	0	0
T148	402	0	0	0
T209	871	0	0	0
T278	0	3	0	0
T280	0	2	0	0
T282	0	1	0	0
T283	0	11	0	0
T284	0	2	0	0
T285	0	4	0	0
T286	0	3	0	0
T287	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	13145	0	0
T1	20180	45	0	0
T2	28487	82	0	0
T3	25937	299	0	0
T4	746	0	0	0
T7	17991	60	0	0
T12	0	94	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T38	0	581	0	0
T51	0	200	0	0
T52	0	93	0	0
T53	0	98	0	0
T54	0	126	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	302	0	0
T1	20180	1	0	0
T2	28487	6	0	0
T3	25937	4	0	0
T4	746	0	0	0
T7	17991	1	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T38	0	10	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5104503	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	24032	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	16377	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5105882	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	24038	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	16380	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	383	0	0
T1	20180	1	0	0
T2	28487	7	0	0
T3	25937	4	0	0
T4	746	0	0	0
T7	17991	1	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T37	0	3	0	0
T38	0	10	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	340	0	0
T1	20180	1	0	0
T2	28487	6	0	0
T3	25937	4	0	0
T4	746	0	0	0
T7	17991	1	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T37	0	3	0	0
T38	0	10	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	302	0	0
T1	20180	1	0	0
T2	28487	6	0	0
T3	25937	4	0	0
T4	746	0	0	0
T7	17991	1	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T38	0	10	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	302	0	0
T1	20180	1	0	0
T2	28487	6	0	0
T3	25937	4	0	0
T4	746	0	0	0
T7	17991	1	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T38	0	10	0	0
T51	0	4	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	12817	0	0
T1	20180	44	0	0
T2	28487	76	0	0
T3	25937	295	0	0
T4	746	0	0	0
T7	17991	58	0	0
T12	0	92	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T38	0	571	0	0
T51	0	194	0	0
T52	0	92	0	0
T53	0	92	0	0
T54	0	121	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	272	0	0
T1	20180	1	0	0
T2	28487	6	0	0
T3	25937	4	0	0
T4	746	0	0	0
T7	17991	0	0	0
T12	0	2	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T38	0	10	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	6	0	0
T54	0	5	0	0
T96	0	1	0	0