Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T7,T16
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T7,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T16
1	0	Covered	T3,T7,T16
1	1	Covered	T3,T7,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T96,T119,T120
1	0	Covered	T35,T96,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T16
0	1	Covered	T3,T7,T16
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T16
1	-	Covered	T3,T7,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T16
DetectSt	168	Covered	T3,T7,T16
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T7,T16

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T16
DebounceSt->IdleSt	163	Covered	T105,T268,T67
DetectSt->IdleSt	186	Covered	T35,T96,T98
DetectSt->StableSt	191	Covered	T3,T7,T16
IdleSt->DebounceSt	148	Covered	T3,T7,T16
StableSt->IdleSt	206	Covered	T3,T7,T16

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T16
0	1	Covered	T3,T7,T16
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T16
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T16
IdleSt	0	-	-	-	-	-	-	Covered	T3,T7,T16
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T105,T268,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T16
DetectSt	-	-	-	-	1	-	-	Covered	T35,T96,T98
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T16
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T16
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T16
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T16
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	3491	0	0
CntIncr_A	5916283	110439	0	0
CntNoWrap_A	5916283	5437984	0	0
DetectStDropOut_A	5916283	420	0	0
DetectedOut_A	5916283	84102	0	0
DetectedPulseOut_A	5916283	1031	0	0
DisabledIdleSt_A	5916283	4989538	0	0
DisabledNoDetection_A	5916283	4991302	0	0
EnterDebounceSt_A	5916283	1755	0	0
EnterDetectSt_A	5916283	1738	0	0
EnterStableSt_A	5916283	1031	0	0
PulseIsPulse_A	5916283	1031	0	0
StayInStableSt	5916283	82935	0	0
gen_high_event_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	895	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	3491	0	0
T3	25937	60	0	0
T4	746	0	0	0
T7	17991	50	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	52	0	0
T17	402	0	0	0
T35	0	64	0	0
T51	0	18	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	16	0	0
T94	0	22	0	0
T96	0	26	0	0
T97	0	20	0	0
T98	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	110439	0	0
T3	25937	1500	0	0
T4	746	0	0	0
T7	17991	2225	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	1378	0	0
T17	402	0	0	0
T35	0	1601	0	0
T51	0	477	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	456	0	0
T94	0	715	0	0
T96	0	840	0	0
T97	0	680	0	0
T98	0	480	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5437984	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	25458	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17532	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	420	0	0
T47	2047	0	0	0
T55	744	0	0	0
T92	512	0	0	0
T96	9855	3	0	0
T97	32674	0	0	0
T98	9028	0	0	0
T119	0	21	0	0
T120	0	22	0	0
T121	0	15	0	0
T122	0	10	0	0
T123	0	7	0	0
T125	0	6	0	0
T126	0	8	0	0
T144	15512	0	0	0
T154	25489	0	0	0
T155	553	0	0	0
T191	738	0	0	0
T254	0	25	0	0
T288	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	84102	0	0
T3	25937	1923	0	0
T4	746	0	0	0
T7	17991	1720	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2454	0	0
T17	402	0	0	0
T51	0	344	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	1124	0	0
T94	0	742	0	0
T97	0	127	0	0
T124	0	2402	0	0
T270	0	555	0	0
T272	0	1089	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1031	0	0
T3	25937	30	0	0
T4	746	0	0	0
T7	17991	25	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	26	0	0
T17	402	0	0	0
T51	0	9	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	8	0	0
T94	0	11	0	0
T97	0	10	0	0
T124	0	24	0	0
T270	0	12	0	0
T272	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4989538	0	0
T1	20180	19765	0	0
T2	28487	28062	0	0
T3	25937	20765	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	10764	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	4991302	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	20767	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	10766	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1755	0	0
T3	25937	30	0	0
T4	746	0	0	0
T7	17991	25	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	26	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	9	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	8	0	0
T94	0	11	0	0
T96	0	13	0	0
T97	0	10	0	0
T98	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1738	0	0
T3	25937	30	0	0
T4	746	0	0	0
T7	17991	25	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	26	0	0
T17	402	0	0	0
T35	0	32	0	0
T51	0	9	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	8	0	0
T94	0	11	0	0
T96	0	13	0	0
T97	0	10	0	0
T98	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1031	0	0
T3	25937	30	0	0
T4	746	0	0	0
T7	17991	25	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	26	0	0
T17	402	0	0	0
T51	0	9	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	8	0	0
T94	0	11	0	0
T97	0	10	0	0
T124	0	24	0	0
T270	0	12	0	0
T272	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	1031	0	0
T3	25937	30	0	0
T4	746	0	0	0
T7	17991	25	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	26	0	0
T17	402	0	0	0
T51	0	9	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	8	0	0
T94	0	11	0	0
T97	0	10	0	0
T124	0	24	0	0
T270	0	12	0	0
T272	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	82935	0	0
T3	25937	1886	0	0
T4	746	0	0	0
T7	17991	1693	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2427	0	0
T17	402	0	0	0
T51	0	335	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	1115	0	0
T94	0	730	0	0
T97	0	116	0	0
T124	0	2371	0	0
T270	0	543	0	0
T272	0	1063	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	895	0	0
T3	25937	23	0	0
T4	746	0	0	0
T7	17991	23	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	25	0	0
T17	402	0	0	0
T51	0	9	0	0
T62	405	0	0	0
T68	653	0	0	0
T93	0	7	0	0
T94	0	10	0	0
T97	0	9	0	0
T124	0	17	0	0
T270	0	12	0	0
T272	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T54,T263
1	0	Covered	T105,T67

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T3,T7
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T7
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T36,T154
DetectSt->IdleSt	186	Covered	T2,T54,T263
DetectSt->StableSt	191	Covered	T1,T3,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T105,T67
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T36,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T54,T263
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5916283	765	0	0
CntIncr_A	5916283	36386	0	0
CntNoWrap_A	5916283	5440710	0	0
DetectStDropOut_A	5916283	24	0	0
DetectedOut_A	5916283	14762	0	0
DetectedPulseOut_A	5916283	332	0	0
DisabledIdleSt_A	5916283	5099663	0	0
DisabledNoDetection_A	5916283	5101012	0	0
EnterDebounceSt_A	5916283	406	0	0
EnterDetectSt_A	5916283	359	0	0
EnterStableSt_A	5916283	332	0	0
PulseIsPulse_A	5916283	332	0	0
StayInStableSt	5916283	14391	0	0
gen_high_level_sva.HighLevelEvent_A	5916283	5443473	0	0
gen_not_sticky_sva.StableStDropOut_A	5916283	291	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	765	0	0
T1	20180	8	0	0
T2	28487	6	0	0
T3	25937	10	0	0
T4	746	0	0	0
T7	17991	4	0	0
T12	0	6	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	4	0	0
T17	402	0	0	0
T36	0	5	0	0
T37	0	4	0	0
T53	0	12	0	0
T54	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	36386	0	0
T1	20180	248	0	0
T2	28487	200	0	0
T3	25937	260	0	0
T4	746	0	0	0
T7	17991	114	0	0
T12	0	342	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	148	0	0
T17	402	0	0	0
T36	0	334	0	0
T37	0	154	0	0
T53	0	600	0	0
T54	0	312	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5440710	0	0
T1	20180	19757	0	0
T2	28487	28056	0	0
T3	25937	25508	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	17578	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	24	0	0
T2	28487	2	0	0
T3	25937	0	0	0
T4	746	0	0	0
T7	17991	0	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	0	0	0
T17	402	0	0	0
T54	0	3	0	0
T62	405	0	0	0
T105	0	1	0	0
T263	0	3	0	0
T278	0	2	0	0
T279	0	2	0	0
T289	0	3	0	0
T290	0	2	0	0
T291	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	14762	0	0
T1	20180	190	0	0
T2	28487	0	0	0
T3	25937	309	0	0
T4	746	0	0	0
T7	17991	149	0	0
T12	0	159	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	136	0	0
T17	402	0	0	0
T36	0	154	0	0
T37	0	132	0	0
T53	0	56	0	0
T93	0	53	0	0
T94	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	332	0	0
T1	20180	4	0	0
T2	28487	0	0	0
T3	25937	5	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	3	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T53	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5099663	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	23602	0	0
T4	746	345	0	0
T5	423	22	0	0
T6	422	21	0	0
T7	17991	15864	0	0
T13	527	126	0	0
T14	489	88	0	0
T15	404	3	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5101012	0	0
T1	20180	16113	0	0
T2	28487	26189	0	0
T3	25937	23605	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	15867	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	406	0	0
T1	20180	4	0	0
T2	28487	4	0	0
T3	25937	5	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	3	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T53	0	6	0	0
T54	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	359	0	0
T1	20180	4	0	0
T2	28487	2	0	0
T3	25937	5	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	3	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T53	0	6	0	0
T54	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	332	0	0
T1	20180	4	0	0
T2	28487	0	0	0
T3	25937	5	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	3	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T53	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	332	0	0
T1	20180	4	0	0
T2	28487	0	0	0
T3	25937	5	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	3	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T53	0	6	0	0
T93	0	1	0	0
T94	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	14391	0	0
T1	20180	186	0	0
T2	28487	0	0	0
T3	25937	304	0	0
T4	746	0	0	0
T7	17991	147	0	0
T12	0	156	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	134	0	0
T17	402	0	0	0
T36	0	152	0	0
T37	0	130	0	0
T53	0	50	0	0
T93	0	52	0	0
T94	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	5443473	0	0
T1	20180	19773	0	0
T2	28487	28075	0	0
T3	25937	25528	0	0
T4	746	346	0	0
T5	423	23	0	0
T6	422	22	0	0
T7	17991	17587	0	0
T13	527	127	0	0
T14	489	89	0	0
T15	404	4	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5916283	291	0	0
T1	20180	4	0	0
T2	28487	0	0	0
T3	25937	5	0	0
T4	746	0	0	0
T7	17991	2	0	0
T12	0	3	0	0
T13	527	0	0	0
T14	489	0	0	0
T15	404	0	0	0
T16	10468	2	0	0
T17	402	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T53	0	6	0	0
T93	0	1	0	0
T144	0	1	0	0