Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1213090441	10199	0	0
auto_block_debounce_ctl_rd_A	1213090441	2167	0	0
auto_block_out_ctl_rd_A	1213090441	2798	0	0
com_det_ctl_0_rd_A	1213090441	3967	0	0
com_det_ctl_1_rd_A	1213090441	3998	0	0
com_det_ctl_2_rd_A	1213090441	3878	0	0
com_det_ctl_3_rd_A	1213090441	4008	0	0
com_out_ctl_0_rd_A	1213090441	4575	0	0
com_out_ctl_1_rd_A	1213090441	4384	0	0
com_out_ctl_2_rd_A	1213090441	4367	0	0
com_out_ctl_3_rd_A	1213090441	4440	0	0
com_pre_det_ctl_0_rd_A	1213090441	1567	0	0
com_pre_det_ctl_1_rd_A	1213090441	1662	0	0
com_pre_det_ctl_2_rd_A	1213090441	1702	0	0
com_pre_det_ctl_3_rd_A	1213090441	1735	0	0
com_pre_sel_ctl_0_rd_A	1213090441	4839	0	0
com_pre_sel_ctl_1_rd_A	1213090441	4625	0	0
com_pre_sel_ctl_2_rd_A	1213090441	4675	0	0
com_pre_sel_ctl_3_rd_A	1213090441	4879	0	0
com_sel_ctl_0_rd_A	1213090441	4736	0	0
com_sel_ctl_1_rd_A	1213090441	4688	0	0
com_sel_ctl_2_rd_A	1213090441	4487	0	0
com_sel_ctl_3_rd_A	1213090441	4745	0	0
ec_rst_ctl_rd_A	1213090441	2411	0	0
intr_enable_rd_A	1213090441	1960	0	0
key_intr_ctl_rd_A	1213090441	4138	0	0
key_intr_debounce_ctl_rd_A	1213090441	1750	0	0
key_invert_ctl_rd_A	1213090441	4449	0	0
pin_allowed_ctl_rd_A	1213090441	5252	0	0
pin_out_ctl_rd_A	1213090441	4278	0	0
pin_out_value_rd_A	1213090441	4036	0	0
regwen_rd_A	1213090441	1637	0	0
ulp_ac_debounce_ctl_rd_A	1213090441	1758	0	0
ulp_ctl_rd_A	1213090441	1610	0	0
ulp_lid_debounce_ctl_rd_A	1213090441	1754	0	0
ulp_pwrb_debounce_ctl_rd_A	1213090441	1730	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	10199	0	0
T47	255911	5	0	0
T55	171272	0	0	0
T57	0	7	0	0
T73	0	16	0	0
T92	11416	0	0	0
T98	767432	0	0	0
T144	775651	0	0	0
T154	943071	0	0	0
T155	265521	0	0	0
T191	361942	0	0	0
T192	181603	5	0	0
T193	352319	7	0	0
T262	0	8	0	0
T317	0	4	0	0
T318	0	15	0	0
T319	0	8	0	0
T320	0	19	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	2167	0	0
T21	63277	0	0	0
T28	16815	21	0	0
T37	113635	0	0	0
T41	294214	0	0	0
T52	135150	0	0	0
T53	676290	0	0	0
T61	0	12	0	0
T65	475603	0	0	0
T66	251051	0	0	0
T146	143647	0	0	0
T192	0	19	0	0
T193	0	28	0	0
T262	0	19	0	0
T316	15535	0	0	0
T317	0	13	0	0
T321	0	3	0	0
T322	0	31	0	0
T323	0	29	0	0
T324	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	2798	0	0
T21	63277	0	0	0
T28	16815	6	0	0
T37	113635	0	0	0
T41	294214	0	0	0
T52	135150	0	0	0
T53	676290	0	0	0
T61	0	11	0	0
T65	475603	0	0	0
T66	251051	0	0	0
T146	143647	0	0	0
T192	0	12	0	0
T193	0	15	0	0
T262	0	11	0	0
T316	15535	0	0	0
T317	0	3	0	0
T321	0	8	0	0
T322	0	37	0	0
T323	0	49	0	0
T324	0	16	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	3967	0	0
T2	299120	82	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	103	0	0
T62	48665	0	0	0
T93	0	57	0	0
T94	0	18	0	0
T154	0	44	0	0
T192	0	25	0	0
T193	0	12	0	0
T262	0	34	0	0
T280	0	66	0	0
T317	0	6	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	3998	0	0
T2	299120	75	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	149	0	0
T62	48665	0	0	0
T93	0	17	0	0
T94	0	45	0	0
T154	0	26	0	0
T192	0	26	0	0
T193	0	13	0	0
T251	0	55	0	0
T262	0	24	0	0
T280	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	3878	0	0
T2	299120	73	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	134	0	0
T62	48665	0	0	0
T93	0	38	0	0
T94	0	32	0	0
T154	0	42	0	0
T192	0	12	0	0
T193	0	5	0	0
T262	0	19	0	0
T280	0	79	0	0
T317	0	24	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4008	0	0
T2	299120	60	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	143	0	0
T62	48665	0	0	0
T93	0	25	0	0
T94	0	48	0	0
T154	0	48	0	0
T192	0	20	0	0
T193	0	31	0	0
T262	0	14	0	0
T280	0	58	0	0
T317	0	1	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4575	0	0
T2	299120	86	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	158	0	0
T62	48665	0	0	0
T93	0	23	0	0
T94	0	32	0	0
T154	0	45	0	0
T192	0	17	0	0
T193	0	15	0	0
T262	0	24	0	0
T280	0	60	0	0
T317	0	11	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4384	0	0
T2	299120	79	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	94	0	0
T62	48665	0	0	0
T93	0	29	0	0
T94	0	30	0	0
T154	0	16	0	0
T192	0	25	0	0
T193	0	27	0	0
T262	0	29	0	0
T280	0	52	0	0
T317	0	12	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4367	0	0
T2	299120	76	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	104	0	0
T62	48665	0	0	0
T93	0	33	0	0
T94	0	37	0	0
T154	0	20	0	0
T192	0	36	0	0
T193	0	8	0	0
T262	0	11	0	0
T280	0	50	0	0
T317	0	12	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4440	0	0
T2	299120	69	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	97	0	0
T62	48665	0	0	0
T93	0	21	0	0
T94	0	47	0	0
T154	0	38	0	0
T192	0	22	0	0
T193	0	21	0	0
T251	0	59	0	0
T262	0	9	0	0
T280	0	71	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1567	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	24	0	0
T193	352319	11	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	43	0	0
T262	0	17	0	0
T298	0	20	0	0
T317	0	11	0	0
T322	0	37	0	0
T323	0	48	0	0
T325	0	26	0	0
T326	0	17	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1662	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	40	0	0
T193	352319	34	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	42	0	0
T262	0	11	0	0
T298	0	10	0	0
T317	0	2	0	0
T322	0	30	0	0
T323	0	29	0	0
T325	0	25	0	0
T326	0	12	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1702	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	25	0	0
T193	352319	18	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	29	0	0
T262	0	25	0	0
T298	0	23	0	0
T317	0	1	0	0
T322	0	21	0	0
T323	0	35	0	0
T325	0	24	0	0
T326	0	17	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1735	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	23	0	0
T193	352319	33	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	38	0	0
T262	0	18	0	0
T298	0	11	0	0
T317	0	8	0	0
T322	0	34	0	0
T323	0	30	0	0
T325	0	18	0	0
T326	0	3	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4839	0	0
T2	299120	84	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	171	0	0
T62	48665	0	0	0
T93	0	26	0	0
T94	0	31	0	0
T154	0	43	0	0
T192	0	21	0	0
T193	0	10	0	0
T262	0	21	0	0
T280	0	76	0	0
T317	0	17	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4625	0	0
T2	299120	67	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	173	0	0
T62	48665	0	0	0
T93	0	30	0	0
T94	0	37	0	0
T154	0	59	0	0
T192	0	6	0	0
T193	0	44	0	0
T262	0	15	0	0
T280	0	62	0	0
T317	0	10	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4675	0	0
T2	299120	57	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	148	0	0
T62	48665	0	0	0
T93	0	14	0	0
T94	0	30	0	0
T154	0	20	0	0
T192	0	19	0	0
T193	0	13	0	0
T262	0	18	0	0
T280	0	64	0	0
T317	0	17	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4879	0	0
T2	299120	102	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	153	0	0
T62	48665	0	0	0
T93	0	27	0	0
T94	0	19	0	0
T154	0	41	0	0
T192	0	14	0	0
T193	0	27	0	0
T251	0	67	0	0
T262	0	17	0	0
T280	0	84	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4736	0	0
T2	299120	66	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	141	0	0
T62	48665	0	0	0
T93	0	39	0	0
T94	0	25	0	0
T154	0	29	0	0
T192	0	23	0	0
T193	0	20	0	0
T262	0	13	0	0
T280	0	66	0	0
T317	0	10	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4688	0	0
T2	299120	87	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	156	0	0
T62	48665	0	0	0
T93	0	26	0	0
T94	0	29	0	0
T154	0	54	0	0
T192	0	23	0	0
T193	0	23	0	0
T262	0	27	0	0
T280	0	71	0	0
T317	0	9	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4487	0	0
T2	299120	65	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	149	0	0
T62	48665	0	0	0
T93	0	33	0	0
T94	0	38	0	0
T154	0	24	0	0
T192	0	8	0	0
T193	0	36	0	0
T262	0	23	0	0
T280	0	71	0	0
T317	0	1	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4745	0	0
T2	299120	69	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	151	0	0
T62	48665	0	0	0
T93	0	39	0	0
T94	0	24	0	0
T154	0	43	0	0
T192	0	5	0	0
T193	0	14	0	0
T262	0	13	0	0
T280	0	65	0	0
T317	0	7	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	2411	0	0
T2	299120	51	0	0
T3	127093	0	0	0
T4	139783	0	0	0
T7	854591	0	0	0
T13	47548	0	0	0
T14	239971	0	0	0
T15	97214	0	0	0
T16	502460	0	0	0
T17	193382	0	0	0
T39	0	23	0	0
T43	0	4	0	0
T62	48665	0	0	0
T93	0	5	0	0
T94	0	5	0	0
T154	0	20	0	0
T155	0	1	0	0
T192	0	9	0	0
T193	0	25	0	0
T327	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1960	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	31	0	0
T193	352319	23	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	39	0	0
T262	0	26	0	0
T298	0	25	0	0
T317	0	11	0	0
T322	0	31	0	0
T323	0	27	0	0
T325	0	25	0	0
T326	0	14	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4138	0	0
T35	875672	0	0	0
T38	464667	0	0	0
T39	0	4	0	0
T41	294214	6	0	0
T42	20852	0	0	0
T45	0	4	0	0
T54	388496	0	0	0
T87	31971	0	0	0
T88	243573	0	0	0
T107	0	2	0	0
T147	78568	0	0	0
T148	193291	0	0	0
T167	0	3	0	0
T186	0	7	0	0
T192	0	22	0	0
T193	0	17	0	0
T209	104577	0	0	0
T262	0	19	0	0
T317	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1750	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	21	0	0
T193	352319	19	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	48	0	0
T262	0	15	0	0
T298	0	19	0	0
T317	0	19	0	0
T322	0	27	0	0
T323	0	28	0	0
T325	0	24	0	0
T326	0	7	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4449	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T163	0	73	0	0
T192	181603	26	0	0
T193	352319	11	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T262	0	22	0	0
T298	0	18	0	0
T317	0	89	0	0
T322	0	40	0	0
T323	0	42	0	0
T328	0	55	0	0
T329	0	58	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	5252	0	0
T21	63277	0	0	0
T37	113635	0	0	0
T41	294214	0	0	0
T42	20852	0	0	0
T53	676290	0	0	0
T66	251051	38	0	0
T88	0	74	0	0
T146	143647	0	0	0
T147	78568	0	0	0
T148	193291	0	0	0
T192	0	11	0	0
T193	0	18	0	0
T195	0	59	0	0
T262	0	21	0	0
T316	15535	0	0	0
T317	0	1	0	0
T322	0	43	0	0
T330	0	57	0	0
T331	0	58	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4278	0	0
T21	63277	0	0	0
T37	113635	0	0	0
T41	294214	0	0	0
T42	20852	0	0	0
T53	676290	0	0	0
T66	251051	34	0	0
T88	0	57	0	0
T146	143647	0	0	0
T147	78568	0	0	0
T148	193291	0	0	0
T192	0	27	0	0
T193	0	29	0	0
T195	0	74	0	0
T219	0	20	0	0
T262	0	20	0	0
T316	15535	0	0	0
T322	0	33	0	0
T330	0	38	0	0
T331	0	81	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	4036	0	0
T21	63277	0	0	0
T37	113635	0	0	0
T41	294214	0	0	0
T42	20852	0	0	0
T53	676290	0	0	0
T66	251051	43	0	0
T88	0	81	0	0
T146	143647	0	0	0
T147	78568	0	0	0
T148	193291	0	0	0
T192	0	10	0	0
T193	0	11	0	0
T195	0	93	0	0
T262	0	29	0	0
T316	15535	0	0	0
T317	0	6	0	0
T322	0	35	0	0
T330	0	50	0	0
T331	0	68	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1637	0	0
T39	198549	0	0	0
T90	60818	0	0	0
T119	242170	0	0	0
T120	607194	0	0	0
T192	181603	23	0	0
T193	352319	12	0	0
T224	98899	0	0	0
T225	53200	0	0	0
T226	202658	0	0	0
T233	199422	0	0	0
T247	0	27	0	0
T262	0	18	0	0
T298	0	16	0	0
T304	0	38	0	0
T322	0	30	0	0
T323	0	39	0	0
T325	0	28	0	0
T326	0	9	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1758	0	0
T10	314716	0	0	0
T11	213331	0	0	0
T12	525682	0	0	0
T22	0	9	0	0
T27	72428	0	0	0
T34	51416	8	0	0
T69	76561	0	0	0
T70	109049	0	0	0
T77	47183	0	0	0
T78	258437	0	0	0
T79	38544	0	0	0
T103	0	5	0	0
T116	0	6	0	0
T192	0	14	0	0
T193	0	6	0	0
T262	0	29	0	0
T317	0	8	0	0
T321	0	2	0	0
T322	0	32	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1610	0	0
T10	314716	0	0	0
T11	213331	0	0	0
T12	525682	0	0	0
T22	0	3	0	0
T27	72428	0	0	0
T34	51416	4	0	0
T69	76561	0	0	0
T70	109049	0	0	0
T77	47183	0	0	0
T78	258437	0	0	0
T79	38544	0	0	0
T99	0	8	0	0
T100	0	4	0	0
T192	0	19	0	0
T193	0	20	0	0
T262	0	17	0	0
T317	0	8	0	0
T321	0	1	0	0
T322	0	29	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1754	0	0
T22	229229	5	0	0
T47	255911	0	0	0
T55	171272	0	0	0
T92	11416	0	0	0
T96	591369	0	0	0
T97	816877	0	0	0
T98	767432	0	0	0
T99	0	3	0	0
T100	0	11	0	0
T103	0	9	0	0
T144	775651	0	0	0
T154	943071	0	0	0
T155	265521	0	0	0
T192	0	22	0	0
T193	0	23	0	0
T262	0	13	0	0
T317	0	8	0	0
T321	0	5	0	0
T322	0	28	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1213090441	1730	0	0
T10	314716	0	0	0
T11	213331	0	0	0
T12	525682	0	0	0
T22	0	1	0	0
T27	72428	0	0	0
T34	51416	8	0	0
T69	76561	0	0	0
T70	109049	0	0	0
T77	47183	0	0	0
T78	258437	0	0	0
T79	38544	0	0	0
T99	0	2	0	0
T103	0	5	0	0
T192	0	18	0	0
T193	0	10	0	0
T262	0	19	0	0
T317	0	9	0	0
T321	0	1	0	0
T322	0	28	0	0