Unified Coverage Report :: Cond split page

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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T264,T265,T266
1	1	Covered	T4,T5,T1

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T267,T169,T268
1	0	Covered	T269,T270,T271

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T267,T169,T268
0	1	0	Covered	T269,T270,T271
1	0	0	Covered	T267,T169,T268

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T269,T270,T271
0	1	0	Covered	T120,T272,T132
1	0	0	Covered	T264,T265,T266

 LINE       1952
 EXPRESSION (aon_ec_rst_ctl_we & aon_ec_rst_ctl_regwen)
             --------1--------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T5,T2,T13

 LINE       1983
 EXPRESSION (aon_ulp_ac_debounce_ctl_we & aon_ulp_ac_debounce_ctl_regwen)
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T273,T269
1	1	Covered	T1,T21,T22

 LINE       2015
 EXPRESSION (aon_ulp_lid_debounce_ctl_we & aon_ulp_lid_debounce_ctl_regwen)
             -------------1-------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T1,T21,T22

 LINE       2047
 EXPRESSION (aon_ulp_pwrb_debounce_ctl_we & aon_ulp_pwrb_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T1,T21,T22

 LINE       2165
 EXPRESSION (aon_key_invert_ctl_we & aon_key_invert_ctl_regwen)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T273,T269
1	1	Covered	T6,T23,T24

 LINE       2494
 EXPRESSION (aon_pin_allowed_ctl_we & aon_pin_allowed_ctl_regwen)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T4,T6,T26

 LINE       3585
 EXPRESSION (aon_key_intr_ctl_we & aon_key_intr_ctl_regwen)
             ---------1---------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T273,T269
1	1	Covered	T6,T9,T11

 LINE       3968
 EXPRESSION (aon_key_intr_debounce_ctl_we & aon_key_intr_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T2,T3,T15

 LINE       4000
 EXPRESSION (aon_auto_block_debounce_ctl_we & aon_auto_block_debounce_ctl_regwen)
             ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T273,T269
1	1	Covered	T27,T28,T29

 LINE       4060
 EXPRESSION (aon_auto_block_out_ctl_we & aon_auto_block_out_ctl_regwen)
             ------------1------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T31,T273
1	1	Covered	T27,T28,T29

 LINE       4229
 EXPRESSION (aon_com_pre_sel_ctl_0_we & aon_com_pre_sel_ctl_0_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T3,T16,T7

 LINE       4370
 EXPRESSION (aon_com_pre_sel_ctl_1_we & aon_com_pre_sel_ctl_1_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T3,T16,T7

 LINE       4511
 EXPRESSION (aon_com_pre_sel_ctl_2_we & aon_com_pre_sel_ctl_2_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T3,T16,T7

 LINE       4652
 EXPRESSION (aon_com_pre_sel_ctl_3_we & aon_com_pre_sel_ctl_3_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T273,T269
1	1	Covered	T3,T16,T7

 LINE       4793
 EXPRESSION (aon_com_pre_det_ctl_0_we & aon_com_pre_det_ctl_0_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T3,T16,T7

 LINE       4825
 EXPRESSION (aon_com_pre_det_ctl_1_we & aon_com_pre_det_ctl_1_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T3,T16,T7

 LINE       4857
 EXPRESSION (aon_com_pre_det_ctl_2_we & aon_com_pre_det_ctl_2_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T273,T269
1	1	Covered	T3,T16,T7

 LINE       4889
 EXPRESSION (aon_com_pre_det_ctl_3_we & aon_com_pre_det_ctl_3_regwen)
             ------------1-----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T3,T16,T7

 LINE       4921
 EXPRESSION (aon_com_sel_ctl_0_we & aon_com_sel_ctl_0_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T2,T3,T15

 LINE       5062
 EXPRESSION (aon_com_sel_ctl_1_we & aon_com_sel_ctl_1_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T31,T273,T269
1	1	Covered	T2,T3,T16

 LINE       5203
 EXPRESSION (aon_com_sel_ctl_2_we & aon_com_sel_ctl_2_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T31,T273
1	1	Covered	T2,T3,T16

 LINE       5344
 EXPRESSION (aon_com_sel_ctl_3_we & aon_com_sel_ctl_3_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T2,T3,T16

 LINE       5485
 EXPRESSION (aon_com_det_ctl_0_we & aon_com_det_ctl_0_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T30,T273,T269
1	1	Covered	T2,T3,T15

 LINE       5517
 EXPRESSION (aon_com_det_ctl_1_we & aon_com_det_ctl_1_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T2,T3,T16

 LINE       5549
 EXPRESSION (aon_com_det_ctl_2_we & aon_com_det_ctl_2_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T31,T273
1	1	Covered	T2,T3,T16

 LINE       5581
 EXPRESSION (aon_com_det_ctl_3_we & aon_com_det_ctl_3_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T31,T273
1	1	Covered	T2,T3,T16

 LINE       5613
 EXPRESSION (aon_com_out_ctl_0_we & aon_com_out_ctl_0_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T273
1	1	Covered	T2,T3,T15

 LINE       5727
 EXPRESSION (aon_com_out_ctl_1_we & aon_com_out_ctl_1_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T273,T269
1	1	Covered	T2,T3,T16

 LINE       5841
 EXPRESSION (aon_com_out_ctl_2_we & aon_com_out_ctl_2_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T31,T273
1	1	Covered	T2,T3,T16

 LINE       5955
 EXPRESSION (aon_com_out_ctl_3_we & aon_com_out_ctl_3_regwen)
             ----------1---------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T30,T31
1	1	Covered	T2,T3,T16

 LINE       6559
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       6560
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       6561
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6562
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T14

 LINE       6563
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_REGWEN_OFFSET)
            ------------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6564
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_EC_RST_CTL_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T2

 LINE       6565
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_OFFSET)
            ------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       6566
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6567
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6568
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_CTL_OFFSET)
            ------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       6569
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_STATUS_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6570
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_WKUP_STATUS_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6571
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INVERT_CTL_OFFSET)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6572
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_ALLOWED_CTL_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       6573
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_CTL_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       6574
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_VALUE_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       6575
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_IN_VALUE_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T72

 LINE       6576
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_CTL_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6577
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6578
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET)
            --------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6579
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_OFFSET)
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6580
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6581
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6582
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6583
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6584
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6585
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6586
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       6587
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6588
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6589
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6590
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6591
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6592
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6593
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6594
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6595
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6596
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_0_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6597
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_1_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6598
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_2_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       6599
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_3_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6600
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COMBO_INTR_STATUS_OFFSET)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       6601
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_STATUS_OFFSET)
            ----------------------------------1----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T6

 LINE       6604
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       6604
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1

 LINE       6608
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T120,T272,T132

 LINE       6608
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b0011 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T4,T5,T1
43 (addr_hit[42] & ((\|(4'...	Covered	T1,T2,T6
42 (addr_hit[41] & ((\|(4'...	Covered	T1,T2,T3
41 (addr_hit[40] & ((\|(4'...	Covered	T1,T2,T3
40 (addr_hit[39] & ((\|(4'...	Covered	T1,T2,T13
39 (addr_hit[38] & ((\|(4'...	Covered	T1,T2,T3
38 (addr_hit[37] & ((\|(4'...	Covered	T1,T2,T3
37 (addr_hit[36] & ((\|(4'...	Covered	T1,T2,T3
36 (addr_hit[35] & ((\|(4'...	Covered	T1,T2,T3
35 (addr_hit[34] & ((\|(4'...	Covered	T1,T2,T3
34 (addr_hit[33] & ((\|(4'...	Covered	T1,T2,T3
33 (addr_hit[32] & ((\|(4'...	Covered	T1,T2,T3
32 (addr_hit[31] & ((\|(4'...	Covered	T1,T2,T3
31 (addr_hit[30] & ((\|(4'...	Covered	T1,T2,T3
30 (addr_hit[29] & ((\|(4'...	Covered	T1,T2,T3
29 (addr_hit[28] & ((\|(4'...	Covered	T1,T2,T6
28 (addr_hit[27] & ((\|(4'...	Covered	T1,T2,T13
27 (addr_hit[26] & ((\|(4'...	Covered	T1,T2,T6
26 (addr_hit[25] & ((\|(4'...	Covered	T1,T2,T6
25 (addr_hit[24] & ((\|(4'...	Covered	T1,T2,T3
24 (addr_hit[23] & ((\|(4'...	Covered	T1,T2,T3
23 (addr_hit[22] & ((\|(4'...	Covered	T1,T2,T3
22 (addr_hit[21] & ((\|(4'...	Covered	T1,T2,T3
21 (addr_hit[20] & ((\|(4'...	Covered	T1,T2,T6
20 (addr_hit[19] & ((\|(4'...	Covered	T1,T2,T6
19 (addr_hit[18] & ((\|(4'...	Covered	T1,T2,T6
18 (addr_hit[17] & ((\|(4'...	Covered	T1,T2,T6
17 (addr_hit[16] & ((\|(4'...	Covered	T1,T2,T46
16 (addr_hit[15] & ((\|(4'...	Covered	T4,T1,T2
15 (addr_hit[14] & ((\|(4'...	Covered	T4,T1,T2
14 (addr_hit[13] & ((\|(4'...	Covered	T4,T1,T2
13 (addr_hit[12] & ((\|(4'...	Covered	T1,T2,T6
12 (addr_hit[11] & ((\|(4'...	Covered	T1,T2,T3
11 (addr_hit[10] & ((\|(4'...	Covered	T1,T2,T6
10 (addr_hit[9] & ((\|(4'b...	Covered	T1,T2,T6
9 (addr_hit[8] & ((\|(4'b...	Covered	T1,T2,T6
8 (addr_hit[7] & ((\|(4'b...	Covered	T1,T2,T6
7 (addr_hit[6] & ((\|(4'b...	Covered	T1,T2,T13
6 (addr_hit[5] & ((\|(4'b...	Covered	T1,T2,T3
5 (addr_hit[4] & ((\|(4'b...	Covered	T1,T2,T6
4 (addr_hit[3] & ((\|(4'b...	Covered	T1,T2,T6
3 (addr_hit[2] & ((\|(4'b...	Covered	T1,T2,T6
2 (addr_hit[1] & ((\|(4'b...	Covered	T1,T2,T6
1 (addr_hit[0] & ((\|(4'b...	Covered	T5,T1,T2

 LINE       6608
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T5,T1,T2

 LINE       6608
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T13

 LINE       6608
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       6608
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T1,T2

 LINE       6608
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       6608
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T72
1	1	Covered	T1,T2,T46

 LINE       6608
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T13

 LINE       6608
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T6,T16
1	1	Covered	T1,T2,T6

 LINE       6608
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T2,T3,T6
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T13

 LINE       6608
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       6608
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T6,T72
1	1	Covered	T1,T2,T6

 LINE       6655
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T274,T275,T276
1	1	1	Covered	T4,T2,T13

 LINE       6658
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T266,T277,T278
1	1	1	Covered	T6,T49,T279

 LINE       6661
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T14
1	1	0	Covered	T264,T265,T266
1	1	1	Covered	T14,T17,T55

 LINE       6664
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T265,T266,T277
1	1	1	Covered	T18,T30,T31

 LINE       6667
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T5,T1,T2
1	1	0	Covered	T266,T278,T274
1	1	1	Covered	T5,T2,T13

 LINE       6669
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T13
1	1	0	Covered	T265,T280,T278
1	1	1	Covered	T1,T21,T22

 LINE       6671
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T266,T278,T271
1	1	1	Covered	T1,T21,T22

 LINE       6673
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T264,T266,T278
1	1	1	Covered	T1,T21,T22

 LINE       6675
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T13
1	1	0	Covered	T264,T265,T278
1	1	1	Covered	T1,T21,T22

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T6
1	1	0	Covered	T265,T277,T274
1	1	1	Covered	T1,T21,T22