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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.85 99.23 96.33 100.00 96.79 98.60 99.33 87.66


Total test records in report: 915
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T17 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1745598058 Aug 19 04:28:06 PM PDT 24 Aug 19 04:28:12 PM PDT 24 2048165349 ps
T249 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.799386204 Aug 19 04:28:17 PM PDT 24 Aug 19 04:28:19 PM PDT 24 2170588908 ps
T18 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3450315667 Aug 19 04:28:18 PM PDT 24 Aug 19 04:28:35 PM PDT 24 8800677713 ps
T23 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.104723740 Aug 19 04:28:19 PM PDT 24 Aug 19 04:29:33 PM PDT 24 76620930240 ps
T54 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2256085927 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2050772263 ps
T266 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4260337258 Aug 19 04:27:55 PM PDT 24 Aug 19 04:27:57 PM PDT 24 2109857510 ps
T250 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1086057486 Aug 19 04:28:10 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2081020534 ps
T19 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.691470926 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:20 PM PDT 24 9619057287 ps
T792 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.687112328 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2015722381 ps
T325 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1796215470 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:25 PM PDT 24 7017500257 ps
T793 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.349040723 Aug 19 04:28:28 PM PDT 24 Aug 19 04:28:30 PM PDT 24 2043500905 ps
T794 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.34593495 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:36 PM PDT 24 2012980301 ps
T251 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1372474232 Aug 19 04:28:16 PM PDT 24 Aug 19 04:28:47 PM PDT 24 42516049736 ps
T795 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.579712179 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:29 PM PDT 24 2037055373 ps
T255 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2658466225 Aug 19 04:28:22 PM PDT 24 Aug 19 04:29:01 PM PDT 24 22236282686 ps
T796 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.448058279 Aug 19 04:28:04 PM PDT 24 Aug 19 04:28:05 PM PDT 24 2136436119 ps
T797 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.701872985 Aug 19 04:28:28 PM PDT 24 Aug 19 04:28:30 PM PDT 24 2029010260 ps
T264 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.288953312 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:29 PM PDT 24 2119856171 ps
T256 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1871248349 Aug 19 04:28:28 PM PDT 24 Aug 19 04:29:29 PM PDT 24 42394110428 ps
T331 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3213716936 Aug 19 04:28:45 PM PDT 24 Aug 19 04:31:41 PM PDT 24 38803293096 ps
T326 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2601409353 Aug 19 04:28:34 PM PDT 24 Aug 19 04:29:00 PM PDT 24 10699818106 ps
T259 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.139767786 Aug 19 04:27:56 PM PDT 24 Aug 19 04:28:00 PM PDT 24 2050518477 ps
T262 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2534166754 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:34 PM PDT 24 22273695376 ps
T798 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.604629181 Aug 19 04:28:23 PM PDT 24 Aug 19 04:28:28 PM PDT 24 2008644524 ps
T799 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1084802412 Aug 19 04:28:12 PM PDT 24 Aug 19 04:28:19 PM PDT 24 2081724354 ps
T260 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2527133584 Aug 19 04:28:04 PM PDT 24 Aug 19 04:28:11 PM PDT 24 2137949563 ps
T800 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1623931526 Aug 19 04:28:25 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2042815541 ps
T327 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2109420772 Aug 19 04:27:57 PM PDT 24 Aug 19 04:28:08 PM PDT 24 4372559138 ps
T801 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3472040044 Aug 19 04:28:17 PM PDT 24 Aug 19 04:28:19 PM PDT 24 2033162353 ps
T802 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1878257907 Aug 19 04:27:58 PM PDT 24 Aug 19 04:28:00 PM PDT 24 2037944137 ps
T267 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.71466550 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:35 PM PDT 24 42534331573 ps
T803 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3287453682 Aug 19 04:28:18 PM PDT 24 Aug 19 04:28:21 PM PDT 24 2026005664 ps
T261 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2491137055 Aug 19 04:28:21 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2051927573 ps
T265 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1554838592 Aug 19 04:28:08 PM PDT 24 Aug 19 04:29:03 PM PDT 24 22248697247 ps
T804 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1615144464 Aug 19 04:28:18 PM PDT 24 Aug 19 04:28:20 PM PDT 24 2033416534 ps
T328 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.870585751 Aug 19 04:28:35 PM PDT 24 Aug 19 04:28:47 PM PDT 24 4704903021 ps
T805 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1455562561 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:28 PM PDT 24 2031653911 ps
T263 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2786750741 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:53 PM PDT 24 2134594148 ps
T806 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.238107056 Aug 19 04:28:17 PM PDT 24 Aug 19 04:28:23 PM PDT 24 2010360936 ps
T807 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.133564632 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:14 PM PDT 24 2055635857 ps
T808 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1201605978 Aug 19 04:28:22 PM PDT 24 Aug 19 04:28:32 PM PDT 24 22377272213 ps
T809 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1600527660 Aug 19 04:27:56 PM PDT 24 Aug 19 04:28:25 PM PDT 24 77478307662 ps
T329 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3438684334 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:21 PM PDT 24 4937571307 ps
T810 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3393120563 Aug 19 04:28:34 PM PDT 24 Aug 19 04:28:40 PM PDT 24 2011924713 ps
T811 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1910907726 Aug 19 04:28:18 PM PDT 24 Aug 19 04:28:20 PM PDT 24 2031152493 ps
T812 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1269944546 Aug 19 04:28:03 PM PDT 24 Aug 19 04:28:09 PM PDT 24 2016527876 ps
T813 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3922078969 Aug 19 04:29:05 PM PDT 24 Aug 19 04:29:11 PM PDT 24 2012640124 ps
T814 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.201422895 Aug 19 04:28:19 PM PDT 24 Aug 19 04:28:23 PM PDT 24 2022511479 ps
T815 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.812729667 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:21 PM PDT 24 2039808656 ps
T816 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2025909747 Aug 19 04:28:17 PM PDT 24 Aug 19 04:28:21 PM PDT 24 2025072839 ps
T817 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3847819111 Aug 19 04:28:51 PM PDT 24 Aug 19 04:28:55 PM PDT 24 2610636490 ps
T818 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2405836988 Aug 19 04:28:29 PM PDT 24 Aug 19 04:28:37 PM PDT 24 2125417651 ps
T819 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1282631222 Aug 19 04:28:23 PM PDT 24 Aug 19 04:28:29 PM PDT 24 2041314451 ps
T820 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.106280241 Aug 19 04:28:06 PM PDT 24 Aug 19 04:28:08 PM PDT 24 2030122383 ps
T330 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3241137822 Aug 19 04:28:33 PM PDT 24 Aug 19 04:28:41 PM PDT 24 5350368483 ps
T821 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3399810587 Aug 19 04:28:26 PM PDT 24 Aug 19 04:28:31 PM PDT 24 2065561280 ps
T822 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3228498000 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:18 PM PDT 24 7368720347 ps
T823 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3444240673 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2107508913 ps
T824 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2455286652 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:11 PM PDT 24 2125675009 ps
T825 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.584968596 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:20 PM PDT 24 2014446817 ps
T826 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3434821945 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:54 PM PDT 24 22235951921 ps
T827 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.150539983 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2034272822 ps
T828 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.693584089 Aug 19 04:28:09 PM PDT 24 Aug 19 04:29:08 PM PDT 24 22227909554 ps
T829 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2001860794 Aug 19 04:28:10 PM PDT 24 Aug 19 04:29:10 PM PDT 24 42541635624 ps
T312 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.794707279 Aug 19 04:28:03 PM PDT 24 Aug 19 04:28:08 PM PDT 24 6053138079 ps
T830 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1288578715 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:14 PM PDT 24 2009593862 ps
T831 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1931592335 Aug 19 04:28:12 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2018918023 ps
T313 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2048919038 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2051142986 ps
T832 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3183727699 Aug 19 04:28:10 PM PDT 24 Aug 19 04:28:13 PM PDT 24 5065488862 ps
T314 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1568821719 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:32 PM PDT 24 2048374317 ps
T833 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3770529754 Aug 19 04:28:12 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2011431294 ps
T834 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2224159325 Aug 19 04:28:34 PM PDT 24 Aug 19 04:28:36 PM PDT 24 2044093428 ps
T835 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4180114783 Aug 19 04:28:12 PM PDT 24 Aug 19 04:29:08 PM PDT 24 42427074739 ps
T836 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4010183672 Aug 19 04:28:24 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2016657349 ps
T837 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.550639816 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2150112729 ps
T838 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3643038336 Aug 19 04:28:18 PM PDT 24 Aug 19 04:28:19 PM PDT 24 2151104425 ps
T839 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.768231612 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:19 PM PDT 24 2018090591 ps
T840 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1297275809 Aug 19 04:28:24 PM PDT 24 Aug 19 04:28:40 PM PDT 24 22410533276 ps
T841 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.596398277 Aug 19 04:27:57 PM PDT 24 Aug 19 04:28:07 PM PDT 24 5965510583 ps
T842 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.407164508 Aug 19 04:28:19 PM PDT 24 Aug 19 04:28:30 PM PDT 24 7727344393 ps
T843 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1971795858 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:30 PM PDT 24 22260409115 ps
T315 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3882633958 Aug 19 04:28:03 PM PDT 24 Aug 19 04:28:31 PM PDT 24 8800558238 ps
T844 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2082092580 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:11 PM PDT 24 2127288402 ps
T845 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2632682099 Aug 19 04:28:20 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2055182526 ps
T846 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.167863311 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:11 PM PDT 24 4045602087 ps
T847 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.936367467 Aug 19 04:28:16 PM PDT 24 Aug 19 04:28:18 PM PDT 24 2071554046 ps
T848 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3405845524 Aug 19 04:28:10 PM PDT 24 Aug 19 04:28:13 PM PDT 24 2020013894 ps
T367 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3233825288 Aug 19 04:28:13 PM PDT 24 Aug 19 04:29:12 PM PDT 24 22218993575 ps
T849 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2785864932 Aug 19 04:28:53 PM PDT 24 Aug 19 04:28:56 PM PDT 24 4038617723 ps
T850 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.680462787 Aug 19 04:28:10 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2013913995 ps
T851 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1530150892 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:10 PM PDT 24 2052083677 ps
T852 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2163567493 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:18 PM PDT 24 2053684656 ps
T853 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1795619346 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:35 PM PDT 24 10275080706 ps
T316 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3875938735 Aug 19 04:28:25 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2121224232 ps
T317 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3687346341 Aug 19 04:28:33 PM PDT 24 Aug 19 04:28:39 PM PDT 24 2066273151 ps
T854 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2273309920 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:10 PM PDT 24 2188997656 ps
T318 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.640570094 Aug 19 04:28:00 PM PDT 24 Aug 19 04:28:02 PM PDT 24 2066055114 ps
T855 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2083974321 Aug 19 04:28:17 PM PDT 24 Aug 19 04:28:23 PM PDT 24 2010656321 ps
T856 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2493848467 Aug 19 04:28:31 PM PDT 24 Aug 19 04:28:38 PM PDT 24 2088498644 ps
T857 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.50303445 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:36 PM PDT 24 2013318080 ps
T858 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3301649713 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:13 PM PDT 24 2040877105 ps
T859 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3874805494 Aug 19 04:28:25 PM PDT 24 Aug 19 04:28:37 PM PDT 24 5287597493 ps
T860 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3103171490 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2388369676 ps
T861 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3702851483 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:22 PM PDT 24 2033509294 ps
T862 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3947138625 Aug 19 04:28:10 PM PDT 24 Aug 19 04:28:19 PM PDT 24 22409297434 ps
T863 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4293138595 Aug 19 04:28:19 PM PDT 24 Aug 19 04:28:25 PM PDT 24 2078700806 ps
T864 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.81965164 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:13 PM PDT 24 2078500926 ps
T865 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.6373089 Aug 19 04:28:23 PM PDT 24 Aug 19 04:28:27 PM PDT 24 2067908502 ps
T866 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1390033769 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:28 PM PDT 24 2042731542 ps
T867 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1829320777 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:13 PM PDT 24 2077613329 ps
T319 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1039598950 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2493806655 ps
T868 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4252507339 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:20 PM PDT 24 2042822981 ps
T869 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2867860882 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:27 PM PDT 24 6946444487 ps
T870 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.963585045 Aug 19 04:28:21 PM PDT 24 Aug 19 04:28:24 PM PDT 24 2022708581 ps
T871 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2590012551 Aug 19 04:28:09 PM PDT 24 Aug 19 04:29:22 PM PDT 24 42546715625 ps
T320 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4225746240 Aug 19 04:28:41 PM PDT 24 Aug 19 04:29:56 PM PDT 24 76040937461 ps
T321 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.882804194 Aug 19 04:27:56 PM PDT 24 Aug 19 04:28:12 PM PDT 24 6035169259 ps
T872 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2894434227 Aug 19 04:28:31 PM PDT 24 Aug 19 04:28:35 PM PDT 24 2588346145 ps
T322 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3424854599 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2033801443 ps
T873 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.457826363 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:21 PM PDT 24 2037320579 ps
T874 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2501255410 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:36 PM PDT 24 8181202929 ps
T875 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2330987436 Aug 19 04:28:01 PM PDT 24 Aug 19 04:28:35 PM PDT 24 9147793310 ps
T876 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2585555291 Aug 19 04:28:10 PM PDT 24 Aug 19 04:28:11 PM PDT 24 2225958066 ps
T877 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1439426917 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:11 PM PDT 24 2112937891 ps
T878 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2088839805 Aug 19 04:27:57 PM PDT 24 Aug 19 04:28:00 PM PDT 24 2193989511 ps
T879 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2137747515 Aug 19 04:28:05 PM PDT 24 Aug 19 04:28:33 PM PDT 24 22295381109 ps
T880 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1446127929 Aug 19 04:28:12 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2022255315 ps
T881 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2995420254 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:13 PM PDT 24 2130325485 ps
T882 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2777280461 Aug 19 04:28:06 PM PDT 24 Aug 19 04:28:07 PM PDT 24 2044221683 ps
T883 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2045629272 Aug 19 04:28:25 PM PDT 24 Aug 19 04:28:44 PM PDT 24 10116737630 ps
T884 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4017060585 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:20 PM PDT 24 2111934761 ps
T885 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1376752650 Aug 19 04:28:30 PM PDT 24 Aug 19 04:28:33 PM PDT 24 2035890980 ps
T886 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1878598734 Aug 19 04:28:19 PM PDT 24 Aug 19 04:28:21 PM PDT 24 2039980821 ps
T323 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3991605781 Aug 19 04:27:58 PM PDT 24 Aug 19 04:28:07 PM PDT 24 6037272154 ps
T887 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1143187193 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2027918480 ps
T324 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2791530659 Aug 19 04:28:27 PM PDT 24 Aug 19 04:28:31 PM PDT 24 2053331029 ps
T888 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.584914616 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2064164555 ps
T889 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2548800864 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:14 PM PDT 24 2034250713 ps
T890 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3359177105 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2056295233 ps
T891 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2225098677 Aug 19 04:28:07 PM PDT 24 Aug 19 04:28:09 PM PDT 24 2123552908 ps
T892 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3924660069 Aug 19 04:28:12 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2607147722 ps
T893 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1310711560 Aug 19 04:28:16 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2055814068 ps
T894 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.950395509 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:15 PM PDT 24 2113812272 ps
T895 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.130417612 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2039398982 ps
T896 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2829772656 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:16 PM PDT 24 22994507108 ps
T897 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1807206953 Aug 19 04:28:25 PM PDT 24 Aug 19 04:28:31 PM PDT 24 2054649915 ps
T898 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4092265406 Aug 19 04:28:05 PM PDT 24 Aug 19 04:28:13 PM PDT 24 4927606325 ps
T899 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3712349788 Aug 19 04:28:09 PM PDT 24 Aug 19 04:28:24 PM PDT 24 22498163289 ps
T900 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.511297279 Aug 19 04:28:12 PM PDT 24 Aug 19 04:28:19 PM PDT 24 2089293179 ps
T901 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3205285822 Aug 19 04:28:03 PM PDT 24 Aug 19 04:28:09 PM PDT 24 2045920884 ps
T902 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1047013937 Aug 19 04:28:01 PM PDT 24 Aug 19 04:28:05 PM PDT 24 2043040856 ps
T903 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4265939487 Aug 19 04:28:15 PM PDT 24 Aug 19 04:28:20 PM PDT 24 2206151026 ps
T904 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2172928109 Aug 19 04:28:06 PM PDT 24 Aug 19 04:28:14 PM PDT 24 2514847848 ps
T905 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.17465374 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:14 PM PDT 24 2093512880 ps
T906 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3657558719 Aug 19 04:28:31 PM PDT 24 Aug 19 04:28:33 PM PDT 24 2054389357 ps
T907 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1244433275 Aug 19 04:28:05 PM PDT 24 Aug 19 04:28:09 PM PDT 24 2078085126 ps
T908 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2396492937 Aug 19 04:28:31 PM PDT 24 Aug 19 04:28:33 PM PDT 24 2026267731 ps
T909 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1235167891 Aug 19 04:28:14 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2304914961 ps
T368 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3476716571 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:30 PM PDT 24 22388349373 ps
T910 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1628388559 Aug 19 04:28:16 PM PDT 24 Aug 19 04:28:18 PM PDT 24 2069016366 ps
T911 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1121255355 Aug 19 04:28:11 PM PDT 24 Aug 19 04:28:17 PM PDT 24 2074038968 ps
T912 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2398573869 Aug 19 04:28:08 PM PDT 24 Aug 19 04:28:18 PM PDT 24 4772035405 ps
T913 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3929704781 Aug 19 04:28:00 PM PDT 24 Aug 19 04:28:03 PM PDT 24 2049610544 ps
T914 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3312128606 Aug 19 04:28:16 PM PDT 24 Aug 19 04:28:22 PM PDT 24 2009839527 ps
T915 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3195135564 Aug 19 04:28:13 PM PDT 24 Aug 19 04:28:16 PM PDT 24 2018855029 ps

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3446431279
Short name T1
Test name
Test status
Simulation time 102837752740 ps
CPU time 133.44 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:53:01 PM PDT 24
Peak memory 201340 kb
Host smart-45ba51d0-e16e-4544-83d5-248ddff875e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446431279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3446431279
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1536247814
Short name T32
Test name
Test status
Simulation time 462205558037 ps
CPU time 172.65 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 201304 kb
Host smart-4972fa9b-8ac7-4af1-96f4-99af38dd65a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536247814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1536247814
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2190500232
Short name T14
Test name
Test status
Simulation time 23115070871 ps
CPU time 17.65 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:55 PM PDT 24
Peak memory 209680 kb
Host smart-a51dce45-35b0-4d56-8128-4c68c950de24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190500232 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2190500232
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.930024926
Short name T143
Test name
Test status
Simulation time 740340074689 ps
CPU time 32.79 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:51:20 PM PDT 24
Peak memory 201176 kb
Host smart-6a8d5854-098d-421c-8405-765c33da28c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930024926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_st
ress_all.930024926
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1962379023
Short name T20
Test name
Test status
Simulation time 6987250736 ps
CPU time 3.91 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:47:40 PM PDT 24
Peak memory 201144 kb
Host smart-1e386647-c76e-4833-bd2b-b75551d94e51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962379023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1962379023
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1570672246
Short name T80
Test name
Test status
Simulation time 35605332089 ps
CPU time 25.13 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201152 kb
Host smart-826ffb94-59c2-4111-bd3e-36e3d054701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570672246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1570672246
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1372474232
Short name T251
Test name
Test status
Simulation time 42516049736 ps
CPU time 30.96 seconds
Started Aug 19 04:28:16 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 201304 kb
Host smart-65dd3de8-a2f8-4b91-a0b0-16cb3b9c8141
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372474232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.1372474232
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.712349503
Short name T49
Test name
Test status
Simulation time 204549165657 ps
CPU time 125.67 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:52:17 PM PDT 24
Peak memory 201340 kb
Host smart-f6886131-063f-49fe-9f1d-09ffb9b7f805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712349503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_st
ress_all.712349503
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2851731521
Short name T28
Test name
Test status
Simulation time 65799400922 ps
CPU time 156.82 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:53:00 PM PDT 24
Peak memory 201348 kb
Host smart-b33986a2-b684-494c-868e-2ed7c7b921e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851731521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.2851731521
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1072810885
Short name T131
Test name
Test status
Simulation time 3718012601 ps
CPU time 8.19 seconds
Started Aug 19 04:48:30 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 201140 kb
Host smart-fa903062-1c1f-4096-beda-96c3f7b7fd83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072810885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1072810885
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.1019458573
Short name T178
Test name
Test status
Simulation time 14115640279 ps
CPU time 18.27 seconds
Started Aug 19 04:49:19 PM PDT 24
Finished Aug 19 04:49:38 PM PDT 24
Peak memory 201108 kb
Host smart-77b35d39-4201-4528-8296-7fa8dee3efc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019458573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.1019458573
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1003574590
Short name T234
Test name
Test status
Simulation time 156367293182 ps
CPU time 103.6 seconds
Started Aug 19 04:48:20 PM PDT 24
Finished Aug 19 04:50:04 PM PDT 24
Peak memory 201240 kb
Host smart-f828b4f6-0770-4cbf-8cde-54b219e80a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003574590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1003574590
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.903552931
Short name T88
Test name
Test status
Simulation time 51030793577 ps
CPU time 34.2 seconds
Started Aug 19 04:50:56 PM PDT 24
Finished Aug 19 04:51:30 PM PDT 24
Peak memory 201336 kb
Host smart-973dc5e1-834d-4503-8b90-110b2f7ab47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903552931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_wi
th_pre_cond.903552931
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2897547631
Short name T283
Test name
Test status
Simulation time 19119326900 ps
CPU time 12.66 seconds
Started Aug 19 04:49:30 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 209660 kb
Host smart-97fdcc18-4fd2-45cb-b75d-ac74ccbab373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897547631 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.2897547631
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2364424068
Short name T228
Test name
Test status
Simulation time 134686839304 ps
CPU time 161.2 seconds
Started Aug 19 04:50:51 PM PDT 24
Finished Aug 19 04:53:32 PM PDT 24
Peak memory 201404 kb
Host smart-f65dd728-7291-4e41-8ec7-ccdd30fa1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364424068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2364424068
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1033897945
Short name T76
Test name
Test status
Simulation time 26359776539 ps
CPU time 15.66 seconds
Started Aug 19 04:48:52 PM PDT 24
Finished Aug 19 04:49:08 PM PDT 24
Peak memory 217784 kb
Host smart-e5003bfb-43f4-488d-a94a-fc7f9dc174f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033897945 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.1033897945
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3472463833
Short name T252
Test name
Test status
Simulation time 42206383094 ps
CPU time 17.92 seconds
Started Aug 19 04:47:48 PM PDT 24
Finished Aug 19 04:48:06 PM PDT 24
Peak memory 220944 kb
Host smart-946b1e8c-3c5d-41d8-a820-6ee6c1290a14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472463833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3472463833
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2761236022
Short name T85
Test name
Test status
Simulation time 3991440141 ps
CPU time 8.8 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:12 PM PDT 24
Peak memory 201104 kb
Host smart-d6181a44-7cfd-41da-aeb7-8e09e02b232e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761236022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.2761236022
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3827700194
Short name T30
Test name
Test status
Simulation time 3095962448 ps
CPU time 2.03 seconds
Started Aug 19 04:50:06 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 201144 kb
Host smart-ba8ee17c-1f72-435c-91b0-f2de029518ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827700194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3827700194
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2983221041
Short name T335
Test name
Test status
Simulation time 145906000304 ps
CPU time 276.36 seconds
Started Aug 19 04:49:53 PM PDT 24
Finished Aug 19 04:54:30 PM PDT 24
Peak memory 201232 kb
Host smart-e28f661b-2428-430a-a7d6-86bf1b32d3e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983221041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.2983221041
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.2422142917
Short name T91
Test name
Test status
Simulation time 159233840494 ps
CPU time 429.48 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:57:19 PM PDT 24
Peak memory 201284 kb
Host smart-a28c7c8f-4b7d-4db4-a3c7-0ecc603adba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422142917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.2422142917
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1086057486
Short name T250
Test name
Test status
Simulation time 2081020534 ps
CPU time 4.8 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 201268 kb
Host smart-0a25878d-438f-4c47-a32a-d0f54a57663f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086057486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.1086057486
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.588713295
Short name T25
Test name
Test status
Simulation time 23584456182 ps
CPU time 13.28 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:36 PM PDT 24
Peak memory 212136 kb
Host smart-ff6656fd-c751-4303-a84c-4163d17c621d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588713295 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.588713295
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3190006122
Short name T377
Test name
Test status
Simulation time 29041579448 ps
CPU time 8.93 seconds
Started Aug 19 04:49:51 PM PDT 24
Finished Aug 19 04:50:00 PM PDT 24
Peak memory 213020 kb
Host smart-1a0ef095-2d4d-45a4-bbbe-eb4f4351c02d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190006122 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.3190006122
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.1716527783
Short name T22
Test name
Test status
Simulation time 233519795151 ps
CPU time 68.63 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:51:55 PM PDT 24
Peak memory 201200 kb
Host smart-3cf53d01-e348-44d3-9bbf-038246f8f7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716527783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.1716527783
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3315711620
Short name T189
Test name
Test status
Simulation time 112350555419 ps
CPU time 304.07 seconds
Started Aug 19 04:48:15 PM PDT 24
Finished Aug 19 04:53:19 PM PDT 24
Peak memory 201172 kb
Host smart-c888a50f-6afc-4743-b3ed-ec7da1ddd0e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315711620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3315711620
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1094454550
Short name T81
Test name
Test status
Simulation time 38577645238 ps
CPU time 25.17 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201156 kb
Host smart-5cdf1e39-e070-4cf2-a4a4-d6d150821237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094454550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1094454550
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1973547589
Short name T74
Test name
Test status
Simulation time 190327144176 ps
CPU time 28.36 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:51:17 PM PDT 24
Peak memory 201404 kb
Host smart-dc874732-e085-41fc-96a1-760265fe56eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973547589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.1973547589
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2348876913
Short name T142
Test name
Test status
Simulation time 160743273077 ps
CPU time 155.62 seconds
Started Aug 19 04:48:49 PM PDT 24
Finished Aug 19 04:51:25 PM PDT 24
Peak memory 201108 kb
Host smart-6f8225c1-3e1e-4cd6-bef8-f4c2341873a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348876913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2348876913
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1057183552
Short name T176
Test name
Test status
Simulation time 2776026997 ps
CPU time 7.61 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:48:13 PM PDT 24
Peak memory 201096 kb
Host smart-a8e7017d-3b5e-4d00-867f-7422de75ca73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057183552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1057183552
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3170934204
Short name T9
Test name
Test status
Simulation time 109709652874 ps
CPU time 74.63 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:49:20 PM PDT 24
Peak memory 201216 kb
Host smart-56249776-8967-4e3a-bba4-eb7946299749
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170934204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.3170934204
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1745598058
Short name T17
Test name
Test status
Simulation time 2048165349 ps
CPU time 5.64 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:12 PM PDT 24
Peak memory 200936 kb
Host smart-e96ac77a-f4e8-4f32-a2cd-4ab15d324d87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745598058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.1745598058
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.2890257983
Short name T122
Test name
Test status
Simulation time 12855481289 ps
CPU time 32.28 seconds
Started Aug 19 04:48:08 PM PDT 24
Finished Aug 19 04:48:41 PM PDT 24
Peak memory 201020 kb
Host smart-af540cf6-e02b-4970-b9e4-50cad3e0b098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890257983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.2890257983
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4225746240
Short name T320
Test name
Test status
Simulation time 76040937461 ps
CPU time 75.28 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:29:56 PM PDT 24
Peak memory 201188 kb
Host smart-86c6d1ad-531d-45fa-b3d4-3d19ddc7b1a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225746240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.4225746240
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1809555903
Short name T98
Test name
Test status
Simulation time 198254986184 ps
CPU time 125.32 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:50:34 PM PDT 24
Peak memory 201236 kb
Host smart-ae3b2b95-138d-4be8-8bfc-9613c7f2ce13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809555903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1809555903
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.1893971894
Short name T345
Test name
Test status
Simulation time 141877133026 ps
CPU time 53.76 seconds
Started Aug 19 04:49:07 PM PDT 24
Finished Aug 19 04:50:01 PM PDT 24
Peak memory 201336 kb
Host smart-501e17f1-70b1-497f-b4f9-4b39b83a1da6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893971894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.1893971894
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.302003800
Short name T271
Test name
Test status
Simulation time 2009329885 ps
CPU time 5.79 seconds
Started Aug 19 04:48:49 PM PDT 24
Finished Aug 19 04:48:55 PM PDT 24
Peak memory 201100 kb
Host smart-920b918c-6b13-4b11-b9d1-dd8e16adf9c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302003800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.302003800
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1600527660
Short name T809
Test name
Test status
Simulation time 77478307662 ps
CPU time 29.44 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:28:25 PM PDT 24
Peak memory 201136 kb
Host smart-e91ba0a2-dfb4-452f-b96a-cc88080b3937
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600527660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.1600527660
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.508318582
Short name T364
Test name
Test status
Simulation time 86347256652 ps
CPU time 96.5 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 201276 kb
Host smart-1c3f202d-db3b-4c9a-ad0b-4c6b479b239f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508318582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.508318582
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3851803841
Short name T352
Test name
Test status
Simulation time 111311901347 ps
CPU time 67.41 seconds
Started Aug 19 04:50:59 PM PDT 24
Finished Aug 19 04:52:07 PM PDT 24
Peak memory 201392 kb
Host smart-f7a2c698-b66a-4f1d-a15e-30086714a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851803841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.3851803841
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2527133584
Short name T260
Test name
Test status
Simulation time 2137949563 ps
CPU time 7.58 seconds
Started Aug 19 04:28:04 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 201320 kb
Host smart-bbcd96f6-aa25-4f98-b50d-9301bdf9b312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527133584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.2527133584
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2398427605
Short name T356
Test name
Test status
Simulation time 80019888207 ps
CPU time 112.5 seconds
Started Aug 19 04:50:51 PM PDT 24
Finished Aug 19 04:52:44 PM PDT 24
Peak memory 201308 kb
Host smart-c6637a6a-2b7f-49e2-8885-b0d360742aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398427605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.2398427605
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2110234538
Short name T350
Test name
Test status
Simulation time 86798856659 ps
CPU time 114.45 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:51:24 PM PDT 24
Peak memory 201360 kb
Host smart-701190f0-747c-48cd-a6a5-9d8d8a11a67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110234538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2110234538
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.728774172
Short name T11
Test name
Test status
Simulation time 145861343408 ps
CPU time 96.98 seconds
Started Aug 19 04:50:12 PM PDT 24
Finished Aug 19 04:51:49 PM PDT 24
Peak memory 201252 kb
Host smart-9c61c583-b898-4a37-8372-36b909ec2c41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728774172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_combo_detect.728774172
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1803495003
Short name T282
Test name
Test status
Simulation time 100127113517 ps
CPU time 42.86 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:51:07 PM PDT 24
Peak memory 201308 kb
Host smart-06e0b81e-f239-46c8-9f6b-6a9091b05b33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803495003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1803495003
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2526918225
Short name T225
Test name
Test status
Simulation time 74145326484 ps
CPU time 179.41 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:53:47 PM PDT 24
Peak memory 201328 kb
Host smart-f6c01b54-4498-443d-ad59-ec59facc20a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526918225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.2526918225
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3978311665
Short name T257
Test name
Test status
Simulation time 8613456518 ps
CPU time 8.7 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:49 PM PDT 24
Peak memory 201260 kb
Host smart-7ce14eaa-2d2f-4cea-a79a-88eaf1955c7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978311665 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3978311665
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.936966014
Short name T292
Test name
Test status
Simulation time 2511452259 ps
CPU time 7.35 seconds
Started Aug 19 04:48:59 PM PDT 24
Finished Aug 19 04:49:07 PM PDT 24
Peak memory 201152 kb
Host smart-20577a3d-9988-49ae-924b-90f743a0a1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936966014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.936966014
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.976788352
Short name T351
Test name
Test status
Simulation time 44515698347 ps
CPU time 11.26 seconds
Started Aug 19 04:49:54 PM PDT 24
Finished Aug 19 04:50:05 PM PDT 24
Peak memory 201288 kb
Host smart-89005b34-3115-4f4f-89a3-64aec1c57e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976788352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_wi
th_pre_cond.976788352
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3748336135
Short name T10
Test name
Test status
Simulation time 81982490403 ps
CPU time 81.46 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:52:10 PM PDT 24
Peak memory 201328 kb
Host smart-1572382e-5781-44f7-b01e-e4b9a2eb92ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748336135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.3748336135
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3792128656
Short name T376
Test name
Test status
Simulation time 98773643057 ps
CPU time 60.89 seconds
Started Aug 19 04:48:18 PM PDT 24
Finished Aug 19 04:49:19 PM PDT 24
Peak memory 201428 kb
Host smart-ec1dd95f-9aad-4d0e-a9bc-7220f6ae9b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792128656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.3792128656
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2430162781
Short name T38
Test name
Test status
Simulation time 2479514444 ps
CPU time 6.67 seconds
Started Aug 19 04:49:45 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201152 kb
Host smart-a6fd15f8-0c6f-477b-8c9d-bfceee4d455c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430162781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.2430162781
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2799094751
Short name T110
Test name
Test status
Simulation time 10465601641 ps
CPU time 7.69 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:47 PM PDT 24
Peak memory 201132 kb
Host smart-b4dbfc66-a904-466c-baa7-d220b670a169
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799094751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2799094751
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3991605781
Short name T323
Test name
Test status
Simulation time 6037272154 ps
CPU time 9.07 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 201020 kb
Host smart-d57c3df4-0733-4d72-832c-d1ebe38eb205
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991605781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3991605781
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3476716571
Short name T368
Test name
Test status
Simulation time 22388349373 ps
CPU time 16.56 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 201304 kb
Host smart-712ebc0e-4011-47dc-a8aa-a7a090bb8e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476716571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3476716571
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4255542626
Short name T47
Test name
Test status
Simulation time 3354522816 ps
CPU time 4.84 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:22 PM PDT 24
Peak memory 201208 kb
Host smart-12e8b5d3-0ef4-4ed8-a791-23f8966a03e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255542626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.4
255542626
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.337267298
Short name T83
Test name
Test status
Simulation time 165771711715 ps
CPU time 215.5 seconds
Started Aug 19 04:48:16 PM PDT 24
Finished Aug 19 04:51:52 PM PDT 24
Peak memory 201384 kb
Host smart-ca9ad752-d8d2-41ee-aa68-aafd132aa963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337267298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.337267298
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3436556253
Short name T372
Test name
Test status
Simulation time 99962648363 ps
CPU time 259.84 seconds
Started Aug 19 04:48:47 PM PDT 24
Finished Aug 19 04:53:07 PM PDT 24
Peak memory 201228 kb
Host smart-3df9847b-b945-4daa-bbd3-f75db2ec750d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436556253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3436556253
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3220236486
Short name T359
Test name
Test status
Simulation time 118948558047 ps
CPU time 289.2 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:52:36 PM PDT 24
Peak memory 201308 kb
Host smart-e4348c3f-75b9-4f87-af5c-e61d61fc0a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220236486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.3220236486
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2859563644
Short name T58
Test name
Test status
Simulation time 1695262702845 ps
CPU time 538.8 seconds
Started Aug 19 04:48:58 PM PDT 24
Finished Aug 19 04:57:57 PM PDT 24
Peak memory 201160 kb
Host smart-215d1327-5314-4332-8877-e229a93fb6cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859563644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2859563644
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1436032156
Short name T214
Test name
Test status
Simulation time 65448043763 ps
CPU time 165.58 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:51:55 PM PDT 24
Peak memory 201404 kb
Host smart-ffd9d0b1-efab-4748-8849-8c3bc8a93fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436032156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.1436032156
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3297692780
Short name T362
Test name
Test status
Simulation time 92162289706 ps
CPU time 48.18 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:50:17 PM PDT 24
Peak memory 201360 kb
Host smart-fc09139e-e2fe-48ee-a4fd-f6b9d0ca0613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297692780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.3297692780
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4238123471
Short name T39
Test name
Test status
Simulation time 76939772054 ps
CPU time 33.53 seconds
Started Aug 19 04:49:57 PM PDT 24
Finished Aug 19 04:50:31 PM PDT 24
Peak memory 201328 kb
Host smart-a5614315-16a1-4539-af9a-a75bd2b7773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238123471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.4238123471
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.646323702
Short name T236
Test name
Test status
Simulation time 94620834833 ps
CPU time 64.36 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:51:44 PM PDT 24
Peak memory 201272 kb
Host smart-69ea2bb8-18de-4b6a-bda3-6715bd7b3316
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646323702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_combo_detect.646323702
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4170615126
Short name T232
Test name
Test status
Simulation time 55163782308 ps
CPU time 73.57 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:51:52 PM PDT 24
Peak memory 201308 kb
Host smart-dcf7ad07-c2f5-4750-a8e6-07921ce08f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170615126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.4170615126
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1299492099
Short name T375
Test name
Test status
Simulation time 73086944823 ps
CPU time 90.25 seconds
Started Aug 19 04:50:53 PM PDT 24
Finished Aug 19 04:52:23 PM PDT 24
Peak memory 201360 kb
Host smart-3964e7cb-d75f-4e61-ba4b-c8e71220bc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299492099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1299492099
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1683089849
Short name T194
Test name
Test status
Simulation time 11792275139 ps
CPU time 8.63 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:26 PM PDT 24
Peak memory 217096 kb
Host smart-9b0b60d1-0ef3-456c-9733-1f5e6ee21690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683089849 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1683089849
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2488805407
Short name T140
Test name
Test status
Simulation time 3053634029 ps
CPU time 1.4 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201148 kb
Host smart-b004abfd-de08-4fd3-a537-86ae0a78ab9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488805407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.2488805407
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3020590234
Short name T29
Test name
Test status
Simulation time 2947052702 ps
CPU time 2.15 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201136 kb
Host smart-523d3f36-4f59-40a9-8b5d-d799f826e9c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020590234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3020590234
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2172928109
Short name T904
Test name
Test status
Simulation time 2514847848 ps
CPU time 8.02 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 201116 kb
Host smart-d748b145-4fec-4b45-aff9-79d9a22e6f4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172928109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.2172928109
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.882804194
Short name T321
Test name
Test status
Simulation time 6035169259 ps
CPU time 15.94 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:28:12 PM PDT 24
Peak memory 200956 kb
Host smart-bd3d1e61-ba85-4c23-9680-7b623d0f4168
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882804194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_hw_reset.882804194
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2585555291
Short name T876
Test name
Test status
Simulation time 2225958066 ps
CPU time 1.58 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 209548 kb
Host smart-8750cce1-8208-4a5e-941a-0afdb0412f4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585555291 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2585555291
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3205285822
Short name T901
Test name
Test status
Simulation time 2045920884 ps
CPU time 5.89 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 200812 kb
Host smart-d01a5eb5-017e-49cc-a80f-9cda519c27dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205285822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.3205285822
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3922078969
Short name T813
Test name
Test status
Simulation time 2012640124 ps
CPU time 5.54 seconds
Started Aug 19 04:29:05 PM PDT 24
Finished Aug 19 04:29:11 PM PDT 24
Peak memory 200672 kb
Host smart-214b300e-2ad6-432e-8344-57925b610913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922078969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3922078969
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.596398277
Short name T841
Test name
Test status
Simulation time 5965510583 ps
CPU time 10.55 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 201264 kb
Host smart-b4af1b74-f35a-4a55-ab65-017b52fe52ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596398277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.596398277
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2548800864
Short name T889
Test name
Test status
Simulation time 2034250713 ps
CPU time 6.84 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 200640 kb
Host smart-ebdfc14e-eea9-4464-a52a-281745ca5ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548800864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.2548800864
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4180114783
Short name T835
Test name
Test status
Simulation time 42427074739 ps
CPU time 46.02 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 201308 kb
Host smart-08572ce7-2076-42da-b441-675a464ed2ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180114783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.4180114783
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3847819111
Short name T817
Test name
Test status
Simulation time 2610636490 ps
CPU time 3.73 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:55 PM PDT 24
Peak memory 201052 kb
Host smart-ac06384b-b300-44c1-b10f-138c0f7f0f17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847819111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3847819111
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2785864932
Short name T849
Test name
Test status
Simulation time 4038617723 ps
CPU time 3.55 seconds
Started Aug 19 04:28:53 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 201012 kb
Host smart-2941983f-807a-4578-9290-b69ccef5e71c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785864932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.2785864932
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4260337258
Short name T266
Test name
Test status
Simulation time 2109857510 ps
CPU time 2.14 seconds
Started Aug 19 04:27:55 PM PDT 24
Finished Aug 19 04:27:57 PM PDT 24
Peak memory 201044 kb
Host smart-2c7e21ef-d966-48e4-9877-9c29a84dda71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260337258 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4260337258
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2995420254
Short name T881
Test name
Test status
Simulation time 2130325485 ps
CPU time 1.35 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 200832 kb
Host smart-5ea17e5a-9811-45a1-94d3-e7bda59384f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995420254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2995420254
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1530150892
Short name T851
Test name
Test status
Simulation time 2052083677 ps
CPU time 1.85 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:10 PM PDT 24
Peak memory 200660 kb
Host smart-10e38b12-b541-42b5-9eb8-cf5abb4e811b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530150892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1530150892
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2867860882
Short name T869
Test name
Test status
Simulation time 6946444487 ps
CPU time 17.94 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 201224 kb
Host smart-e086c0a6-fd62-4380-916e-58432601506a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867860882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2867860882
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.139767786
Short name T259
Test name
Test status
Simulation time 2050518477 ps
CPU time 3.96 seconds
Started Aug 19 04:27:56 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 201164 kb
Host smart-79bf189b-238a-415c-bca2-87d4644cfee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139767786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors
.139767786
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2001860794
Short name T829
Test name
Test status
Simulation time 42541635624 ps
CPU time 60.08 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 201228 kb
Host smart-6eb26159-5178-4577-9e59-64f651288103
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001860794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.2001860794
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1084802412
Short name T799
Test name
Test status
Simulation time 2081724354 ps
CPU time 6.11 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 200968 kb
Host smart-e1a1fec5-c8b7-4f85-8106-6066bce84373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084802412 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1084802412
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1628388559
Short name T910
Test name
Test status
Simulation time 2069016366 ps
CPU time 1.89 seconds
Started Aug 19 04:28:16 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 200980 kb
Host smart-3f2da763-6d2a-492e-8ad8-59372e980027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628388559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.1628388559
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3770529754
Short name T833
Test name
Test status
Simulation time 2011431294 ps
CPU time 5.55 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 200844 kb
Host smart-58cc6920-a2ce-4847-beaf-ce0514bb1dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770529754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3770529754
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.691470926
Short name T19
Test name
Test status
Simulation time 9619057287 ps
CPU time 6.93 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 201268 kb
Host smart-61963cee-e053-4d1c-b5b5-a340d3616e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691470926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.691470926
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.17465374
Short name T905
Test name
Test status
Simulation time 2093512880 ps
CPU time 3.21 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 201252 kb
Host smart-c8458f61-b82f-4595-baf8-3849a950f40e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17465374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors
.17465374
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2829772656
Short name T896
Test name
Test status
Simulation time 22994507108 ps
CPU time 7.25 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 201260 kb
Host smart-eae2dd2f-44e0-4628-840c-e06ac1e07ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829772656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2829772656
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1121255355
Short name T911
Test name
Test status
Simulation time 2074038968 ps
CPU time 6.49 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 201020 kb
Host smart-7cb3f202-0ba4-4173-a6c0-1703299dac40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121255355 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1121255355
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3359177105
Short name T890
Test name
Test status
Simulation time 2056295233 ps
CPU time 3.58 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 200892 kb
Host smart-2efbb594-4193-47b8-9a37-686c97b0b9ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359177105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.3359177105
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2083974321
Short name T855
Test name
Test status
Simulation time 2010656321 ps
CPU time 5.87 seconds
Started Aug 19 04:28:17 PM PDT 24
Finished Aug 19 04:28:23 PM PDT 24
Peak memory 200676 kb
Host smart-a652a28e-0b70-406e-a05e-bc8d071aad81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083974321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.2083974321
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.870585751
Short name T328
Test name
Test status
Simulation time 4704903021 ps
CPU time 11.47 seconds
Started Aug 19 04:28:35 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 201300 kb
Host smart-d5645c29-8484-4d19-b30a-fc5ef6ad2f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870585751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.870585751
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.799386204
Short name T249
Test name
Test status
Simulation time 2170588908 ps
CPU time 2.41 seconds
Started Aug 19 04:28:17 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 201304 kb
Host smart-06e06db8-4f21-4aa2-99f0-7b00783c0d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799386204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.799386204
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3712349788
Short name T899
Test name
Test status
Simulation time 22498163289 ps
CPU time 14.47 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:24 PM PDT 24
Peak memory 201328 kb
Host smart-67237da7-60a3-4b95-9b49-5185c4fcf71b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712349788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.3712349788
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2273309920
Short name T854
Test name
Test status
Simulation time 2188997656 ps
CPU time 2.4 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:10 PM PDT 24
Peak memory 201120 kb
Host smart-14dbf293-cf9a-4e64-8869-92d2073964d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273309920 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2273309920
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3657558719
Short name T906
Test name
Test status
Simulation time 2054389357 ps
CPU time 2.06 seconds
Started Aug 19 04:28:31 PM PDT 24
Finished Aug 19 04:28:33 PM PDT 24
Peak memory 200960 kb
Host smart-661b9bad-9b45-4ff6-8961-2ab1b6119eec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657558719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.3657558719
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3195135564
Short name T915
Test name
Test status
Simulation time 2018855029 ps
CPU time 3.08 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 200864 kb
Host smart-35ef0483-2f2c-4c13-a65b-59cdd6910b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195135564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3195135564
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2501255410
Short name T874
Test name
Test status
Simulation time 8181202929 ps
CPU time 9.11 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 201236 kb
Host smart-40e94ce5-12f3-4865-971f-a280f1b881b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501255410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.2501255410
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3399810587
Short name T821
Test name
Test status
Simulation time 2065561280 ps
CPU time 4.36 seconds
Started Aug 19 04:28:26 PM PDT 24
Finished Aug 19 04:28:31 PM PDT 24
Peak memory 201220 kb
Host smart-38a23173-3efb-4709-b416-4ca80516e4b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399810587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.3399810587
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1871248349
Short name T256
Test name
Test status
Simulation time 42394110428 ps
CPU time 61.11 seconds
Started Aug 19 04:28:28 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 201260 kb
Host smart-bd3fb6a3-113c-4dcf-988b-0265aa9c7bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871248349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.1871248349
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4293138595
Short name T863
Test name
Test status
Simulation time 2078700806 ps
CPU time 6.33 seconds
Started Aug 19 04:28:19 PM PDT 24
Finished Aug 19 04:28:25 PM PDT 24
Peak memory 201064 kb
Host smart-41a02daf-f9f9-43d4-8e22-801e74021b2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293138595 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4293138595
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3687346341
Short name T317
Test name
Test status
Simulation time 2066273151 ps
CPU time 6.22 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:39 PM PDT 24
Peak memory 200944 kb
Host smart-c63cab07-67aa-4b92-97be-ce8f7454dde6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687346341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3687346341
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.604629181
Short name T798
Test name
Test status
Simulation time 2008644524 ps
CPU time 5.24 seconds
Started Aug 19 04:28:23 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 200740 kb
Host smart-114684f5-b4b3-4b20-930a-7f064fb59527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604629181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.604629181
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3228498000
Short name T822
Test name
Test status
Simulation time 7368720347 ps
CPU time 9.98 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 201224 kb
Host smart-35ad6708-1cbc-435e-a800-36f56e40377c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228498000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3228498000
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2405836988
Short name T818
Test name
Test status
Simulation time 2125417651 ps
CPU time 7.85 seconds
Started Aug 19 04:28:29 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 201232 kb
Host smart-030a54d9-4798-45cd-9023-0d910e6f35ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405836988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.2405836988
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.693584089
Short name T828
Test name
Test status
Simulation time 22227909554 ps
CPU time 58.74 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 201260 kb
Host smart-027d371c-4537-492f-b6c9-4b7a0f082ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693584089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_tl_intg_err.693584089
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3301649713
Short name T858
Test name
Test status
Simulation time 2040877105 ps
CPU time 6.1 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 200996 kb
Host smart-3c4f83a8-e326-4d10-9d39-56da8182fa86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301649713 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3301649713
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.812729667
Short name T815
Test name
Test status
Simulation time 2039808656 ps
CPU time 5.52 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 200968 kb
Host smart-c8139aed-9dac-47a1-83e5-744567b39e3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812729667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.812729667
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3472040044
Short name T801
Test name
Test status
Simulation time 2033162353 ps
CPU time 2.49 seconds
Started Aug 19 04:28:17 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 200600 kb
Host smart-5d0e143a-61c2-4253-ad38-b40a633278e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472040044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3472040044
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3874805494
Short name T859
Test name
Test status
Simulation time 5287597493 ps
CPU time 11.79 seconds
Started Aug 19 04:28:25 PM PDT 24
Finished Aug 19 04:28:37 PM PDT 24
Peak memory 201232 kb
Host smart-32bfb81a-7701-44f9-a5a0-74e1d9d70d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874805494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.3874805494
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3103171490
Short name T860
Test name
Test status
Simulation time 2388369676 ps
CPU time 2.61 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 201196 kb
Host smart-9837b896-f294-4053-a8b1-e7caaa9a2a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103171490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.3103171490
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1971795858
Short name T843
Test name
Test status
Simulation time 22260409115 ps
CPU time 15.16 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 201316 kb
Host smart-d5bbc05f-d9aa-405b-9626-42f65e529c74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971795858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.1971795858
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4252507339
Short name T868
Test name
Test status
Simulation time 2042822981 ps
CPU time 6.23 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 200920 kb
Host smart-42d75580-0c7f-415e-906a-c9cb1d6a81fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252507339 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4252507339
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.950395509
Short name T894
Test name
Test status
Simulation time 2113812272 ps
CPU time 1.54 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 200884 kb
Host smart-20edffe4-ec68-4411-b37b-0f778e24d70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950395509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_r
w.950395509
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1615144464
Short name T804
Test name
Test status
Simulation time 2033416534 ps
CPU time 2.26 seconds
Started Aug 19 04:28:18 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 200868 kb
Host smart-096b46b3-57cc-4be1-9d1d-ca99942b6c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615144464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.1615144464
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2045629272
Short name T883
Test name
Test status
Simulation time 10116737630 ps
CPU time 19.61 seconds
Started Aug 19 04:28:25 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 201308 kb
Host smart-6281f4e1-00c4-41fb-8122-0a99b63c4065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045629272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2045629272
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2493848467
Short name T856
Test name
Test status
Simulation time 2088498644 ps
CPU time 6.88 seconds
Started Aug 19 04:28:31 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 201216 kb
Host smart-e5a1a7d6-89c7-4559-b655-8cea2e3c302c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493848467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2493848467
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1297275809
Short name T840
Test name
Test status
Simulation time 22410533276 ps
CPU time 16.11 seconds
Started Aug 19 04:28:24 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 201220 kb
Host smart-f583cb41-b557-4a66-b1f4-21dd6ba1ccaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297275809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1297275809
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.550639816
Short name T837
Test name
Test status
Simulation time 2150112729 ps
CPU time 1.77 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 201068 kb
Host smart-5f9b4fce-ac56-4d05-b740-ce6532ee4b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550639816 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.550639816
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2048919038
Short name T313
Test name
Test status
Simulation time 2051142986 ps
CPU time 2.19 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 200888 kb
Host smart-077fca43-6d54-4dd7-b269-f696b12e1930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048919038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.2048919038
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3312128606
Short name T914
Test name
Test status
Simulation time 2009839527 ps
CPU time 5.68 seconds
Started Aug 19 04:28:16 PM PDT 24
Finished Aug 19 04:28:22 PM PDT 24
Peak memory 200728 kb
Host smart-360f8689-14e4-4ec9-929e-9fe9e04ebf2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312128606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.3312128606
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3438684334
Short name T329
Test name
Test status
Simulation time 4937571307 ps
CPU time 11.78 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 201308 kb
Host smart-4fab0bb5-fb0f-4cb3-ad19-1b7cc93f3826
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438684334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.3438684334
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2894434227
Short name T872
Test name
Test status
Simulation time 2588346145 ps
CPU time 3.6 seconds
Started Aug 19 04:28:31 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 201296 kb
Host smart-58be9032-14a5-4905-b0de-17be7eb74774
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894434227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.2894434227
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1282631222
Short name T819
Test name
Test status
Simulation time 2041314451 ps
CPU time 5.72 seconds
Started Aug 19 04:28:23 PM PDT 24
Finished Aug 19 04:28:29 PM PDT 24
Peak memory 201060 kb
Host smart-daf0c983-3c9f-4d8c-b467-80df2246f558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282631222 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1282631222
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1807206953
Short name T897
Test name
Test status
Simulation time 2054649915 ps
CPU time 5.94 seconds
Started Aug 19 04:28:25 PM PDT 24
Finished Aug 19 04:28:31 PM PDT 24
Peak memory 200984 kb
Host smart-628da504-f039-41bd-ace7-e4b2effd01ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807206953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1807206953
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1910907726
Short name T811
Test name
Test status
Simulation time 2031152493 ps
CPU time 1.91 seconds
Started Aug 19 04:28:18 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 200868 kb
Host smart-b698a066-aca7-440a-a2c1-5032c2456ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910907726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.1910907726
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.407164508
Short name T842
Test name
Test status
Simulation time 7727344393 ps
CPU time 10.27 seconds
Started Aug 19 04:28:19 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 201344 kb
Host smart-6d0525c6-2b73-4321-aca7-f8c2e60050b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407164508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.407164508
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2491137055
Short name T261
Test name
Test status
Simulation time 2051927573 ps
CPU time 5.54 seconds
Started Aug 19 04:28:21 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 201244 kb
Host smart-cd96ba0e-377b-4c34-8270-a9e8b2f3371a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491137055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2491137055
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3947138625
Short name T862
Test name
Test status
Simulation time 22409297434 ps
CPU time 8.31 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 201312 kb
Host smart-79cfb60c-3d37-4549-8227-21c5983144bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947138625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3947138625
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.584914616
Short name T888
Test name
Test status
Simulation time 2064164555 ps
CPU time 6.65 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 201300 kb
Host smart-5932de9e-07ab-4403-9a2c-c0cf75d7627b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584914616 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.584914616
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3875938735
Short name T316
Test name
Test status
Simulation time 2121224232 ps
CPU time 2.08 seconds
Started Aug 19 04:28:25 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 200964 kb
Host smart-a50226f6-a27f-44fa-8c08-364cb0052c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875938735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3875938735
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2224159325
Short name T834
Test name
Test status
Simulation time 2044093428 ps
CPU time 1.96 seconds
Started Aug 19 04:28:34 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 200704 kb
Host smart-eca7cc84-094c-44a6-a4ba-58ed62bc474d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224159325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2224159325
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2601409353
Short name T326
Test name
Test status
Simulation time 10699818106 ps
CPU time 25.17 seconds
Started Aug 19 04:28:34 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 201256 kb
Host smart-a4cc1e4c-26b9-4376-9843-445bc3d6d8ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601409353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2601409353
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4017060585
Short name T884
Test name
Test status
Simulation time 2111934761 ps
CPU time 7.34 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 201252 kb
Host smart-3f40268d-4e0b-4d38-a5b9-aaa5ab38b69e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017060585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.4017060585
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1201605978
Short name T808
Test name
Test status
Simulation time 22377272213 ps
CPU time 9.87 seconds
Started Aug 19 04:28:22 PM PDT 24
Finished Aug 19 04:28:32 PM PDT 24
Peak memory 201168 kb
Host smart-a60c0578-0f6d-462b-befb-3f6ced741b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201605978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1201605978
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.288953312
Short name T264
Test name
Test status
Simulation time 2119856171 ps
CPU time 2.43 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:29 PM PDT 24
Peak memory 201268 kb
Host smart-d65337c5-d580-4ebe-af14-9ec35ec14ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288953312 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.288953312
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2791530659
Short name T324
Test name
Test status
Simulation time 2053331029 ps
CPU time 3.55 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:31 PM PDT 24
Peak memory 200984 kb
Host smart-ffaaa357-5222-45d9-9566-63101d4574b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791530659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2791530659
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1376752650
Short name T885
Test name
Test status
Simulation time 2035890980 ps
CPU time 1.84 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:33 PM PDT 24
Peak memory 200852 kb
Host smart-562ca485-df6f-40d8-be7f-620f3238f58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376752650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.1376752650
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3241137822
Short name T330
Test name
Test status
Simulation time 5350368483 ps
CPU time 7.21 seconds
Started Aug 19 04:28:33 PM PDT 24
Finished Aug 19 04:28:41 PM PDT 24
Peak memory 201204 kb
Host smart-eb442088-5835-4cbf-b11c-0a5c055366cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241137822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.3241137822
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2163567493
Short name T852
Test name
Test status
Simulation time 2053684656 ps
CPU time 4.98 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 201296 kb
Host smart-e7bfad89-7d1b-496a-8bbb-e353682bb83a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163567493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.2163567493
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2534166754
Short name T262
Test name
Test status
Simulation time 22273695376 ps
CPU time 14.34 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:34 PM PDT 24
Peak memory 201204 kb
Host smart-2f5a5bef-6cf9-4465-9c5b-3c3c8624a4da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534166754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2534166754
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3924660069
Short name T892
Test name
Test status
Simulation time 2607147722 ps
CPU time 3.73 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 201164 kb
Host smart-e90f3dec-d68b-46b3-a579-f468419b62af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924660069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3924660069
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.104723740
Short name T23
Test name
Test status
Simulation time 76620930240 ps
CPU time 74.15 seconds
Started Aug 19 04:28:19 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 201168 kb
Host smart-39315156-1818-4d7f-b2c3-3e626e5720a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104723740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.104723740
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1829320777
Short name T867
Test name
Test status
Simulation time 2077613329 ps
CPU time 6.38 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 200992 kb
Host smart-26890997-5ff2-4d70-ab73-a3b84012d1b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829320777 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1829320777
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1568821719
Short name T314
Test name
Test status
Simulation time 2048374317 ps
CPU time 2.04 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:32 PM PDT 24
Peak memory 201040 kb
Host smart-7515af37-67ec-4990-acb4-7781e0fa6c08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568821719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.1568821719
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2777280461
Short name T882
Test name
Test status
Simulation time 2044221683 ps
CPU time 1.3 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:07 PM PDT 24
Peak memory 200584 kb
Host smart-cf57753c-f50e-4322-84c9-e2f2a90dc224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777280461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.2777280461
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4092265406
Short name T898
Test name
Test status
Simulation time 4927606325 ps
CPU time 7.91 seconds
Started Aug 19 04:28:05 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 201308 kb
Host smart-b002160d-ec46-4d76-a35d-9f2bc7ed5c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092265406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.4092265406
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.238107056
Short name T806
Test name
Test status
Simulation time 2010360936 ps
CPU time 5.37 seconds
Started Aug 19 04:28:17 PM PDT 24
Finished Aug 19 04:28:23 PM PDT 24
Peak memory 200604 kb
Host smart-3a582487-648f-4ae2-beab-89e9df57c8d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238107056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.238107056
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.768231612
Short name T839
Test name
Test status
Simulation time 2018090591 ps
CPU time 3.32 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 200604 kb
Host smart-c9010990-ec47-4285-8a45-009e6ef2c216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768231612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_tes
t.768231612
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2632682099
Short name T845
Test name
Test status
Simulation time 2055182526 ps
CPU time 1.45 seconds
Started Aug 19 04:28:20 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 200748 kb
Host smart-b38b6645-55fe-4ea1-9a28-1bf6ab2aa2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632682099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2632682099
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.680462787
Short name T850
Test name
Test status
Simulation time 2013913995 ps
CPU time 5.93 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 200708 kb
Host smart-2f7ba3ba-f553-48e4-bdca-a17e49de61db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680462787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_tes
t.680462787
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1623931526
Short name T800
Test name
Test status
Simulation time 2042815541 ps
CPU time 1.78 seconds
Started Aug 19 04:28:25 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 200616 kb
Host smart-744b7e75-806b-4621-ba54-e68a7d53d6c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623931526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1623931526
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.34593495
Short name T794
Test name
Test status
Simulation time 2012980301 ps
CPU time 5.53 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 200768 kb
Host smart-f43e5dc2-4ce6-49ab-af6b-dcd4c19ced18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test
.34593495
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.584968596
Short name T825
Test name
Test status
Simulation time 2014446817 ps
CPU time 5.87 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 200660 kb
Host smart-60f15767-8a9b-4d87-84c8-fccc3fc264cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584968596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.584968596
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3444240673
Short name T823
Test name
Test status
Simulation time 2107508913 ps
CPU time 1.08 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 200740 kb
Host smart-27d2a83e-fa45-4c54-ab5c-30d1ba55db65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444240673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.3444240673
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.701872985
Short name T797
Test name
Test status
Simulation time 2029010260 ps
CPU time 1.95 seconds
Started Aug 19 04:28:28 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 200784 kb
Host smart-6217c8fb-5e7f-4ce8-8cc3-f8bad769377b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701872985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.701872985
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.130417612
Short name T895
Test name
Test status
Simulation time 2039398982 ps
CPU time 1.92 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 200784 kb
Host smart-7c1b74e1-6b19-4d9c-9ad5-f49d2b93564f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130417612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_tes
t.130417612
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1235167891
Short name T909
Test name
Test status
Simulation time 2304914961 ps
CPU time 3.47 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 201244 kb
Host smart-2b3105c3-0b47-4554-8848-0468012cb967
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235167891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1235167891
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3882633958
Short name T315
Test name
Test status
Simulation time 8800558238 ps
CPU time 27.17 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:31 PM PDT 24
Peak memory 201232 kb
Host smart-920ccce1-6476-4c03-a879-7317e3d29ec4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882633958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3882633958
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.794707279
Short name T312
Test name
Test status
Simulation time 6053138079 ps
CPU time 4.78 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 201016 kb
Host smart-8f607374-3c15-4c1c-bc50-d6afc6f1bbf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794707279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_hw_reset.794707279
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2082092580
Short name T844
Test name
Test status
Simulation time 2127288402 ps
CPU time 2.01 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 201000 kb
Host smart-167e7c76-485a-4651-9c97-1b8bae8aa2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082092580 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2082092580
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3929704781
Short name T913
Test name
Test status
Simulation time 2049610544 ps
CPU time 2.43 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:03 PM PDT 24
Peak memory 200868 kb
Host smart-6846657c-07f1-49c9-8995-a7489866c009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929704781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.3929704781
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1143187193
Short name T887
Test name
Test status
Simulation time 2027918480 ps
CPU time 3.18 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:28:16 PM PDT 24
Peak memory 200780 kb
Host smart-7c44a7fd-70c9-4d8d-b126-f49e30c73cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143187193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1143187193
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3183727699
Short name T832
Test name
Test status
Simulation time 5065488862 ps
CPU time 2.89 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 201164 kb
Host smart-3bb5f5a1-b4e3-40e4-adfb-4ec6499f438f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183727699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.3183727699
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2088839805
Short name T878
Test name
Test status
Simulation time 2193989511 ps
CPU time 2.62 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 201328 kb
Host smart-a0bdcf93-8da4-4788-8f20-77ec9f346f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088839805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.2088839805
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3233825288
Short name T367
Test name
Test status
Simulation time 22218993575 ps
CPU time 59.41 seconds
Started Aug 19 04:28:13 PM PDT 24
Finished Aug 19 04:29:12 PM PDT 24
Peak memory 201268 kb
Host smart-e1b5422a-0ccc-4d3a-be37-f7d93825ffb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233825288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3233825288
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.150539983
Short name T827
Test name
Test status
Simulation time 2034272822 ps
CPU time 1.99 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 200576 kb
Host smart-b980928f-d34e-4427-92b5-08cd3157416e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150539983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.150539983
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.687112328
Short name T792
Test name
Test status
Simulation time 2015722381 ps
CPU time 5.63 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 200384 kb
Host smart-59acb794-44b2-42d8-975b-64ed78fb7b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687112328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_tes
t.687112328
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1878598734
Short name T886
Test name
Test status
Simulation time 2039980821 ps
CPU time 1.98 seconds
Started Aug 19 04:28:19 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 200612 kb
Host smart-f8bdc947-b624-462a-83dc-a3b30ab1ae41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878598734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.1878598734
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2396492937
Short name T908
Test name
Test status
Simulation time 2026267731 ps
CPU time 1.77 seconds
Started Aug 19 04:28:31 PM PDT 24
Finished Aug 19 04:28:33 PM PDT 24
Peak memory 200716 kb
Host smart-e511336e-2ecc-46ba-9363-b457cfc1f18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396492937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2396492937
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.201422895
Short name T814
Test name
Test status
Simulation time 2022511479 ps
CPU time 3.45 seconds
Started Aug 19 04:28:19 PM PDT 24
Finished Aug 19 04:28:23 PM PDT 24
Peak memory 200672 kb
Host smart-7f9f840f-9d81-42ca-8df7-6dd9cab66642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201422895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.201422895
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3393120563
Short name T810
Test name
Test status
Simulation time 2011924713 ps
CPU time 5.94 seconds
Started Aug 19 04:28:34 PM PDT 24
Finished Aug 19 04:28:40 PM PDT 24
Peak memory 200672 kb
Host smart-0a0258c8-9842-4695-8591-477243c5b264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393120563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3393120563
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3643038336
Short name T838
Test name
Test status
Simulation time 2151104425 ps
CPU time 0.93 seconds
Started Aug 19 04:28:18 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 200800 kb
Host smart-4efc27e3-7b3d-4fb8-8acb-635bd58ff82e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643038336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.3643038336
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.349040723
Short name T793
Test name
Test status
Simulation time 2043500905 ps
CPU time 1.71 seconds
Started Aug 19 04:28:28 PM PDT 24
Finished Aug 19 04:28:30 PM PDT 24
Peak memory 200612 kb
Host smart-ce21df01-3494-4633-86b9-51cb9e1eaa2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349040723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.349040723
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.50303445
Short name T857
Test name
Test status
Simulation time 2013318080 ps
CPU time 5.61 seconds
Started Aug 19 04:28:30 PM PDT 24
Finished Aug 19 04:28:36 PM PDT 24
Peak memory 200604 kb
Host smart-e5686555-deac-4eea-b5fe-4aa6f9fb6bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50303445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test
.50303445
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1310711560
Short name T893
Test name
Test status
Simulation time 2055814068 ps
CPU time 1.42 seconds
Started Aug 19 04:28:16 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 200864 kb
Host smart-ab6d4f7e-1fc5-4054-a6b7-0e1cbd3f93bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310711560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.1310711560
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1039598950
Short name T319
Test name
Test status
Simulation time 2493806655 ps
CPU time 3.54 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 201212 kb
Host smart-9315a073-f3c6-4921-a244-3f985a35ad5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039598950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.1039598950
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3213716936
Short name T331
Test name
Test status
Simulation time 38803293096 ps
CPU time 175.85 seconds
Started Aug 19 04:28:45 PM PDT 24
Finished Aug 19 04:31:41 PM PDT 24
Peak memory 201124 kb
Host smart-8c42a0ce-3a17-45a1-82f3-ddcb5731ad38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213716936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.3213716936
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.167863311
Short name T846
Test name
Test status
Simulation time 4045602087 ps
CPU time 3.28 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 200920 kb
Host smart-3a447bbd-ef49-4097-99fa-0fa21d4bdf40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167863311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.167863311
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2455286652
Short name T824
Test name
Test status
Simulation time 2125675009 ps
CPU time 2.32 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 210104 kb
Host smart-a21b5e9a-c440-438f-9e35-29543f0776aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455286652 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2455286652
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2256085927
Short name T54
Test name
Test status
Simulation time 2050772263 ps
CPU time 6.11 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 200956 kb
Host smart-97142598-f808-4246-aede-294b7be16f7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256085927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2256085927
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1878257907
Short name T802
Test name
Test status
Simulation time 2037944137 ps
CPU time 1.85 seconds
Started Aug 19 04:27:58 PM PDT 24
Finished Aug 19 04:28:00 PM PDT 24
Peak memory 200700 kb
Host smart-8eb3b08a-6bf9-4810-b21e-3e47e60bd611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878257907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.1878257907
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2330987436
Short name T875
Test name
Test status
Simulation time 9147793310 ps
CPU time 34.08 seconds
Started Aug 19 04:28:01 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 201300 kb
Host smart-bc2a228a-0f22-4c70-bea1-8060eb4dd558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330987436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2330987436
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.81965164
Short name T864
Test name
Test status
Simulation time 2078500926 ps
CPU time 2.26 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 201196 kb
Host smart-6d8d7339-63fc-4620-95db-39d2b3ac5d44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81965164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.81965164
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.71466550
Short name T267
Test name
Test status
Simulation time 42534331573 ps
CPU time 26.48 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 201316 kb
Host smart-b6aa73d2-3fac-4460-b233-11a7822d8c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71466550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_tl_intg_err.71466550
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.579712179
Short name T795
Test name
Test status
Simulation time 2037055373 ps
CPU time 1.84 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:29 PM PDT 24
Peak memory 200660 kb
Host smart-e29ea46b-35d6-4cdf-b67a-7e2f4e611d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579712179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.579712179
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3405845524
Short name T848
Test name
Test status
Simulation time 2020013894 ps
CPU time 3.28 seconds
Started Aug 19 04:28:10 PM PDT 24
Finished Aug 19 04:28:13 PM PDT 24
Peak memory 200672 kb
Host smart-bd992b19-f2f2-4a2f-9198-415cba9cd3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405845524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3405845524
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2025909747
Short name T816
Test name
Test status
Simulation time 2025072839 ps
CPU time 3.08 seconds
Started Aug 19 04:28:17 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 200868 kb
Host smart-ac2f6295-5427-4f0b-a7c4-35815778e6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025909747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.2025909747
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.963585045
Short name T870
Test name
Test status
Simulation time 2022708581 ps
CPU time 2.97 seconds
Started Aug 19 04:28:21 PM PDT 24
Finished Aug 19 04:28:24 PM PDT 24
Peak memory 200788 kb
Host smart-ebbf797e-a99c-4314-b2d2-16f987bfa885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963585045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.963585045
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4010183672
Short name T836
Test name
Test status
Simulation time 2016657349 ps
CPU time 2.83 seconds
Started Aug 19 04:28:24 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 200780 kb
Host smart-33029756-5f71-4a57-915e-232cc4599d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010183672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.4010183672
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1390033769
Short name T866
Test name
Test status
Simulation time 2042731542 ps
CPU time 1.84 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 200684 kb
Host smart-2af2d2ae-3a7b-4603-a388-41796fa8d94f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390033769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1390033769
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1455562561
Short name T805
Test name
Test status
Simulation time 2031653911 ps
CPU time 1.82 seconds
Started Aug 19 04:28:27 PM PDT 24
Finished Aug 19 04:28:28 PM PDT 24
Peak memory 200672 kb
Host smart-06e90885-1b2f-40c1-b28a-0f7f35065149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455562561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1455562561
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1446127929
Short name T880
Test name
Test status
Simulation time 2022255315 ps
CPU time 3.11 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 200656 kb
Host smart-6115b803-a163-4e94-9b31-1434f8791a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446127929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.1446127929
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3287453682
Short name T803
Test name
Test status
Simulation time 2026005664 ps
CPU time 2.94 seconds
Started Aug 19 04:28:18 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 200740 kb
Host smart-4ae9fe6c-de76-47bf-94c1-38528561ef30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287453682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3287453682
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1931592335
Short name T831
Test name
Test status
Simulation time 2018918023 ps
CPU time 3.2 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:15 PM PDT 24
Peak memory 200612 kb
Host smart-82c95b3f-7f5c-456c-b9eb-76ade341ed6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931592335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1931592335
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2225098677
Short name T891
Test name
Test status
Simulation time 2123552908 ps
CPU time 1.67 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 200896 kb
Host smart-817bcf03-ff40-4de5-b329-68a8c32903e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225098677 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2225098677
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1047013937
Short name T902
Test name
Test status
Simulation time 2043040856 ps
CPU time 3.07 seconds
Started Aug 19 04:28:01 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 200776 kb
Host smart-6b80a6f9-3f23-473d-b76f-8af6510327ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047013937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.1047013937
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.448058279
Short name T796
Test name
Test status
Simulation time 2136436119 ps
CPU time 0.86 seconds
Started Aug 19 04:28:04 PM PDT 24
Finished Aug 19 04:28:05 PM PDT 24
Peak memory 200628 kb
Host smart-e03c1b9c-5079-437b-b655-d5720db40242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448058279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.448058279
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2109420772
Short name T327
Test name
Test status
Simulation time 4372559138 ps
CPU time 10.85 seconds
Started Aug 19 04:27:57 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 201220 kb
Host smart-c4e6fdf5-4c33-4fc6-8039-1056dfc8f6be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109420772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2109420772
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2786750741
Short name T263
Test name
Test status
Simulation time 2134594148 ps
CPU time 3.2 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:53 PM PDT 24
Peak memory 201224 kb
Host smart-4733077a-bcd0-43cb-aa8c-30b6dff072a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786750741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2786750741
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3434821945
Short name T826
Test name
Test status
Simulation time 22235951921 ps
CPU time 46.11 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 201220 kb
Host smart-eb9b4102-202b-4ace-8bf4-5e6d832d7c34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434821945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3434821945
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.6373089
Short name T865
Test name
Test status
Simulation time 2067908502 ps
CPU time 3.7 seconds
Started Aug 19 04:28:23 PM PDT 24
Finished Aug 19 04:28:27 PM PDT 24
Peak memory 200948 kb
Host smart-ede67f5a-f7e5-4d6d-87d7-cf77e63a5aa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6373089 -assert nopostproc +UVM_TESTNAME=sy
srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.6373089
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1244433275
Short name T907
Test name
Test status
Simulation time 2078085126 ps
CPU time 3.57 seconds
Started Aug 19 04:28:05 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 200896 kb
Host smart-46932adf-9fc9-4bd0-a732-9e5a2f040259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244433275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.1244433275
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1288578715
Short name T830
Test name
Test status
Simulation time 2009593862 ps
CPU time 5.68 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 200612 kb
Host smart-f9b95fa5-78fa-470a-889b-4b4352650878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288578715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.1288578715
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1796215470
Short name T325
Test name
Test status
Simulation time 7017500257 ps
CPU time 16.2 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:25 PM PDT 24
Peak memory 201260 kb
Host smart-a73fbafb-107c-460e-a45a-d1b33365effc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796215470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1796215470
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1554838592
Short name T265
Test name
Test status
Simulation time 22248697247 ps
CPU time 54.65 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 201216 kb
Host smart-5e11171a-65c1-4de2-9d5b-077f91315a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554838592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.1554838592
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1439426917
Short name T877
Test name
Test status
Simulation time 2112937891 ps
CPU time 2.36 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:11 PM PDT 24
Peak memory 201248 kb
Host smart-b60f5233-0d25-449a-aa00-3db983027134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439426917 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1439426917
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.640570094
Short name T318
Test name
Test status
Simulation time 2066055114 ps
CPU time 2.16 seconds
Started Aug 19 04:28:00 PM PDT 24
Finished Aug 19 04:28:02 PM PDT 24
Peak memory 200892 kb
Host smart-ed048b3c-c693-4a23-a0dd-d77aad81319c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640570094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw
.640570094
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1269944546
Short name T812
Test name
Test status
Simulation time 2016527876 ps
CPU time 5.5 seconds
Started Aug 19 04:28:03 PM PDT 24
Finished Aug 19 04:28:09 PM PDT 24
Peak memory 200780 kb
Host smart-0c4d2263-f5dc-4830-ab21-dc4398cba7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269944546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1269944546
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2398573869
Short name T912
Test name
Test status
Simulation time 4772035405 ps
CPU time 9.8 seconds
Started Aug 19 04:28:08 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 201224 kb
Host smart-a74ad496-ecdf-468c-893b-142707b0017e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398573869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2398573869
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.457826363
Short name T873
Test name
Test status
Simulation time 2037320579 ps
CPU time 7.53 seconds
Started Aug 19 04:28:14 PM PDT 24
Finished Aug 19 04:28:21 PM PDT 24
Peak memory 201120 kb
Host smart-4c1217bf-9116-479a-8d7d-51608621ad81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457826363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors
.457826363
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2658466225
Short name T255
Test name
Test status
Simulation time 22236282686 ps
CPU time 38.7 seconds
Started Aug 19 04:28:22 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 201320 kb
Host smart-a2c39089-3ae1-4b8f-b4bc-84c15886ee37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658466225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.2658466225
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.936367467
Short name T847
Test name
Test status
Simulation time 2071554046 ps
CPU time 2.18 seconds
Started Aug 19 04:28:16 PM PDT 24
Finished Aug 19 04:28:18 PM PDT 24
Peak memory 201008 kb
Host smart-b3629276-16f8-4d68-96bb-815a1d129b8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936367467 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.936367467
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3424854599
Short name T322
Test name
Test status
Simulation time 2033801443 ps
CPU time 5.84 seconds
Started Aug 19 04:28:11 PM PDT 24
Finished Aug 19 04:28:17 PM PDT 24
Peak memory 200876 kb
Host smart-5a44f4ac-9901-4464-961b-f1a7400bb920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424854599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3424854599
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3702851483
Short name T861
Test name
Test status
Simulation time 2033509294 ps
CPU time 1.79 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:22 PM PDT 24
Peak memory 200604 kb
Host smart-808e70b9-e6bc-48ff-9324-a6c34c7f1aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702851483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.3702851483
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1795619346
Short name T853
Test name
Test status
Simulation time 10275080706 ps
CPU time 26.35 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 201268 kb
Host smart-58423935-7924-4849-a8f8-e0bdcdfc690f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795619346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1795619346
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.133564632
Short name T807
Test name
Test status
Simulation time 2055635857 ps
CPU time 6.71 seconds
Started Aug 19 04:28:07 PM PDT 24
Finished Aug 19 04:28:14 PM PDT 24
Peak memory 201144 kb
Host smart-62c97725-46da-4260-9443-276c511837e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133564632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.133564632
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2137747515
Short name T879
Test name
Test status
Simulation time 22295381109 ps
CPU time 27.79 seconds
Started Aug 19 04:28:05 PM PDT 24
Finished Aug 19 04:28:33 PM PDT 24
Peak memory 201168 kb
Host smart-75abaca0-97c8-4a6c-b485-cba6980def05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137747515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.2137747515
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.511297279
Short name T900
Test name
Test status
Simulation time 2089293179 ps
CPU time 6.25 seconds
Started Aug 19 04:28:12 PM PDT 24
Finished Aug 19 04:28:19 PM PDT 24
Peak memory 201296 kb
Host smart-8f5858f5-5407-474f-a541-36491673c576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511297279 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.511297279
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.106280241
Short name T820
Test name
Test status
Simulation time 2030122383 ps
CPU time 1.89 seconds
Started Aug 19 04:28:06 PM PDT 24
Finished Aug 19 04:28:08 PM PDT 24
Peak memory 200872 kb
Host smart-376b708a-dce6-4448-b2be-4f356e86298c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106280241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.106280241
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3450315667
Short name T18
Test name
Test status
Simulation time 8800677713 ps
CPU time 16.22 seconds
Started Aug 19 04:28:18 PM PDT 24
Finished Aug 19 04:28:35 PM PDT 24
Peak memory 201304 kb
Host smart-90a4f63f-078f-4701-9ae2-9d0a0b8061e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450315667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3450315667
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4265939487
Short name T903
Test name
Test status
Simulation time 2206151026 ps
CPU time 4.63 seconds
Started Aug 19 04:28:15 PM PDT 24
Finished Aug 19 04:28:20 PM PDT 24
Peak memory 201304 kb
Host smart-c2f175c1-7550-4223-acb6-6ef242fc94e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265939487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.4265939487
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2590012551
Short name T871
Test name
Test status
Simulation time 42546715625 ps
CPU time 72.77 seconds
Started Aug 19 04:28:09 PM PDT 24
Finished Aug 19 04:29:22 PM PDT 24
Peak memory 201304 kb
Host smart-f435fe6f-eb66-4d26-9464-9add1b2d37ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590012551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2590012551
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.2372530809
Short name T417
Test name
Test status
Simulation time 2027009347 ps
CPU time 2.7 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:47:40 PM PDT 24
Peak memory 201120 kb
Host smart-d4694830-1d1d-49a0-9e5f-e351653ece61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372530809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.2372530809
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1756617731
Short name T82
Test name
Test status
Simulation time 3050754707 ps
CPU time 2.79 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:47:38 PM PDT 24
Peak memory 201204 kb
Host smart-7fb13831-5459-4471-aa09-ef8bdf0fb6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756617731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1756617731
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3329171886
Short name T529
Test name
Test status
Simulation time 2421470662 ps
CPU time 6.6 seconds
Started Aug 19 04:47:29 PM PDT 24
Finished Aug 19 04:47:36 PM PDT 24
Peak memory 201136 kb
Host smart-04868c1a-68ed-4721-ac5d-89b36422300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329171886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.3329171886
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3091711762
Short name T647
Test name
Test status
Simulation time 2478304551 ps
CPU time 1.01 seconds
Started Aug 19 04:47:32 PM PDT 24
Finished Aug 19 04:47:33 PM PDT 24
Peak memory 201084 kb
Host smart-d2706701-9714-4a7d-a117-80249a2c624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091711762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3091711762
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2949286198
Short name T87
Test name
Test status
Simulation time 26081523381 ps
CPU time 70.32 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:48:47 PM PDT 24
Peak memory 201308 kb
Host smart-c9d47c40-e937-4483-a4e2-766514456e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949286198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.2949286198
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2768249422
Short name T728
Test name
Test status
Simulation time 3564520028 ps
CPU time 9.12 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:47:45 PM PDT 24
Peak memory 201100 kb
Host smart-3c5b849d-ebb1-421b-a467-b47d0bec47d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768249422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.2768249422
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2330947330
Short name T617
Test name
Test status
Simulation time 2544844878 ps
CPU time 6.15 seconds
Started Aug 19 04:47:34 PM PDT 24
Finished Aug 19 04:47:41 PM PDT 24
Peak memory 201148 kb
Host smart-fad1ec25-2d77-4a4e-8bca-62b6f0fa3fc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330947330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2330947330
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3011571829
Short name T70
Test name
Test status
Simulation time 2610184613 ps
CPU time 6.93 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:47:44 PM PDT 24
Peak memory 201168 kb
Host smart-e3bb220c-55ff-4da9-adb1-2119543df675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011571829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3011571829
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3418634110
Short name T494
Test name
Test status
Simulation time 2446316832 ps
CPU time 6.63 seconds
Started Aug 19 04:47:29 PM PDT 24
Finished Aug 19 04:47:36 PM PDT 24
Peak memory 201144 kb
Host smart-2c5542f5-1ab1-4e22-9941-302003207813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418634110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3418634110
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.141506
Short name T602
Test name
Test status
Simulation time 2191929967 ps
CPU time 1.91 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:47:38 PM PDT 24
Peak memory 201160 kb
Host smart-3fbe200d-3e85-4bed-b940-0a2ee381b828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.141506
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1316038313
Short name T713
Test name
Test status
Simulation time 2511663896 ps
CPU time 7.58 seconds
Started Aug 19 04:47:34 PM PDT 24
Finished Aug 19 04:47:42 PM PDT 24
Peak memory 201148 kb
Host smart-25ecd6c8-e4db-4c29-9e60-813eed8fbed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316038313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1316038313
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.4268011850
Short name T202
Test name
Test status
Simulation time 22013283857 ps
CPU time 56.75 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:48:33 PM PDT 24
Peak memory 220868 kb
Host smart-94cbe901-2cb7-40b0-a088-5dd4538d0304
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268011850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.4268011850
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2587468021
Short name T440
Test name
Test status
Simulation time 2137509781 ps
CPU time 1.69 seconds
Started Aug 19 04:47:27 PM PDT 24
Finished Aug 19 04:47:29 PM PDT 24
Peak memory 201072 kb
Host smart-6ba43cef-73a9-4648-8edd-6469be9b3edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587468021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2587468021
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3880431385
Short name T245
Test name
Test status
Simulation time 255007424462 ps
CPU time 666.26 seconds
Started Aug 19 04:47:41 PM PDT 24
Finished Aug 19 04:58:47 PM PDT 24
Peak memory 201228 kb
Host smart-9d51fd9c-5b01-48dd-bcdb-018fc4bcf73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880431385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3880431385
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2651980571
Short name T586
Test name
Test status
Simulation time 11183127012 ps
CPU time 14.11 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:47:49 PM PDT 24
Peak memory 209628 kb
Host smart-ee4fcebe-5c07-4471-8f70-ab9de23f846e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651980571 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2651980571
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.435720692
Short name T57
Test name
Test status
Simulation time 4604900347 ps
CPU time 7.64 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:47:44 PM PDT 24
Peak memory 201164 kb
Host smart-b85faa41-5b80-4c56-bbd1-665116ffd028
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435720692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ultra_low_pwr.435720692
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.4099706739
Short name T670
Test name
Test status
Simulation time 2014972535 ps
CPU time 5.54 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:47:42 PM PDT 24
Peak memory 201124 kb
Host smart-f67366c6-2805-488f-b1f5-90c3eeefda46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099706739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.4099706739
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1209406210
Short name T477
Test name
Test status
Simulation time 194018631092 ps
CPU time 492.06 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:55:48 PM PDT 24
Peak memory 201164 kb
Host smart-f6b5e048-2a38-49bf-b18f-30d56695ac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209406210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1209406210
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.4077193082
Short name T565
Test name
Test status
Simulation time 221464559613 ps
CPU time 582.09 seconds
Started Aug 19 04:47:41 PM PDT 24
Finished Aug 19 04:57:23 PM PDT 24
Peak memory 201252 kb
Host smart-357cb378-cb6f-4bab-a37c-aab3593c98db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077193082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.4077193082
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1444090860
Short name T597
Test name
Test status
Simulation time 2280594044 ps
CPU time 1.94 seconds
Started Aug 19 04:47:34 PM PDT 24
Finished Aug 19 04:47:36 PM PDT 24
Peak memory 201132 kb
Host smart-637bbeb9-5d0f-4e52-a5ea-14c7c55fc71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444090860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1444090860
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2759697007
Short name T752
Test name
Test status
Simulation time 2547626088 ps
CPU time 3.88 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:47:41 PM PDT 24
Peak memory 201128 kb
Host smart-2e394780-f1da-4c78-8ce5-9575fba98a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759697007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2759697007
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3975338033
Short name T434
Test name
Test status
Simulation time 5187705722 ps
CPU time 13.83 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:47:51 PM PDT 24
Peak memory 201128 kb
Host smart-d7841a48-9fc1-4ecf-affa-4b31f0bb978a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975338033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3975338033
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3104669116
Short name T136
Test name
Test status
Simulation time 5482903100 ps
CPU time 5.36 seconds
Started Aug 19 04:47:37 PM PDT 24
Finished Aug 19 04:47:42 PM PDT 24
Peak memory 201044 kb
Host smart-427d00f1-d6e5-417d-9b6b-a2ed9c5a1941
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104669116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.3104669116
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.200797719
Short name T511
Test name
Test status
Simulation time 2619671129 ps
CPU time 4.01 seconds
Started Aug 19 04:47:34 PM PDT 24
Finished Aug 19 04:47:38 PM PDT 24
Peak memory 201144 kb
Host smart-973e0f38-9fc3-476b-9ade-567a82686810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200797719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.200797719
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.868647976
Short name T548
Test name
Test status
Simulation time 2474483851 ps
CPU time 2.09 seconds
Started Aug 19 04:47:38 PM PDT 24
Finished Aug 19 04:47:40 PM PDT 24
Peak memory 201152 kb
Host smart-109bf17c-2c07-4958-8c59-0264af241e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868647976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.868647976
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.2891506942
Short name T443
Test name
Test status
Simulation time 2206560892 ps
CPU time 5 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:47:40 PM PDT 24
Peak memory 201140 kb
Host smart-fc9bf454-6620-4ada-81c3-d6dae2bb8f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891506942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.2891506942
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3069106100
Short name T145
Test name
Test status
Simulation time 2510487335 ps
CPU time 6.84 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:47:42 PM PDT 24
Peak memory 201152 kb
Host smart-ee9512db-3cdd-45cf-aec3-a953f7e841c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069106100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3069106100
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3483935456
Short name T253
Test name
Test status
Simulation time 42013844848 ps
CPU time 112.75 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:49:29 PM PDT 24
Peak memory 221048 kb
Host smart-f1cb3f9c-ffe0-42e0-92c1-a538ae76c3d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483935456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3483935456
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.3205979858
Short name T560
Test name
Test status
Simulation time 2114934089 ps
CPU time 6.14 seconds
Started Aug 19 04:47:35 PM PDT 24
Finished Aug 19 04:47:41 PM PDT 24
Peak memory 201060 kb
Host smart-1b852db2-c6aa-409c-86fc-b6d4299ca701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205979858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.3205979858
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.112949760
Short name T309
Test name
Test status
Simulation time 28085670612 ps
CPU time 13.99 seconds
Started Aug 19 04:47:36 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 209672 kb
Host smart-d3fbe65a-3aa1-410b-80a3-22d88ec84a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112949760 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.112949760
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.4144854744
Short name T539
Test name
Test status
Simulation time 2026674518 ps
CPU time 1.92 seconds
Started Aug 19 04:48:16 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201104 kb
Host smart-1c5a8570-0721-4ec0-a73a-14c9b5f3412d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144854744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.4144854744
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.693901029
Short name T108
Test name
Test status
Simulation time 72720714047 ps
CPU time 191.18 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:51:31 PM PDT 24
Peak memory 201324 kb
Host smart-46cb0913-7f39-4df9-ab15-0fdb287ee3da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693901029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.693901029
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1170779630
Short name T654
Test name
Test status
Simulation time 34255772294 ps
CPU time 90.89 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:49:48 PM PDT 24
Peak memory 201408 kb
Host smart-ee1542d8-aa00-4636-b62e-71a12c56ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170779630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1170779630
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3225259293
Short name T740
Test name
Test status
Simulation time 3438822914 ps
CPU time 1.63 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:19 PM PDT 24
Peak memory 201132 kb
Host smart-032a0797-32ec-4028-a67c-3846857c5055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225259293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.3225259293
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1671800161
Short name T84
Test name
Test status
Simulation time 2915660085 ps
CPU time 8.21 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:25 PM PDT 24
Peak memory 201108 kb
Host smart-9f4e384b-df45-4191-b190-b2b58e8b1196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671800161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.1671800161
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.4148854679
Short name T171
Test name
Test status
Simulation time 2610774553 ps
CPU time 7.08 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:48:26 PM PDT 24
Peak memory 201144 kb
Host smart-503cbfc4-f08b-4e7c-890b-8b6a1e087c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148854679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.4148854679
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2003133832
Short name T448
Test name
Test status
Simulation time 2490024162 ps
CPU time 2.38 seconds
Started Aug 19 04:48:15 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201152 kb
Host smart-efcab0a8-f51f-4f6b-8aca-1c713c8d8cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003133832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.2003133832
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1067749560
Short name T103
Test name
Test status
Simulation time 2239097978 ps
CPU time 2.08 seconds
Started Aug 19 04:48:15 PM PDT 24
Finished Aug 19 04:48:17 PM PDT 24
Peak memory 201124 kb
Host smart-0b070d02-a109-4c08-b1cb-c61f4f70af78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067749560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1067749560
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1545943488
Short name T628
Test name
Test status
Simulation time 2513248873 ps
CPU time 7.15 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:24 PM PDT 24
Peak memory 201152 kb
Host smart-40b6e494-fdee-4566-9fbb-d05390e104b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545943488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1545943488
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.109173870
Short name T731
Test name
Test status
Simulation time 2123203314 ps
CPU time 3.42 seconds
Started Aug 19 04:48:21 PM PDT 24
Finished Aug 19 04:48:24 PM PDT 24
Peak memory 200996 kb
Host smart-4a9d05be-98c0-46e2-adc6-55e4388540b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109173870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.109173870
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1948401079
Short name T285
Test name
Test status
Simulation time 7306756132 ps
CPU time 18.04 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:48:37 PM PDT 24
Peak memory 211212 kb
Host smart-7c717fde-92bc-48d2-b3be-7f7bed594725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948401079 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1948401079
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3764069380
Short name T12
Test name
Test status
Simulation time 6822996985 ps
CPU time 3.82 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:48:23 PM PDT 24
Peak memory 201164 kb
Host smart-7e844930-4f32-4b60-8b69-91d12240ca5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764069380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3764069380
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.7689923
Short name T559
Test name
Test status
Simulation time 2026792916 ps
CPU time 2 seconds
Started Aug 19 04:48:29 PM PDT 24
Finished Aug 19 04:48:31 PM PDT 24
Peak memory 201140 kb
Host smart-7de3534e-766f-4971-bbc5-f905b81f5e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7689923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.7689923
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2979509464
Short name T445
Test name
Test status
Simulation time 89859637755 ps
CPU time 243.25 seconds
Started Aug 19 04:48:20 PM PDT 24
Finished Aug 19 04:52:24 PM PDT 24
Peak memory 201224 kb
Host smart-99945863-eb6c-4881-b214-f006ab71fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979509464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
979509464
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3864627073
Short name T248
Test name
Test status
Simulation time 65724253488 ps
CPU time 81.71 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:49:39 PM PDT 24
Peak memory 201304 kb
Host smart-ff14d84a-8186-4b06-9fc4-6ad59586210b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864627073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.3864627073
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.864235665
Short name T452
Test name
Test status
Simulation time 2795179580 ps
CPU time 2.43 seconds
Started Aug 19 04:48:20 PM PDT 24
Finished Aug 19 04:48:22 PM PDT 24
Peak memory 201144 kb
Host smart-fd98d709-a897-4e0a-aea4-535c9fca783a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864235665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ec_pwr_on_rst.864235665
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.3481606108
Short name T168
Test name
Test status
Simulation time 640064251859 ps
CPU time 21.79 seconds
Started Aug 19 04:48:16 PM PDT 24
Finished Aug 19 04:48:37 PM PDT 24
Peak memory 201064 kb
Host smart-6c78709d-26a6-43ad-a16b-4e25376d77dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481606108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.3481606108
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1726138242
Short name T390
Test name
Test status
Simulation time 2615072271 ps
CPU time 4.02 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:21 PM PDT 24
Peak memory 201148 kb
Host smart-9d55fa3f-e228-4adf-b215-1ecb4e473ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726138242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1726138242
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3669370336
Short name T65
Test name
Test status
Simulation time 2444827849 ps
CPU time 7 seconds
Started Aug 19 04:48:16 PM PDT 24
Finished Aug 19 04:48:23 PM PDT 24
Peak memory 201160 kb
Host smart-acd356df-8a65-4733-b651-b7f0eef859c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669370336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3669370336
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1276636014
Short name T468
Test name
Test status
Simulation time 2247383592 ps
CPU time 1.93 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:48:21 PM PDT 24
Peak memory 201144 kb
Host smart-584be021-3325-4ba8-85c6-4cf8df5b6d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276636014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1276636014
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2774342186
Short name T639
Test name
Test status
Simulation time 2517564069 ps
CPU time 3.79 seconds
Started Aug 19 04:48:14 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201136 kb
Host smart-81f918fa-d114-497c-b75f-bb3dffb83eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774342186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2774342186
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.3283882413
Short name T193
Test name
Test status
Simulation time 2123208998 ps
CPU time 1.95 seconds
Started Aug 19 04:48:16 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201072 kb
Host smart-30df77f4-d5e6-437c-b516-f7bbe56575ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283882413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3283882413
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.630355843
Short name T693
Test name
Test status
Simulation time 174589428573 ps
CPU time 435.25 seconds
Started Aug 19 04:48:27 PM PDT 24
Finished Aug 19 04:55:43 PM PDT 24
Peak memory 201296 kb
Host smart-df36893d-cdca-406b-ab95-12c42b0f447c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630355843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_st
ress_all.630355843
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.868350585
Short name T289
Test name
Test status
Simulation time 4094429693 ps
CPU time 12.34 seconds
Started Aug 19 04:48:29 PM PDT 24
Finished Aug 19 04:48:41 PM PDT 24
Peak memory 209644 kb
Host smart-5bbd2874-028a-438d-9676-6575ef8b343c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868350585 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.868350585
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3857855513
Short name T783
Test name
Test status
Simulation time 5948373976 ps
CPU time 4.99 seconds
Started Aug 19 04:48:15 PM PDT 24
Finished Aug 19 04:48:20 PM PDT 24
Peak memory 201164 kb
Host smart-dcd8de0a-1069-4510-96df-c1e1d968e334
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857855513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.3857855513
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1322326603
Short name T220
Test name
Test status
Simulation time 2021848155 ps
CPU time 3.37 seconds
Started Aug 19 04:48:33 PM PDT 24
Finished Aug 19 04:48:36 PM PDT 24
Peak memory 201128 kb
Host smart-c537c582-e14d-4a2d-8da3-570fa3124ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322326603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1322326603
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3545227369
Short name T42
Test name
Test status
Simulation time 3637556480 ps
CPU time 9.44 seconds
Started Aug 19 04:48:29 PM PDT 24
Finished Aug 19 04:48:39 PM PDT 24
Peak memory 201188 kb
Host smart-c0b625e9-4455-405f-96dc-1878e7a90ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545227369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
545227369
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1793727317
Short name T247
Test name
Test status
Simulation time 85760578031 ps
CPU time 190.64 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:51:39 PM PDT 24
Peak memory 201308 kb
Host smart-dfcdc101-40b7-4f72-b131-26f7aa4b5e9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793727317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1793727317
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2716335722
Short name T637
Test name
Test status
Simulation time 31978236274 ps
CPU time 44.03 seconds
Started Aug 19 04:48:25 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201364 kb
Host smart-3a9fad3d-c025-4979-a91f-580019423a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716335722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2716335722
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3880274383
Short name T679
Test name
Test status
Simulation time 3106001685 ps
CPU time 8.05 seconds
Started Aug 19 04:48:27 PM PDT 24
Finished Aug 19 04:48:35 PM PDT 24
Peak memory 201144 kb
Host smart-c9a14121-d97e-4081-b871-bf9d46dcd685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880274383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.3880274383
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.3229706884
Short name T180
Test name
Test status
Simulation time 2525848334 ps
CPU time 2.24 seconds
Started Aug 19 04:48:29 PM PDT 24
Finished Aug 19 04:48:31 PM PDT 24
Peak memory 201108 kb
Host smart-c6b81879-8276-41f9-a9c9-e62921fab263
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229706884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.3229706884
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4095306988
Short name T758
Test name
Test status
Simulation time 2633629121 ps
CPU time 2.46 seconds
Started Aug 19 04:48:26 PM PDT 24
Finished Aug 19 04:48:29 PM PDT 24
Peak memory 201128 kb
Host smart-01e4a348-aa33-4085-a1e9-0c845da56b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095306988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.4095306988
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2106761364
Short name T761
Test name
Test status
Simulation time 2465586720 ps
CPU time 3.6 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:48:32 PM PDT 24
Peak memory 201116 kb
Host smart-3f03465f-4839-43f0-a0b9-fceded4fca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106761364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2106761364
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.833645159
Short name T538
Test name
Test status
Simulation time 2172152508 ps
CPU time 3.33 seconds
Started Aug 19 04:48:27 PM PDT 24
Finished Aug 19 04:48:30 PM PDT 24
Peak memory 201132 kb
Host smart-6fd3440f-db30-40fa-b022-007dab9f7126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833645159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.833645159
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1882085794
Short name T743
Test name
Test status
Simulation time 2520952554 ps
CPU time 3.71 seconds
Started Aug 19 04:48:25 PM PDT 24
Finished Aug 19 04:48:29 PM PDT 24
Peak memory 201152 kb
Host smart-46e246e0-eded-46a8-af75-f01ce4c9961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882085794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1882085794
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.272893129
Short name T295
Test name
Test status
Simulation time 2116151890 ps
CPU time 3.25 seconds
Started Aug 19 04:48:26 PM PDT 24
Finished Aug 19 04:48:30 PM PDT 24
Peak memory 201072 kb
Host smart-3612edf7-d02e-4d32-95ec-b97c59c2397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272893129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.272893129
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1303096577
Short name T667
Test name
Test status
Simulation time 6562176498 ps
CPU time 18.43 seconds
Started Aug 19 04:48:27 PM PDT 24
Finished Aug 19 04:48:46 PM PDT 24
Peak memory 201136 kb
Host smart-acf3a4a6-5677-4b8f-b114-f1f0e6810eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303096577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1303096577
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3794859556
Short name T53
Test name
Test status
Simulation time 4394283606 ps
CPU time 12.02 seconds
Started Aug 19 04:48:33 PM PDT 24
Finished Aug 19 04:48:45 PM PDT 24
Peak memory 201252 kb
Host smart-4addda0d-c60a-4f16-9425-85705a3d2145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794859556 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3794859556
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.581665419
Short name T630
Test name
Test status
Simulation time 5030688477 ps
CPU time 1.11 seconds
Started Aug 19 04:48:25 PM PDT 24
Finished Aug 19 04:48:26 PM PDT 24
Peak memory 201108 kb
Host smart-c7cdc6dc-1612-48f8-9365-c23269d72dee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581665419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ultra_low_pwr.581665419
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.2795560787
Short name T691
Test name
Test status
Simulation time 2021173156 ps
CPU time 1.9 seconds
Started Aug 19 04:48:45 PM PDT 24
Finished Aug 19 04:48:47 PM PDT 24
Peak memory 201156 kb
Host smart-da4eaa8b-4687-4d94-9360-826ae0057435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795560787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.2795560787
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3837903584
Short name T725
Test name
Test status
Simulation time 3446899018 ps
CPU time 2.91 seconds
Started Aug 19 04:48:29 PM PDT 24
Finished Aug 19 04:48:32 PM PDT 24
Peak memory 201204 kb
Host smart-5de0c52b-0a75-4072-a36b-6be8d41c1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837903584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3
837903584
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2250838852
Short name T644
Test name
Test status
Simulation time 23332646797 ps
CPU time 60.4 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:49:28 PM PDT 24
Peak memory 201296 kb
Host smart-c315280b-60f5-40fc-be85-b43bb08f8f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250838852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.2250838852
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1358809908
Short name T190
Test name
Test status
Simulation time 2632877747 ps
CPU time 7.58 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:48:36 PM PDT 24
Peak memory 201140 kb
Host smart-684b5f99-3676-4131-ac4e-2d20ebe8c7ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358809908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1358809908
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.430391386
Short name T649
Test name
Test status
Simulation time 2614998471 ps
CPU time 3.76 seconds
Started Aug 19 04:48:27 PM PDT 24
Finished Aug 19 04:48:31 PM PDT 24
Peak memory 201128 kb
Host smart-aadfff9c-d162-471f-8791-cadb4188e128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430391386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.430391386
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1683498523
Short name T695
Test name
Test status
Simulation time 2454615975 ps
CPU time 2.37 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:48:31 PM PDT 24
Peak memory 201152 kb
Host smart-c67a9ab2-e839-42f5-a5a3-9893d1b2dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683498523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1683498523
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2309944619
Short name T106
Test name
Test status
Simulation time 2166252897 ps
CPU time 1.37 seconds
Started Aug 19 04:48:28 PM PDT 24
Finished Aug 19 04:48:30 PM PDT 24
Peak memory 201140 kb
Host smart-e9978272-c4db-42f4-88ea-9d554815254c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309944619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.2309944619
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3032791791
Short name T572
Test name
Test status
Simulation time 2517899797 ps
CPU time 5.51 seconds
Started Aug 19 04:48:32 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 201136 kb
Host smart-7ed0fc23-1ba7-463d-8af9-9f0a7a9959d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032791791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3032791791
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.3320166483
Short name T392
Test name
Test status
Simulation time 2137373896 ps
CPU time 1.5 seconds
Started Aug 19 04:48:30 PM PDT 24
Finished Aug 19 04:48:32 PM PDT 24
Peak memory 200992 kb
Host smart-efb8f185-a9a3-4d1d-9e81-f86a3a588e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320166483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3320166483
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.268012096
Short name T244
Test name
Test status
Simulation time 167276561413 ps
CPU time 418.73 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:55:45 PM PDT 24
Peak memory 201240 kb
Host smart-75dec565-0e8d-42ab-882f-c74620630a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268012096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st
ress_all.268012096
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3719840312
Short name T514
Test name
Test status
Simulation time 3198051183 ps
CPU time 3.14 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:48:50 PM PDT 24
Peak memory 201288 kb
Host smart-c9d58892-b91b-4cef-982c-91df3a8206d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719840312 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3719840312
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.252410352
Short name T629
Test name
Test status
Simulation time 9157718277 ps
CPU time 6.46 seconds
Started Aug 19 04:48:31 PM PDT 24
Finished Aug 19 04:48:37 PM PDT 24
Peak memory 201144 kb
Host smart-17a2209e-6726-45ed-be37-08f0580333e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252410352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ultra_low_pwr.252410352
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.1502148560
Short name T425
Test name
Test status
Simulation time 2070675813 ps
CPU time 1.77 seconds
Started Aug 19 04:48:47 PM PDT 24
Finished Aug 19 04:48:49 PM PDT 24
Peak memory 201148 kb
Host smart-3fb53968-d3d5-4615-8cc5-e4f561a9997b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502148560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.1502148560
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1298160940
Short name T465
Test name
Test status
Simulation time 211114561556 ps
CPU time 213.2 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:52:19 PM PDT 24
Peak memory 201164 kb
Host smart-e30b45ee-9f4e-4207-8412-5e26150d1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298160940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1
298160940
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2980228008
Short name T358
Test name
Test status
Simulation time 60656322073 ps
CPU time 163.36 seconds
Started Aug 19 04:48:44 PM PDT 24
Finished Aug 19 04:51:27 PM PDT 24
Peak memory 201396 kb
Host smart-442e312d-c936-4c02-9fd4-bf2892a6907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980228008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2980228008
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.606527077
Short name T632
Test name
Test status
Simulation time 2619722309 ps
CPU time 2.28 seconds
Started Aug 19 04:48:43 PM PDT 24
Finished Aug 19 04:48:45 PM PDT 24
Peak memory 201108 kb
Host smart-27a7cd9b-d4ed-4592-99d0-db2fe9af93b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606527077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ec_pwr_on_rst.606527077
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1721981163
Short name T127
Test name
Test status
Simulation time 2636117073 ps
CPU time 2.29 seconds
Started Aug 19 04:48:47 PM PDT 24
Finished Aug 19 04:48:50 PM PDT 24
Peak memory 201116 kb
Host smart-a5f7316b-87c4-4953-a2fc-acae3dc34af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721981163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1721981163
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3652263003
Short name T62
Test name
Test status
Simulation time 2476440888 ps
CPU time 6.92 seconds
Started Aug 19 04:48:43 PM PDT 24
Finished Aug 19 04:48:50 PM PDT 24
Peak memory 201152 kb
Host smart-ca2c17bf-ac4b-4445-8867-09bdca8b8ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652263003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3652263003
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.664512430
Short name T561
Test name
Test status
Simulation time 2069927141 ps
CPU time 5.39 seconds
Started Aug 19 04:48:42 PM PDT 24
Finished Aug 19 04:48:47 PM PDT 24
Peak memory 201056 kb
Host smart-e6de4f50-31ce-451e-a041-b5ff163275d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664512430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.664512430
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.653086422
Short name T383
Test name
Test status
Simulation time 2524239345 ps
CPU time 2.42 seconds
Started Aug 19 04:48:44 PM PDT 24
Finished Aug 19 04:48:46 PM PDT 24
Peak memory 201100 kb
Host smart-168d371f-b22a-436c-ade0-153c8169ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653086422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.653086422
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3839312745
Short name T388
Test name
Test status
Simulation time 2110891817 ps
CPU time 5.98 seconds
Started Aug 19 04:48:44 PM PDT 24
Finished Aug 19 04:48:51 PM PDT 24
Peak memory 201060 kb
Host smart-423d1b6a-e43c-471a-ab82-2bae47978a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839312745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3839312745
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2110207450
Short name T175
Test name
Test status
Simulation time 77145581694 ps
CPU time 56.52 seconds
Started Aug 19 04:48:44 PM PDT 24
Finished Aug 19 04:49:41 PM PDT 24
Peak memory 201308 kb
Host smart-5e79d48d-9071-4f02-b178-6e90a72bd4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110207450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2110207450
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.357047894
Short name T288
Test name
Test status
Simulation time 11407889566 ps
CPU time 5.31 seconds
Started Aug 19 04:48:47 PM PDT 24
Finished Aug 19 04:48:53 PM PDT 24
Peak memory 201440 kb
Host smart-920ed4e6-4254-435a-84a3-865e562dce00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357047894 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.357047894
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.415354020
Short name T116
Test name
Test status
Simulation time 5807442079 ps
CPU time 3.73 seconds
Started Aug 19 04:48:43 PM PDT 24
Finished Aug 19 04:48:47 PM PDT 24
Peak memory 201160 kb
Host smart-cfa2c67b-d4d8-4642-8ac1-c3e83a5aec87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415354020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ultra_low_pwr.415354020
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.1746632074
Short name T702
Test name
Test status
Simulation time 2013409564 ps
CPU time 5.89 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:48:52 PM PDT 24
Peak memory 201048 kb
Host smart-2c49a946-8972-439e-ab1f-b10613e48139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746632074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.1746632074
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2798599558
Short name T436
Test name
Test status
Simulation time 3419044323 ps
CPU time 5.21 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:48:52 PM PDT 24
Peak memory 201240 kb
Host smart-33ad6950-2aee-4d65-a565-9fb5275bd27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798599558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
798599558
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3265702151
Short name T333
Test name
Test status
Simulation time 159983535456 ps
CPU time 257.36 seconds
Started Aug 19 04:48:48 PM PDT 24
Finished Aug 19 04:53:05 PM PDT 24
Peak memory 201280 kb
Host smart-50d5ed67-9beb-422c-a122-2f566785c068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265702151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.3265702151
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2826342631
Short name T741
Test name
Test status
Simulation time 27669934922 ps
CPU time 65.89 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201304 kb
Host smart-2511e3f8-7dcc-49c0-8e1e-4ab2b9ec37a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826342631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.2826342631
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.685294225
Short name T621
Test name
Test status
Simulation time 4019953479 ps
CPU time 9.84 seconds
Started Aug 19 04:48:49 PM PDT 24
Finished Aug 19 04:48:59 PM PDT 24
Peak memory 201036 kb
Host smart-2892c370-87a4-435b-845a-5cb2933dfafd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685294225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.685294225
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4188297952
Short name T208
Test name
Test status
Simulation time 3106170485 ps
CPU time 1.95 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:48:48 PM PDT 24
Peak memory 201176 kb
Host smart-16e8e6be-2b9a-46a6-84be-a3fd8f76d62a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188297952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.4188297952
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1919805086
Short name T755
Test name
Test status
Simulation time 2614269038 ps
CPU time 7.33 seconds
Started Aug 19 04:48:47 PM PDT 24
Finished Aug 19 04:48:54 PM PDT 24
Peak memory 201132 kb
Host smart-73f2d3f2-50bc-4872-a7d7-7d134721611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919805086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1919805086
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.3109039730
Short name T67
Test name
Test status
Simulation time 2474877162 ps
CPU time 3.89 seconds
Started Aug 19 04:48:45 PM PDT 24
Finished Aug 19 04:48:49 PM PDT 24
Peak memory 201100 kb
Host smart-bb003e5c-88dd-410a-b4ed-ef4c7afaed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109039730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.3109039730
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.314464431
Short name T400
Test name
Test status
Simulation time 2161285470 ps
CPU time 6.55 seconds
Started Aug 19 04:48:44 PM PDT 24
Finished Aug 19 04:48:51 PM PDT 24
Peak memory 201104 kb
Host smart-483d594f-a987-418e-b404-76c1c9365a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314464431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.314464431
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.2130458107
Short name T748
Test name
Test status
Simulation time 2121790705 ps
CPU time 2.01 seconds
Started Aug 19 04:48:48 PM PDT 24
Finished Aug 19 04:48:50 PM PDT 24
Peak memory 201056 kb
Host smart-2e79409a-fb89-42c8-a34e-0964f4864e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130458107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.2130458107
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3779923552
Short name T645
Test name
Test status
Simulation time 7276871871 ps
CPU time 5.66 seconds
Started Aug 19 04:48:46 PM PDT 24
Finished Aug 19 04:48:52 PM PDT 24
Peak memory 201112 kb
Host smart-22b922c1-3228-46b6-8a77-6aa258b1295a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779923552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3779923552
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1428465366
Short name T52
Test name
Test status
Simulation time 3775282340 ps
CPU time 10.31 seconds
Started Aug 19 04:48:49 PM PDT 24
Finished Aug 19 04:48:59 PM PDT 24
Peak memory 201184 kb
Host smart-0bf7c778-3b0f-43f8-9b37-5bca4f89737f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428465366 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1428465366
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3724045715
Short name T620
Test name
Test status
Simulation time 3776645213 ps
CPU time 3.08 seconds
Started Aug 19 04:48:50 PM PDT 24
Finished Aug 19 04:48:53 PM PDT 24
Peak memory 201168 kb
Host smart-45583a94-417d-4279-9a01-f8c37979936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724045715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
724045715
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2163480473
Short name T200
Test name
Test status
Simulation time 66504073636 ps
CPU time 85.81 seconds
Started Aug 19 04:48:48 PM PDT 24
Finished Aug 19 04:50:14 PM PDT 24
Peak memory 201204 kb
Host smart-13b80a8b-8b0b-46d9-bc95-00dbbc0226e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163480473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.2163480473
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2123498612
Short name T338
Test name
Test status
Simulation time 72715011647 ps
CPU time 176.95 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:51:48 PM PDT 24
Peak memory 201380 kb
Host smart-c5d7203a-5a64-4c19-8977-e2c5bf940d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123498612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.2123498612
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.123375939
Short name T183
Test name
Test status
Simulation time 4220500015 ps
CPU time 3.19 seconds
Started Aug 19 04:48:48 PM PDT 24
Finished Aug 19 04:48:52 PM PDT 24
Peak memory 201160 kb
Host smart-002c47bd-9af2-458b-9405-30b3f15f13a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123375939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ec_pwr_on_rst.123375939
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2894232363
Short name T157
Test name
Test status
Simulation time 5058730188 ps
CPU time 10.25 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:49:01 PM PDT 24
Peak memory 201144 kb
Host smart-307621cd-829f-4b7b-96e6-74e882df342d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894232363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.2894232363
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.4247391531
Short name T501
Test name
Test status
Simulation time 2637370340 ps
CPU time 2.33 seconds
Started Aug 19 04:48:47 PM PDT 24
Finished Aug 19 04:48:50 PM PDT 24
Peak memory 201144 kb
Host smart-e5d3b0fb-275e-4adf-b547-418082b3e313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247391531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.4247391531
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3183621179
Short name T750
Test name
Test status
Simulation time 2448229254 ps
CPU time 6.98 seconds
Started Aug 19 04:48:48 PM PDT 24
Finished Aug 19 04:48:55 PM PDT 24
Peak memory 201136 kb
Host smart-ebb79cb8-b6b1-4a01-b0d9-88dfa60288c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183621179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3183621179
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1609213769
Short name T393
Test name
Test status
Simulation time 2154092767 ps
CPU time 3.53 seconds
Started Aug 19 04:48:48 PM PDT 24
Finished Aug 19 04:48:51 PM PDT 24
Peak memory 201124 kb
Host smart-f15d8129-19f4-4455-bce7-570a4c4a24db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609213769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1609213769
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.4263198318
Short name T303
Test name
Test status
Simulation time 2520355867 ps
CPU time 2.94 seconds
Started Aug 19 04:48:50 PM PDT 24
Finished Aug 19 04:48:53 PM PDT 24
Peak memory 201116 kb
Host smart-27c945d0-0e04-4093-b54e-ad5ad357e3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263198318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.4263198318
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2112392506
Short name T745
Test name
Test status
Simulation time 2132223051 ps
CPU time 1.93 seconds
Started Aug 19 04:48:45 PM PDT 24
Finished Aug 19 04:48:48 PM PDT 24
Peak memory 201064 kb
Host smart-ee3e0889-a5aa-4d58-a4d6-5a9f1cc3f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112392506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2112392506
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.1209473954
Short name T723
Test name
Test status
Simulation time 804068368602 ps
CPU time 485.62 seconds
Started Aug 19 04:48:49 PM PDT 24
Finished Aug 19 04:56:55 PM PDT 24
Peak memory 201116 kb
Host smart-e03fb51e-a1b0-49f5-a615-fcc05becb3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209473954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.1209473954
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.400995265
Short name T277
Test name
Test status
Simulation time 5625821218 ps
CPU time 16.17 seconds
Started Aug 19 04:48:49 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 209584 kb
Host smart-5e53cdf2-9b7a-4f59-91ba-e0e9c201b71d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400995265 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.400995265
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2826535018
Short name T500
Test name
Test status
Simulation time 8176016545 ps
CPU time 8.28 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:48:59 PM PDT 24
Peak memory 201160 kb
Host smart-944b3ba5-0efb-454f-8563-15f2c4634387
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826535018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2826535018
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.313584250
Short name T593
Test name
Test status
Simulation time 2012598749 ps
CPU time 5.82 seconds
Started Aug 19 04:48:54 PM PDT 24
Finished Aug 19 04:49:00 PM PDT 24
Peak memory 201092 kb
Host smart-fa9e3123-2e29-4f0a-a6f4-2d4d44c74f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313584250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_tes
t.313584250
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2751007295
Short name T705
Test name
Test status
Simulation time 3567637000 ps
CPU time 2.85 seconds
Started Aug 19 04:48:53 PM PDT 24
Finished Aug 19 04:48:56 PM PDT 24
Peak memory 201208 kb
Host smart-d341596d-f2ca-4ec5-8217-d30b361128a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751007295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.2
751007295
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.622997352
Short name T557
Test name
Test status
Simulation time 119085447579 ps
CPU time 303.99 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:54:00 PM PDT 24
Peak memory 201252 kb
Host smart-aa5c4436-fcd8-41c5-aa02-56e79af8b7fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622997352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.622997352
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3728606390
Short name T520
Test name
Test status
Simulation time 26837287901 ps
CPU time 33.91 seconds
Started Aug 19 04:48:52 PM PDT 24
Finished Aug 19 04:49:27 PM PDT 24
Peak memory 201332 kb
Host smart-8ecc690f-cecb-4bd5-b9e6-1df010a1ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728606390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3728606390
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.874637298
Short name T551
Test name
Test status
Simulation time 2569057391 ps
CPU time 3.9 seconds
Started Aug 19 04:48:54 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201128 kb
Host smart-5a21103c-ec47-48f4-80af-7eb2050c486c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874637298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ec_pwr_on_rst.874637298
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.636029702
Short name T199
Test name
Test status
Simulation time 3164307697 ps
CPU time 8.53 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:04 PM PDT 24
Peak memory 201116 kb
Host smart-0ebd4bd0-edbd-4604-bbd5-55fb490f211d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636029702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.636029702
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2267616831
Short name T687
Test name
Test status
Simulation time 2614991624 ps
CPU time 3.96 seconds
Started Aug 19 04:48:50 PM PDT 24
Finished Aug 19 04:48:54 PM PDT 24
Peak memory 201100 kb
Host smart-4528d661-f8c3-4a85-8927-d33b5d96c47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267616831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2267616831
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1620725216
Short name T759
Test name
Test status
Simulation time 2475225333 ps
CPU time 6.64 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201144 kb
Host smart-d0eb4232-70ca-441b-82b7-825d3ac6a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620725216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1620725216
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2205696691
Short name T719
Test name
Test status
Simulation time 2112358406 ps
CPU time 6.02 seconds
Started Aug 19 04:48:52 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201072 kb
Host smart-5dab76e3-c6a4-4401-b0bd-c7d55d885fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205696691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.2205696691
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1812185347
Short name T552
Test name
Test status
Simulation time 2537462688 ps
CPU time 2.35 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 200688 kb
Host smart-301c8bbb-ea61-40df-b199-d35e45b9af1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812185347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1812185347
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.2825789093
Short name T656
Test name
Test status
Simulation time 2127515436 ps
CPU time 1.8 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:48:53 PM PDT 24
Peak memory 201056 kb
Host smart-e8b77645-1ecb-4301-baa7-5f85016953d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825789093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.2825789093
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2441913019
Short name T658
Test name
Test status
Simulation time 17154063356 ps
CPU time 11.28 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:07 PM PDT 24
Peak memory 200688 kb
Host smart-ddb30b1c-69cb-4450-9936-871b606eb68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441913019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2441913019
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2878755154
Short name T15
Test name
Test status
Simulation time 7796459735 ps
CPU time 5.65 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:48:57 PM PDT 24
Peak memory 201152 kb
Host smart-586d40f3-02b3-4eff-bf44-441018f37675
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878755154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.2878755154
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.4195504872
Short name T770
Test name
Test status
Simulation time 2020783862 ps
CPU time 2.19 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 200996 kb
Host smart-72a7b1db-7e57-4002-8ae3-a5f4ce578c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195504872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.4195504872
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3675148071
Short name T48
Test name
Test status
Simulation time 3311603606 ps
CPU time 7.2 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201192 kb
Host smart-9b4789df-6d50-4c36-8e77-04dfe4df5504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675148071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.3
675148071
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.723497621
Short name T678
Test name
Test status
Simulation time 51924703130 ps
CPU time 32.55 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:27 PM PDT 24
Peak memory 201300 kb
Host smart-b46e0826-75f3-4a0b-b34c-c5196373eb8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723497621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_combo_detect.723497621
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3387776508
Short name T231
Test name
Test status
Simulation time 45006890238 ps
CPU time 122.77 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:50:59 PM PDT 24
Peak memory 201360 kb
Host smart-491d0483-1012-4989-918e-c40a15e800e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387776508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.3387776508
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3143151148
Short name T497
Test name
Test status
Simulation time 4469900498 ps
CPU time 6.08 seconds
Started Aug 19 04:48:51 PM PDT 24
Finished Aug 19 04:48:57 PM PDT 24
Peak memory 201104 kb
Host smart-6a72ed95-36af-47c2-8f9e-08cf73077e83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143151148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.3143151148
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1291923853
Short name T590
Test name
Test status
Simulation time 2610342348 ps
CPU time 7.15 seconds
Started Aug 19 04:48:53 PM PDT 24
Finished Aug 19 04:49:01 PM PDT 24
Peak memory 201092 kb
Host smart-addee062-55a7-45f1-a85c-c05c3ec9ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291923853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1291923853
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3376487237
Short name T531
Test name
Test status
Simulation time 2488477679 ps
CPU time 7.3 seconds
Started Aug 19 04:48:54 PM PDT 24
Finished Aug 19 04:49:01 PM PDT 24
Peak memory 201096 kb
Host smart-263843d1-6dff-40b4-8afa-7bb89eb98e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376487237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3376487237
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.2715027456
Short name T411
Test name
Test status
Simulation time 2232802905 ps
CPU time 1.78 seconds
Started Aug 19 04:48:53 PM PDT 24
Finished Aug 19 04:48:55 PM PDT 24
Peak memory 201064 kb
Host smart-cc1248b7-0fb8-4e0d-9122-42571be5d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715027456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.2715027456
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1921081395
Short name T222
Test name
Test status
Simulation time 2536899747 ps
CPU time 2.37 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:48:59 PM PDT 24
Peak memory 201136 kb
Host smart-a29ccf18-57c4-40c2-83a9-f3237cb68cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921081395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1921081395
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3302347923
Short name T646
Test name
Test status
Simulation time 2114620549 ps
CPU time 5.98 seconds
Started Aug 19 04:48:52 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201044 kb
Host smart-c319c440-ea9d-465d-a6d5-d9a106eed42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302347923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3302347923
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.2195818412
Short name T767
Test name
Test status
Simulation time 10844736885 ps
CPU time 6.49 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:49:03 PM PDT 24
Peak memory 201108 kb
Host smart-530b8e07-74cf-49c7-96e0-229a50b0a6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195818412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.2195818412
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1111599982
Short name T674
Test name
Test status
Simulation time 8946538423 ps
CPU time 12.69 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:08 PM PDT 24
Peak memory 217720 kb
Host smart-b9b08433-e26e-482f-8965-acef6679453a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111599982 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1111599982
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1745107985
Short name T676
Test name
Test status
Simulation time 12759746897 ps
CPU time 4.5 seconds
Started Aug 19 04:48:50 PM PDT 24
Finished Aug 19 04:48:54 PM PDT 24
Peak memory 201144 kb
Host smart-1719543a-4e7d-4061-8f57-dfadff22f660
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745107985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.1745107985
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.2672932200
Short name T50
Test name
Test status
Simulation time 2018917898 ps
CPU time 5.32 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:09 PM PDT 24
Peak memory 201136 kb
Host smart-f21f4e6e-fd9d-43d7-af8b-5d3c3d412fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672932200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.2672932200
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3958404375
Short name T605
Test name
Test status
Simulation time 3372661719 ps
CPU time 2.81 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:48:59 PM PDT 24
Peak memory 201212 kb
Host smart-2ce3849d-231e-434d-8a09-29149d44424a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958404375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
958404375
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3954167624
Short name T633
Test name
Test status
Simulation time 164956578665 ps
CPU time 49.73 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:44 PM PDT 24
Peak memory 201240 kb
Host smart-4e4e6d9b-62c7-4e1e-b06a-8d4c3d5575c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954167624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3954167624
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.921330551
Short name T786
Test name
Test status
Simulation time 48575205732 ps
CPU time 126.58 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:51:03 PM PDT 24
Peak memory 201328 kb
Host smart-ca6d2fc9-4de5-4b3f-b21f-221044c3746a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921330551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.921330551
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3148947543
Short name T387
Test name
Test status
Simulation time 2452896623 ps
CPU time 7.2 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:49:03 PM PDT 24
Peak memory 201160 kb
Host smart-db65f3be-f683-4190-99bd-931601fbcf1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148947543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.3148947543
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2144473013
Short name T195
Test name
Test status
Simulation time 2619286921 ps
CPU time 6.3 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:49:03 PM PDT 24
Peak memory 201144 kb
Host smart-fae57c49-229c-4b16-918b-8326063623b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144473013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.2144473013
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2442511573
Short name T164
Test name
Test status
Simulation time 2614413525 ps
CPU time 3.13 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:48:59 PM PDT 24
Peak memory 201100 kb
Host smart-b2805481-1eea-4bd3-854d-f4803483cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442511573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2442511573
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.2233719112
Short name T604
Test name
Test status
Simulation time 2481626812 ps
CPU time 2.14 seconds
Started Aug 19 04:48:56 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201152 kb
Host smart-de486c83-083f-4668-a16b-279c1c2143fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233719112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.2233719112
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.38345421
Short name T198
Test name
Test status
Simulation time 2052814428 ps
CPU time 2.13 seconds
Started Aug 19 04:48:59 PM PDT 24
Finished Aug 19 04:49:01 PM PDT 24
Peak memory 201088 kb
Host smart-d76cfd50-3c32-4f9e-a3f2-67fda9117497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38345421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.38345421
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.421595385
Short name T492
Test name
Test status
Simulation time 2535195471 ps
CPU time 2.4 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:48:57 PM PDT 24
Peak memory 201148 kb
Host smart-682b2ad6-49bb-43bb-9296-1e82a80cb0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421595385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.421595385
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.30048038
Short name T469
Test name
Test status
Simulation time 2109976847 ps
CPU time 5.82 seconds
Started Aug 19 04:48:58 PM PDT 24
Finished Aug 19 04:49:04 PM PDT 24
Peak memory 201056 kb
Host smart-a470aa23-7c87-4cf2-881c-986a5b1e7baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30048038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.30048038
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.3863583207
Short name T746
Test name
Test status
Simulation time 10212693946 ps
CPU time 6.01 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:49:03 PM PDT 24
Peak memory 201116 kb
Host smart-b1f7a6c4-8279-4bfd-8f22-45797a875cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863583207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.3863583207
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2794476582
Short name T286
Test name
Test status
Simulation time 3527535724 ps
CPU time 9.24 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:49:06 PM PDT 24
Peak memory 201292 kb
Host smart-0bd84671-fb61-4015-ad0b-67a69c651d60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794476582 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2794476582
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.328450951
Short name T463
Test name
Test status
Simulation time 2026152398 ps
CPU time 2.36 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:47:49 PM PDT 24
Peak memory 201104 kb
Host smart-316fdfe1-7a01-4889-b927-472a29d5226b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328450951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test
.328450951
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.751785777
Short name T92
Test name
Test status
Simulation time 5727225769 ps
CPU time 7.88 seconds
Started Aug 19 04:47:46 PM PDT 24
Finished Aug 19 04:47:55 PM PDT 24
Peak memory 201180 kb
Host smart-f690c3f8-65b4-4c7c-a7f3-5866710d19a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751785777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.751785777
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3196964375
Short name T237
Test name
Test status
Simulation time 155553866196 ps
CPU time 397.35 seconds
Started Aug 19 04:47:46 PM PDT 24
Finished Aug 19 04:54:23 PM PDT 24
Peak memory 201332 kb
Host smart-88002f48-37e0-48aa-987d-685d98856a4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196964375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3196964375
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.842122275
Short name T785
Test name
Test status
Simulation time 2539088398 ps
CPU time 3.71 seconds
Started Aug 19 04:47:44 PM PDT 24
Finished Aug 19 04:47:48 PM PDT 24
Peak memory 201124 kb
Host smart-b496e0a6-fa85-4e62-a013-87786904c643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842122275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.842122275
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1993487411
Short name T403
Test name
Test status
Simulation time 3675970273 ps
CPU time 2.88 seconds
Started Aug 19 04:47:45 PM PDT 24
Finished Aug 19 04:47:48 PM PDT 24
Peak memory 201140 kb
Host smart-279afddc-a230-47e2-98e1-b57c4d968620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993487411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.1993487411
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.454934072
Short name T662
Test name
Test status
Simulation time 2798313231 ps
CPU time 2.08 seconds
Started Aug 19 04:47:45 PM PDT 24
Finished Aug 19 04:47:47 PM PDT 24
Peak memory 201080 kb
Host smart-38a7446c-fcbe-4d6c-ba64-6408cf891221
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454934072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_edge_detect.454934072
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1648601695
Short name T522
Test name
Test status
Simulation time 2609380109 ps
CPU time 7.25 seconds
Started Aug 19 04:47:45 PM PDT 24
Finished Aug 19 04:47:53 PM PDT 24
Peak memory 201088 kb
Host smart-d0afa001-e8e5-4d6e-8b60-f5a0393b68cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648601695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1648601695
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3994638226
Short name T298
Test name
Test status
Simulation time 2498645319 ps
CPU time 2.19 seconds
Started Aug 19 04:47:45 PM PDT 24
Finished Aug 19 04:47:47 PM PDT 24
Peak memory 201152 kb
Host smart-2a8a147c-228c-4942-8919-5b32c9f12958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994638226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3994638226
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.3333575592
Short name T426
Test name
Test status
Simulation time 2141539984 ps
CPU time 3.19 seconds
Started Aug 19 04:47:45 PM PDT 24
Finished Aug 19 04:47:48 PM PDT 24
Peak memory 201056 kb
Host smart-1d5e1605-6a92-4f21-b2cb-1d0c81a4f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333575592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3333575592
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1734812484
Short name T488
Test name
Test status
Simulation time 2522563459 ps
CPU time 2.34 seconds
Started Aug 19 04:47:48 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 201136 kb
Host smart-a83557bc-c7ed-4669-be06-8d6fda1149b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734812484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1734812484
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.169367041
Short name T254
Test name
Test status
Simulation time 42010836562 ps
CPU time 104.74 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:49:32 PM PDT 24
Peak memory 220652 kb
Host smart-1206feea-b07d-4689-8da7-615cacb763a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169367041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.169367041
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.340077432
Short name T162
Test name
Test status
Simulation time 2131570798 ps
CPU time 2.01 seconds
Started Aug 19 04:47:38 PM PDT 24
Finished Aug 19 04:47:40 PM PDT 24
Peak memory 201060 kb
Host smart-7bd5701f-e25f-4b29-8e4e-006253af046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340077432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.340077432
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3017894634
Short name T369
Test name
Test status
Simulation time 17985532300 ps
CPU time 28.02 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:48:15 PM PDT 24
Peak memory 201084 kb
Host smart-a5307883-8877-4d60-84d9-837f7ea70311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017894634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3017894634
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.792799128
Short name T739
Test name
Test status
Simulation time 8290235013 ps
CPU time 11.05 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:47:58 PM PDT 24
Peak memory 201292 kb
Host smart-77375417-55f0-4194-bfd3-5a0060c8bc29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792799128 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.792799128
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.428601902
Short name T117
Test name
Test status
Simulation time 4694252318 ps
CPU time 3.29 seconds
Started Aug 19 04:47:45 PM PDT 24
Finished Aug 19 04:47:49 PM PDT 24
Peak memory 201144 kb
Host smart-248d3a8f-b4e1-4a54-b652-0ba9a382ce55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428601902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ultra_low_pwr.428601902
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.497018585
Short name T543
Test name
Test status
Simulation time 2013964488 ps
CPU time 5.48 seconds
Started Aug 19 04:49:04 PM PDT 24
Finished Aug 19 04:49:09 PM PDT 24
Peak memory 201144 kb
Host smart-15feefa1-7b20-4cc0-b66b-f118d83eed55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497018585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_tes
t.497018585
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1592280098
Short name T43
Test name
Test status
Simulation time 3630769827 ps
CPU time 9.92 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 201208 kb
Host smart-ec661ac5-423c-4203-b1c0-619cf78251a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592280098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.1
592280098
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.1277077148
Short name T96
Test name
Test status
Simulation time 56868987344 ps
CPU time 123.13 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:51:06 PM PDT 24
Peak memory 201312 kb
Host smart-4dc392de-d747-4bf2-b7f7-0c36e878c152
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277077148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.1277077148
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1621092449
Short name T349
Test name
Test status
Simulation time 133812146820 ps
CPU time 90.7 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:50:33 PM PDT 24
Peak memory 201396 kb
Host smart-15c8ffb0-f5af-430c-9428-5297bc5182d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621092449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.1621092449
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3999643209
Short name T294
Test name
Test status
Simulation time 2996995838 ps
CPU time 7.8 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:03 PM PDT 24
Peak memory 201144 kb
Host smart-e0b3b537-faef-44ab-ab36-d7ab526de0fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999643209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3999643209
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.791057942
Short name T152
Test name
Test status
Simulation time 2631950067 ps
CPU time 2.23 seconds
Started Aug 19 04:48:59 PM PDT 24
Finished Aug 19 04:49:02 PM PDT 24
Peak memory 201140 kb
Host smart-f0f277ac-10c8-47c4-8bee-d279662d6633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791057942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.791057942
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1586920198
Short name T653
Test name
Test status
Simulation time 2478892620 ps
CPU time 1.3 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201136 kb
Host smart-8943cebb-a431-431a-b25b-6479fbdee3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586920198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1586920198
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3311960676
Short name T566
Test name
Test status
Simulation time 2260517584 ps
CPU time 6.43 seconds
Started Aug 19 04:48:57 PM PDT 24
Finished Aug 19 04:49:04 PM PDT 24
Peak memory 201116 kb
Host smart-9de61d6f-f7be-4f57-a65a-5fd2fd5a130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311960676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3311960676
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2816718056
Short name T672
Test name
Test status
Simulation time 2537287222 ps
CPU time 2 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 201140 kb
Host smart-9a91ba78-801c-4f70-8b30-257d716d3bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816718056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2816718056
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1123630465
Short name T498
Test name
Test status
Simulation time 2111326283 ps
CPU time 6.07 seconds
Started Aug 19 04:48:59 PM PDT 24
Finished Aug 19 04:49:06 PM PDT 24
Peak memory 201056 kb
Host smart-7222cba3-fd71-468a-bcc9-5a6ffce9b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123630465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1123630465
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3628881510
Short name T172
Test name
Test status
Simulation time 6554954414 ps
CPU time 9.05 seconds
Started Aug 19 04:48:55 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 201112 kb
Host smart-38d650ca-310f-4e59-af91-0b97a27c4c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628881510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3628881510
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.926934112
Short name T133
Test name
Test status
Simulation time 5340903014 ps
CPU time 5.16 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:09 PM PDT 24
Peak memory 210804 kb
Host smart-fc953623-8913-4b64-9ed7-3c5950ff4e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926934112 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.926934112
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.4615267
Short name T397
Test name
Test status
Simulation time 2032034704 ps
CPU time 1.82 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:11 PM PDT 24
Peak memory 201140 kb
Host smart-28a40c06-d855-496e-8c53-bbe309ecfe16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4615267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.4615267
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1788580152
Short name T661
Test name
Test status
Simulation time 3706789711 ps
CPU time 2.48 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 201236 kb
Host smart-869ab19d-78e2-4dd0-a3a0-bd19ded0aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788580152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1
788580152
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3600044111
Short name T99
Test name
Test status
Simulation time 32211388356 ps
CPU time 85.69 seconds
Started Aug 19 04:49:07 PM PDT 24
Finished Aug 19 04:50:33 PM PDT 24
Peak memory 201252 kb
Host smart-425333bf-b650-4cf1-9111-b6cfe4cdaea8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600044111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3600044111
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2802256358
Short name T790
Test name
Test status
Simulation time 3413491933 ps
CPU time 8.92 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:12 PM PDT 24
Peak memory 201132 kb
Host smart-e470a90d-c5aa-4165-85cc-4102bd9cfa9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802256358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.2802256358
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2995138891
Short name T668
Test name
Test status
Simulation time 3704140458 ps
CPU time 10.35 seconds
Started Aug 19 04:49:07 PM PDT 24
Finished Aug 19 04:49:17 PM PDT 24
Peak memory 201108 kb
Host smart-f49490bc-5ee0-4528-ac0c-3a98cdceef9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995138891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.2995138891
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.633056066
Short name T542
Test name
Test status
Simulation time 2619757777 ps
CPU time 3.21 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:07 PM PDT 24
Peak memory 201140 kb
Host smart-61fe13f7-c713-4a3c-b877-90ec32672bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633056066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.633056066
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3462404897
Short name T16
Test name
Test status
Simulation time 2467238090 ps
CPU time 6.85 seconds
Started Aug 19 04:48:59 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 201168 kb
Host smart-d17bd0d6-1808-46ce-97be-4e1ef10f609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462404897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3462404897
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3863473349
Short name T270
Test name
Test status
Simulation time 2353463912 ps
CPU time 1.07 seconds
Started Aug 19 04:48:59 PM PDT 24
Finished Aug 19 04:49:00 PM PDT 24
Peak memory 201140 kb
Host smart-56a1f76f-e565-460a-8953-66b9a4ad3c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863473349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3863473349
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.4193895786
Short name T467
Test name
Test status
Simulation time 2509021814 ps
CPU time 7.37 seconds
Started Aug 19 04:49:04 PM PDT 24
Finished Aug 19 04:49:11 PM PDT 24
Peak memory 201136 kb
Host smart-ab4b180b-f0be-409d-81ed-0ab58920c1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193895786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.4193895786
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.3033112954
Short name T422
Test name
Test status
Simulation time 2117083001 ps
CPU time 3.32 seconds
Started Aug 19 04:49:03 PM PDT 24
Finished Aug 19 04:49:07 PM PDT 24
Peak memory 201068 kb
Host smart-7d26b1b8-cb5e-470e-acc8-0d420b130a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033112954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.3033112954
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.1516135519
Short name T379
Test name
Test status
Simulation time 1812751225307 ps
CPU time 754.59 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 05:01:44 PM PDT 24
Peak memory 201228 kb
Host smart-3c00a684-f64a-4c76-8abf-ad0e33d9abca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516135519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.1516135519
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3216772840
Short name T305
Test name
Test status
Simulation time 3709574130 ps
CPU time 9.79 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:18 PM PDT 24
Peak memory 201272 kb
Host smart-aed86631-f7b4-4765-a97d-37a351e9bbd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216772840 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3216772840
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2480299495
Short name T509
Test name
Test status
Simulation time 2034568543 ps
CPU time 1.86 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:11 PM PDT 24
Peak memory 201144 kb
Host smart-d0aa4eca-2d9b-49f6-84c4-f65f7e7057b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480299495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2480299495
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1962050223
Short name T722
Test name
Test status
Simulation time 3089521912 ps
CPU time 4.46 seconds
Started Aug 19 04:49:10 PM PDT 24
Finished Aug 19 04:49:15 PM PDT 24
Peak memory 201204 kb
Host smart-b56b6759-6d6c-4a1a-a3c4-77d1cf2654b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962050223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1
962050223
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.893085409
Short name T344
Test name
Test status
Simulation time 130280969774 ps
CPU time 123.98 seconds
Started Aug 19 04:49:14 PM PDT 24
Finished Aug 19 04:51:18 PM PDT 24
Peak memory 201308 kb
Host smart-5cbde018-c7cb-4878-808a-466fab443d6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893085409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_combo_detect.893085409
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2485176042
Short name T706
Test name
Test status
Simulation time 118860852701 ps
CPU time 37.9 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:45 PM PDT 24
Peak memory 201368 kb
Host smart-8b2dda7e-d330-4718-9081-73e1eb535a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485176042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2485176042
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.928359603
Short name T716
Test name
Test status
Simulation time 3494410862 ps
CPU time 8.82 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:18 PM PDT 24
Peak memory 201128 kb
Host smart-15848099-19dc-4792-80e1-e12c5e60b39d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928359603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ec_pwr_on_rst.928359603
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3799384379
Short name T454
Test name
Test status
Simulation time 2623416020 ps
CPU time 2.45 seconds
Started Aug 19 04:49:14 PM PDT 24
Finished Aug 19 04:49:16 PM PDT 24
Peak memory 201136 kb
Host smart-291ec3d5-9907-4c43-bfb6-dc551a7207ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799384379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3799384379
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.928326446
Short name T733
Test name
Test status
Simulation time 2492971846 ps
CPU time 1.67 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201140 kb
Host smart-eb587372-53b7-452f-9b84-279367a97886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928326446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.928326446
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3936285652
Short name T720
Test name
Test status
Simulation time 2159291371 ps
CPU time 2.05 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201176 kb
Host smart-c525b855-ecfa-474f-bfbf-71f723c20073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936285652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3936285652
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1337256522
Short name T789
Test name
Test status
Simulation time 2519764364 ps
CPU time 4.06 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 201152 kb
Host smart-30befe56-7cdc-4114-bcb8-4df8c0325d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337256522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1337256522
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.134943304
Short name T386
Test name
Test status
Simulation time 2126874203 ps
CPU time 2.12 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201076 kb
Host smart-c1e8f295-ed52-4e67-b4a5-a6e76d3f863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134943304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.134943304
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1317399563
Short name T771
Test name
Test status
Simulation time 15434000648 ps
CPU time 26.85 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:35 PM PDT 24
Peak memory 201120 kb
Host smart-e5eb0b6f-1030-4d6b-bf79-afc512ec6566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317399563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1317399563
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.798733980
Short name T757
Test name
Test status
Simulation time 17260446740 ps
CPU time 10.89 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:20 PM PDT 24
Peak memory 209704 kb
Host smart-beec6ff1-8323-4ab1-9ea0-ea18c44a3669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798733980 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.798733980
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3683529606
Short name T115
Test name
Test status
Simulation time 9285296572 ps
CPU time 8.35 seconds
Started Aug 19 04:49:07 PM PDT 24
Finished Aug 19 04:49:16 PM PDT 24
Peak memory 201132 kb
Host smart-fe143394-1c78-42f3-9007-8b41ecc98845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683529606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3683529606
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.94620508
Short name T747
Test name
Test status
Simulation time 2009009136 ps
CPU time 5.99 seconds
Started Aug 19 04:49:11 PM PDT 24
Finished Aug 19 04:49:17 PM PDT 24
Peak memory 201072 kb
Host smart-0b01fa88-329e-490e-9c1c-711d46a5021f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94620508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test
.94620508
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2948065759
Short name T442
Test name
Test status
Simulation time 237414310577 ps
CPU time 91.66 seconds
Started Aug 19 04:49:11 PM PDT 24
Finished Aug 19 04:50:43 PM PDT 24
Peak memory 201212 kb
Host smart-2558129d-3a19-4fab-b817-d3cf589bb869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948065759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
948065759
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3717168297
Short name T229
Test name
Test status
Simulation time 63551661197 ps
CPU time 31.16 seconds
Started Aug 19 04:49:14 PM PDT 24
Finished Aug 19 04:49:45 PM PDT 24
Peak memory 201308 kb
Host smart-a4852a3b-ca40-443b-996d-a8bad74899ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717168297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3717168297
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2603880532
Short name T55
Test name
Test status
Simulation time 5223629594 ps
CPU time 3.8 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:12 PM PDT 24
Peak memory 201144 kb
Host smart-247b0491-199b-42b5-a68b-9320dcd8a61c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603880532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.2603880532
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3257569932
Short name T156
Test name
Test status
Simulation time 3902393894 ps
CPU time 2.53 seconds
Started Aug 19 04:49:10 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 201076 kb
Host smart-9c3ef7f3-e697-4c12-9737-41f0134e058f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257569932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3257569932
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.811816871
Short name T776
Test name
Test status
Simulation time 2619526738 ps
CPU time 4.41 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:12 PM PDT 24
Peak memory 201112 kb
Host smart-6f57a1b0-6949-47c9-9eec-d1a9bd91e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811816871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.811816871
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.4079147837
Short name T582
Test name
Test status
Simulation time 2465871329 ps
CPU time 6.6 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:15 PM PDT 24
Peak memory 201148 kb
Host smart-392cbdc2-41c1-4d88-9e05-045d00b1b18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079147837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.4079147837
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1774592616
Short name T167
Test name
Test status
Simulation time 2166360970 ps
CPU time 6.11 seconds
Started Aug 19 04:49:14 PM PDT 24
Finished Aug 19 04:49:20 PM PDT 24
Peak memory 201132 kb
Host smart-ac4b9553-c83d-4fac-afc1-d0178767ee88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774592616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1774592616
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1830123956
Short name T663
Test name
Test status
Simulation time 2529279200 ps
CPU time 2.26 seconds
Started Aug 19 04:49:10 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 201140 kb
Host smart-c785102b-1ca6-450e-a275-0d4367eb3f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830123956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1830123956
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.1035875903
Short name T191
Test name
Test status
Simulation time 2132366016 ps
CPU time 1.59 seconds
Started Aug 19 04:49:07 PM PDT 24
Finished Aug 19 04:49:08 PM PDT 24
Peak memory 201064 kb
Host smart-7a80991b-ada8-4a7a-996b-8d031e46999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035875903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.1035875903
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.1500891588
Short name T399
Test name
Test status
Simulation time 7322106172 ps
CPU time 20.53 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:30 PM PDT 24
Peak memory 201200 kb
Host smart-f3ec39e1-c9c1-4bdd-97f6-72f90ba10618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500891588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.1500891588
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.4007986847
Short name T307
Test name
Test status
Simulation time 15778392867 ps
CPU time 12.08 seconds
Started Aug 19 04:49:11 PM PDT 24
Finished Aug 19 04:49:23 PM PDT 24
Peak memory 209728 kb
Host smart-d0556aff-3091-41ed-8294-a6fee4f04242
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007986847 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.4007986847
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.679883199
Short name T75
Test name
Test status
Simulation time 5810592858 ps
CPU time 2.33 seconds
Started Aug 19 04:49:10 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 201080 kb
Host smart-d58929d8-180b-479c-8df3-9a6f98966efb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679883199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ultra_low_pwr.679883199
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.623375247
Short name T163
Test name
Test status
Simulation time 2036535754 ps
CPU time 2.12 seconds
Started Aug 19 04:49:19 PM PDT 24
Finished Aug 19 04:49:21 PM PDT 24
Peak memory 201136 kb
Host smart-933ef9c6-903e-42ad-af4e-6b0d5198bc09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623375247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes
t.623375247
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2153899368
Short name T485
Test name
Test status
Simulation time 228319321215 ps
CPU time 133.57 seconds
Started Aug 19 04:49:21 PM PDT 24
Finished Aug 19 04:51:35 PM PDT 24
Peak memory 201208 kb
Host smart-414b27ff-bf63-4c10-bce8-20eeb1e137db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153899368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
153899368
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3894751630
Short name T690
Test name
Test status
Simulation time 200463488965 ps
CPU time 29.02 seconds
Started Aug 19 04:49:18 PM PDT 24
Finished Aug 19 04:49:48 PM PDT 24
Peak memory 201252 kb
Host smart-27568af8-6a5a-4f3f-819b-5668ada9f08c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894751630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.3894751630
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.987159515
Short name T484
Test name
Test status
Simulation time 4841553824 ps
CPU time 12.27 seconds
Started Aug 19 04:49:11 PM PDT 24
Finished Aug 19 04:49:23 PM PDT 24
Peak memory 201128 kb
Host smart-e0c6296d-bd55-4922-83da-05df86274237
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987159515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.987159515
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1382992871
Short name T34
Test name
Test status
Simulation time 3874112014 ps
CPU time 3.45 seconds
Started Aug 19 04:49:19 PM PDT 24
Finished Aug 19 04:49:22 PM PDT 24
Peak memory 201156 kb
Host smart-86b48f22-1b1b-4533-bc4b-287069d23781
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382992871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1382992871
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.4164248349
Short name T523
Test name
Test status
Simulation time 2612823441 ps
CPU time 7.7 seconds
Started Aug 19 04:49:09 PM PDT 24
Finished Aug 19 04:49:17 PM PDT 24
Peak memory 201144 kb
Host smart-a8d2f85f-ea6c-42d9-9b46-10f4f0c39186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164248349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.4164248349
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3363943837
Short name T502
Test name
Test status
Simulation time 2477006707 ps
CPU time 2.39 seconds
Started Aug 19 04:49:07 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201140 kb
Host smart-1965fa54-69f4-403f-8097-e354aa9f4ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363943837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3363943837
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1252753777
Short name T272
Test name
Test status
Simulation time 2040578770 ps
CPU time 5.81 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:14 PM PDT 24
Peak memory 201072 kb
Host smart-11de70ca-ec78-42bb-b1b4-aeec6710a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252753777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1252753777
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2337160725
Short name T744
Test name
Test status
Simulation time 2516095105 ps
CPU time 4.48 seconds
Started Aug 19 04:49:10 PM PDT 24
Finished Aug 19 04:49:14 PM PDT 24
Peak memory 201096 kb
Host smart-2d8ec112-9b80-4afe-9b4c-5b33e9de6b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337160725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2337160725
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.3906622566
Short name T223
Test name
Test status
Simulation time 2135484139 ps
CPU time 1.83 seconds
Started Aug 19 04:49:08 PM PDT 24
Finished Aug 19 04:49:10 PM PDT 24
Peak memory 201056 kb
Host smart-e4eadc5c-284a-402c-bf1d-c0c2791e3665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906622566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3906622566
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.3055403281
Short name T182
Test name
Test status
Simulation time 19322399763 ps
CPU time 14.13 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:34 PM PDT 24
Peak memory 201136 kb
Host smart-add5eade-dad1-4951-bcb2-bec0388aa88a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055403281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.3055403281
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1035257002
Short name T184
Test name
Test status
Simulation time 6248343627 ps
CPU time 17.61 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:38 PM PDT 24
Peak memory 212000 kb
Host smart-9ae4ac38-becc-4a17-bf50-f7569cf493f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035257002 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1035257002
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2749083303
Short name T380
Test name
Test status
Simulation time 3397033343649 ps
CPU time 108.03 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:51:17 PM PDT 24
Peak memory 201136 kb
Host smart-adc0bfeb-4ba7-4831-9f88-1b0ec3fe672e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749083303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.2749083303
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2743105422
Short name T405
Test name
Test status
Simulation time 2022965791 ps
CPU time 3.13 seconds
Started Aug 19 04:49:18 PM PDT 24
Finished Aug 19 04:49:21 PM PDT 24
Peak memory 201160 kb
Host smart-6a75ea45-a02b-44e4-ad30-f307deeb4acf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743105422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2743105422
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2742471015
Short name T735
Test name
Test status
Simulation time 3514336558 ps
CPU time 4.94 seconds
Started Aug 19 04:49:18 PM PDT 24
Finished Aug 19 04:49:23 PM PDT 24
Peak memory 201204 kb
Host smart-c548daa1-2c54-4fd3-b0d5-f0be296912fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742471015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2
742471015
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.421130362
Short name T26
Test name
Test status
Simulation time 82072459948 ps
CPU time 98.31 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:51:07 PM PDT 24
Peak memory 201312 kb
Host smart-f35d0c8d-267a-468a-b166-721db211b173
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421130362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_combo_detect.421130362
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2858233234
Short name T684
Test name
Test status
Simulation time 2626517407 ps
CPU time 2.2 seconds
Started Aug 19 04:49:21 PM PDT 24
Finished Aug 19 04:49:23 PM PDT 24
Peak memory 201024 kb
Host smart-a7142c1f-5401-4bc1-a432-752a974dd571
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858233234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2858233234
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.1976894029
Short name T35
Test name
Test status
Simulation time 5920238817 ps
CPU time 12.76 seconds
Started Aug 19 04:49:21 PM PDT 24
Finished Aug 19 04:49:34 PM PDT 24
Peak memory 201040 kb
Host smart-3628dbbc-f6da-407a-8ed6-012ef57b355b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976894029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.1976894029
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3333497186
Short name T517
Test name
Test status
Simulation time 2624194681 ps
CPU time 2.5 seconds
Started Aug 19 04:49:18 PM PDT 24
Finished Aug 19 04:49:21 PM PDT 24
Peak memory 201152 kb
Host smart-488d0c63-af35-4b70-9bb7-a66f8f4c1963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333497186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3333497186
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.296859546
Short name T584
Test name
Test status
Simulation time 2477713277 ps
CPU time 7.31 seconds
Started Aug 19 04:49:19 PM PDT 24
Finished Aug 19 04:49:26 PM PDT 24
Peak memory 201164 kb
Host smart-bc5d2690-3de9-4b84-8bed-cd779e7f1820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296859546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.296859546
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.742113154
Short name T534
Test name
Test status
Simulation time 2267518624 ps
CPU time 3.57 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:24 PM PDT 24
Peak memory 201152 kb
Host smart-46894272-61c6-45ec-af8f-fba9373e2b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742113154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.742113154
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1902125424
Short name T659
Test name
Test status
Simulation time 2511864360 ps
CPU time 7.08 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:27 PM PDT 24
Peak memory 201168 kb
Host smart-29170dbe-181a-47a4-bdc2-984cb2c0caf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902125424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1902125424
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.615437364
Short name T159
Test name
Test status
Simulation time 2118104779 ps
CPU time 3.36 seconds
Started Aug 19 04:49:18 PM PDT 24
Finished Aug 19 04:49:22 PM PDT 24
Peak memory 201048 kb
Host smart-468d2c08-4174-4178-b090-55135b1512ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615437364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.615437364
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2822298586
Short name T545
Test name
Test status
Simulation time 7710073483 ps
CPU time 11.23 seconds
Started Aug 19 04:49:21 PM PDT 24
Finished Aug 19 04:49:32 PM PDT 24
Peak memory 209640 kb
Host smart-8923d500-5cc3-41a0-9e9a-dcc963532184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822298586 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2822298586
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1153026293
Short name T610
Test name
Test status
Simulation time 9968845523 ps
CPU time 9.19 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:37 PM PDT 24
Peak memory 201132 kb
Host smart-1a99e594-809c-4ed7-88fa-9e2fd294aec7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153026293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.1153026293
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1239668911
Short name T209
Test name
Test status
Simulation time 2036048351 ps
CPU time 1.75 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:30 PM PDT 24
Peak memory 201136 kb
Host smart-54a3d3f8-00e3-4f20-872d-5839b251a5dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239668911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1239668911
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3666825898
Short name T596
Test name
Test status
Simulation time 3758901025 ps
CPU time 5.07 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:34 PM PDT 24
Peak memory 201204 kb
Host smart-4273c436-f307-4426-b087-b0ba79cb693c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666825898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3
666825898
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3144592719
Short name T94
Test name
Test status
Simulation time 85798202262 ps
CPU time 222.76 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:53:11 PM PDT 24
Peak memory 201252 kb
Host smart-1760f3cd-1292-4f96-aed0-3607b4b30106
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144592719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3144592719
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4277468708
Short name T357
Test name
Test status
Simulation time 125605382047 ps
CPU time 82.8 seconds
Started Aug 19 04:49:16 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201328 kb
Host smart-4d6a8863-36c1-4355-a6a7-aa6560f767b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277468708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.4277468708
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.4284961533
Short name T435
Test name
Test status
Simulation time 3968914401 ps
CPU time 3.6 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:32 PM PDT 24
Peak memory 201128 kb
Host smart-ee43d5eb-01aa-47d6-a139-055622a87bd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284961533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.4284961533
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.467084440
Short name T139
Test name
Test status
Simulation time 5837854750 ps
CPU time 13.03 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 201108 kb
Host smart-f56348eb-6e1a-4d76-ad99-01253a77eb07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467084440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_edge_detect.467084440
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3286434277
Short name T754
Test name
Test status
Simulation time 2627319682 ps
CPU time 2.33 seconds
Started Aug 19 04:49:23 PM PDT 24
Finished Aug 19 04:49:25 PM PDT 24
Peak memory 201088 kb
Host smart-75b11ee7-753f-48ea-b0aa-00055d0ab16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286434277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3286434277
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3564627210
Short name T652
Test name
Test status
Simulation time 2487784011 ps
CPU time 2.48 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 201136 kb
Host smart-597d7f60-9bd5-4b21-9ab4-209417f17f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564627210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3564627210
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.1898410066
Short name T625
Test name
Test status
Simulation time 2290679117 ps
CPU time 1.18 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:21 PM PDT 24
Peak memory 201148 kb
Host smart-f0403303-0f45-4736-bb28-3e577e323134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898410066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1898410066
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2210531461
Short name T69
Test name
Test status
Simulation time 2714713732 ps
CPU time 1.11 seconds
Started Aug 19 04:49:17 PM PDT 24
Finished Aug 19 04:49:18 PM PDT 24
Peak memory 201152 kb
Host smart-7c9293b9-0a74-4c3b-87fb-d20681386023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210531461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2210531461
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3077126908
Short name T293
Test name
Test status
Simulation time 2108809558 ps
CPU time 5.53 seconds
Started Aug 19 04:49:17 PM PDT 24
Finished Aug 19 04:49:23 PM PDT 24
Peak memory 201032 kb
Host smart-19c8a707-3ce2-488b-801d-273f8193c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077126908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3077126908
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.3590406507
Short name T413
Test name
Test status
Simulation time 8771684426 ps
CPU time 6.74 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:27 PM PDT 24
Peak memory 201116 kb
Host smart-ed5d697e-c20b-4456-a0a4-e4e288a1ff93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590406507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.3590406507
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.4256307160
Short name T603
Test name
Test status
Simulation time 21026303564 ps
CPU time 11.25 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 217748 kb
Host smart-b67b4f61-432d-4e94-95d8-70338163a3d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256307160 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.4256307160
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3138023998
Short name T304
Test name
Test status
Simulation time 2977664043 ps
CPU time 4.6 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:33 PM PDT 24
Peak memory 201164 kb
Host smart-34dbc371-9882-4578-915b-96f508351231
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138023998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.3138023998
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.814783913
Short name T482
Test name
Test status
Simulation time 2017646891 ps
CPU time 3.32 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:33 PM PDT 24
Peak memory 201136 kb
Host smart-7e8c81e8-a869-4716-8a63-3acc9001a664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814783913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_tes
t.814783913
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.793005306
Short name T564
Test name
Test status
Simulation time 161983847363 ps
CPU time 380.47 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:55:48 PM PDT 24
Peak memory 201168 kb
Host smart-647bf12a-91c9-498d-9af0-f3bb063cce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793005306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.793005306
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1157130527
Short name T46
Test name
Test status
Simulation time 174192787411 ps
CPU time 71.66 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201280 kb
Host smart-d025e406-f77a-4e1d-a464-945e7f2ab7d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157130527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.1157130527
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4202871324
Short name T56
Test name
Test status
Simulation time 4108777639 ps
CPU time 11.14 seconds
Started Aug 19 04:49:25 PM PDT 24
Finished Aug 19 04:49:37 PM PDT 24
Peak memory 201128 kb
Host smart-7ad87e22-8462-42d5-8866-a31afc20e6f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202871324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.4202871324
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1348835996
Short name T526
Test name
Test status
Simulation time 2608613223 ps
CPU time 2.03 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 201140 kb
Host smart-822e2507-ae5c-4ca0-9044-27f517f1f401
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348835996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1348835996
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.4272868934
Short name T201
Test name
Test status
Simulation time 2627834802 ps
CPU time 2.73 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:32 PM PDT 24
Peak memory 201136 kb
Host smart-0225b085-fac2-4c23-81c4-972d5277e2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272868934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.4272868934
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3393859599
Short name T441
Test name
Test status
Simulation time 2455777814 ps
CPU time 3.77 seconds
Started Aug 19 04:49:18 PM PDT 24
Finished Aug 19 04:49:22 PM PDT 24
Peak memory 201164 kb
Host smart-21487934-7499-4787-ba1d-fd230e210327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393859599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3393859599
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3892124757
Short name T150
Test name
Test status
Simulation time 2271684899 ps
CPU time 2.24 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 201128 kb
Host smart-a0eb9e04-6a91-4d3e-a94f-2d5d58aa1611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892124757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3892124757
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.958784639
Short name T5
Test name
Test status
Simulation time 2517929778 ps
CPU time 4.06 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:25 PM PDT 24
Peak memory 201136 kb
Host smart-1efeb80e-80da-46d8-a5fc-5844ff2004cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958784639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.958784639
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.3614931246
Short name T166
Test name
Test status
Simulation time 2125796845 ps
CPU time 1.91 seconds
Started Aug 19 04:49:20 PM PDT 24
Finished Aug 19 04:49:22 PM PDT 24
Peak memory 201052 kb
Host smart-0a305f8b-0ecb-4c10-a218-f7c0e1ee4425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614931246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3614931246
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.3763444461
Short name T241
Test name
Test status
Simulation time 130282285977 ps
CPU time 323.07 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:54:52 PM PDT 24
Peak memory 201296 kb
Host smart-4af486f7-3916-41d6-980d-60188f1e00d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763444461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.3763444461
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1230766979
Short name T524
Test name
Test status
Simulation time 12141683198 ps
CPU time 2.77 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:32 PM PDT 24
Peak memory 201168 kb
Host smart-051c2eda-8a8e-4ebd-b277-862215531662
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230766979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.1230766979
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.2257035587
Short name T4
Test name
Test status
Simulation time 2031350176 ps
CPU time 1.89 seconds
Started Aug 19 04:49:37 PM PDT 24
Finished Aug 19 04:49:39 PM PDT 24
Peak memory 201108 kb
Host smart-bad01144-3a17-42d2-908f-89e9123e3c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257035587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.2257035587
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2414022078
Short name T638
Test name
Test status
Simulation time 3715002184 ps
CPU time 9.6 seconds
Started Aug 19 04:49:31 PM PDT 24
Finished Aug 19 04:49:40 PM PDT 24
Peak memory 201220 kb
Host smart-1f4e2c8a-c3bd-4df6-bfe8-73080ab9b8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414022078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
414022078
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2184203406
Short name T95
Test name
Test status
Simulation time 50630295729 ps
CPU time 140.72 seconds
Started Aug 19 04:49:26 PM PDT 24
Finished Aug 19 04:51:47 PM PDT 24
Peak memory 201252 kb
Host smart-23ffe3ed-6e32-4c1e-8be6-93a1e86720f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184203406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2184203406
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1351692210
Short name T579
Test name
Test status
Simulation time 67944957287 ps
CPU time 29.19 seconds
Started Aug 19 04:49:30 PM PDT 24
Finished Aug 19 04:49:59 PM PDT 24
Peak memory 201304 kb
Host smart-932453ac-6f7b-41f9-85ee-ea3867a78bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351692210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.1351692210
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2354175446
Short name T762
Test name
Test status
Simulation time 3256469418 ps
CPU time 1.56 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:29 PM PDT 24
Peak memory 201084 kb
Host smart-0e33405e-c73d-4317-baae-a77855d707f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354175446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.2354175446
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.896064014
Short name T137
Test name
Test status
Simulation time 4735269090 ps
CPU time 10.72 seconds
Started Aug 19 04:49:27 PM PDT 24
Finished Aug 19 04:49:38 PM PDT 24
Peak memory 201184 kb
Host smart-cf5a7251-c36e-40c5-b824-a8e64ba96430
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896064014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctr
l_edge_detect.896064014
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3737953093
Short name T409
Test name
Test status
Simulation time 2614354460 ps
CPU time 6.95 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:35 PM PDT 24
Peak memory 201136 kb
Host smart-d90d8128-c928-4a84-a4fd-1909b5b50fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737953093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.3737953093
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.209733287
Short name T689
Test name
Test status
Simulation time 2477871682 ps
CPU time 2.36 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 201104 kb
Host smart-016e2e2a-42a1-4425-a981-1aee84546324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209733287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.209733287
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.819339130
Short name T415
Test name
Test status
Simulation time 2141193445 ps
CPU time 6.35 seconds
Started Aug 19 04:49:27 PM PDT 24
Finished Aug 19 04:49:34 PM PDT 24
Peak memory 201076 kb
Host smart-9979395c-fc9d-4723-84b8-7b023bc918c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819339130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.819339130
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2152352830
Short name T616
Test name
Test status
Simulation time 2520746716 ps
CPU time 2.38 seconds
Started Aug 19 04:49:28 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 201148 kb
Host smart-de0746bf-b3b9-4288-8eea-11e94c753d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152352830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2152352830
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.1060980758
Short name T428
Test name
Test status
Simulation time 2109638553 ps
CPU time 6.09 seconds
Started Aug 19 04:49:29 PM PDT 24
Finished Aug 19 04:49:36 PM PDT 24
Peak memory 201064 kb
Host smart-fd06bdd9-98a5-4846-a0b2-5e6218d10a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060980758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1060980758
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.148393148
Short name T631
Test name
Test status
Simulation time 16207912012 ps
CPU time 12.35 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:49:50 PM PDT 24
Peak memory 201108 kb
Host smart-5ac9f611-30e0-44f3-8ab7-3fac6d810973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148393148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.148393148
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1956726518
Short name T284
Test name
Test status
Simulation time 13962609062 ps
CPU time 10.37 seconds
Started Aug 19 04:49:27 PM PDT 24
Finished Aug 19 04:49:38 PM PDT 24
Peak memory 209568 kb
Host smart-506acec6-1b07-4c5e-9813-adc6a0bbc013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956726518 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1956726518
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3922233774
Short name T763
Test name
Test status
Simulation time 6945998076 ps
CPU time 3.79 seconds
Started Aug 19 04:49:30 PM PDT 24
Finished Aug 19 04:49:34 PM PDT 24
Peak memory 201148 kb
Host smart-01b90696-25ba-4196-afa5-18977785e125
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922233774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.3922233774
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.1212525689
Short name T508
Test name
Test status
Simulation time 2059202209 ps
CPU time 1.65 seconds
Started Aug 19 04:49:41 PM PDT 24
Finished Aug 19 04:49:43 PM PDT 24
Peak memory 201132 kb
Host smart-c0195e36-ce72-427f-bc5a-613ec1b74467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212525689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.1212525689
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3749161640
Short name T93
Test name
Test status
Simulation time 3134573732 ps
CPU time 8.83 seconds
Started Aug 19 04:49:41 PM PDT 24
Finished Aug 19 04:49:50 PM PDT 24
Peak memory 201204 kb
Host smart-c4f0657f-d0bb-4048-96ff-e16dc952acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749161640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3
749161640
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.2322871415
Short name T27
Test name
Test status
Simulation time 146062528609 ps
CPU time 195.93 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:52:54 PM PDT 24
Peak memory 201212 kb
Host smart-4236d45f-793c-4539-805f-002c0a77c4d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322871415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.2322871415
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2232098831
Short name T777
Test name
Test status
Simulation time 47335756673 ps
CPU time 121.87 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:51:41 PM PDT 24
Peak memory 201288 kb
Host smart-b8ae2890-077c-41a4-b414-2dd3fb682edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232098831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2232098831
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2817584163
Short name T562
Test name
Test status
Simulation time 3456279760 ps
CPU time 9.58 seconds
Started Aug 19 04:49:44 PM PDT 24
Finished Aug 19 04:49:53 PM PDT 24
Peak memory 201144 kb
Host smart-ad5e307d-0772-4b31-aad8-c114d26ee8ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817584163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.2817584163
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3029183697
Short name T606
Test name
Test status
Simulation time 2676954567 ps
CPU time 1.35 seconds
Started Aug 19 04:49:35 PM PDT 24
Finished Aug 19 04:49:37 PM PDT 24
Peak memory 201136 kb
Host smart-fc986084-d6d7-4acf-86fc-19b3b5361f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029183697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3029183697
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.124826091
Short name T446
Test name
Test status
Simulation time 2473088844 ps
CPU time 2.16 seconds
Started Aug 19 04:49:36 PM PDT 24
Finished Aug 19 04:49:39 PM PDT 24
Peak memory 201040 kb
Host smart-159cfd6c-72fe-42da-ac0d-a5def2567892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124826091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.124826091
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2496601359
Short name T734
Test name
Test status
Simulation time 2034077073 ps
CPU time 1.94 seconds
Started Aug 19 04:49:37 PM PDT 24
Finished Aug 19 04:49:39 PM PDT 24
Peak memory 201116 kb
Host smart-d40e684f-9f05-4dde-8a71-cf50b23e4e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496601359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2496601359
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3503879982
Short name T791
Test name
Test status
Simulation time 2522469188 ps
CPU time 3.92 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:43 PM PDT 24
Peak memory 201140 kb
Host smart-64c1f09b-c443-4b25-8b55-3371ce4af40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503879982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3503879982
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.485596982
Short name T204
Test name
Test status
Simulation time 2122077165 ps
CPU time 1.95 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:41 PM PDT 24
Peak memory 201056 kb
Host smart-089f2490-1490-462f-ae58-625af67b61d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485596982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.485596982
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.2972645115
Short name T219
Test name
Test status
Simulation time 15166016482 ps
CPU time 20.31 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:49:59 PM PDT 24
Peak memory 201200 kb
Host smart-78642360-8052-4ca9-a9cc-83a0f6137d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972645115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.2972645115
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2926793290
Short name T486
Test name
Test status
Simulation time 3689038848 ps
CPU time 10.37 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:49 PM PDT 24
Peak memory 201268 kb
Host smart-777ffe7b-33ac-4aed-9558-bdc7daf904f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926793290 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2926793290
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.4157103590
Short name T113
Test name
Test status
Simulation time 4385632710 ps
CPU time 6.6 seconds
Started Aug 19 04:49:41 PM PDT 24
Finished Aug 19 04:49:48 PM PDT 24
Peak memory 201120 kb
Host smart-bbadabc7-b565-4a72-8ef0-127627bfdb76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157103590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.4157103590
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1812335975
Short name T549
Test name
Test status
Simulation time 2012515250 ps
CPU time 5.53 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:48:02 PM PDT 24
Peak memory 201120 kb
Host smart-20d293cc-9543-44bf-9056-7258b0a9cab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812335975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1812335975
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1555949195
Short name T598
Test name
Test status
Simulation time 3755099352 ps
CPU time 2.99 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 201200 kb
Host smart-aaf9188c-2441-460c-b759-ae4391498104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555949195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1555949195
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2783477493
Short name T235
Test name
Test status
Simulation time 149413276052 ps
CPU time 23.95 seconds
Started Aug 19 04:47:49 PM PDT 24
Finished Aug 19 04:48:13 PM PDT 24
Peak memory 201244 kb
Host smart-9c64c599-7b85-4dc5-9899-e1db9696a593
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783477493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2783477493
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1251002998
Short name T210
Test name
Test status
Simulation time 2399307055 ps
CPU time 3.59 seconds
Started Aug 19 04:47:49 PM PDT 24
Finished Aug 19 04:47:53 PM PDT 24
Peak memory 201172 kb
Host smart-efd264fe-182e-4d8b-afb0-cf3c9c6d834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251002998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1251002998
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2261283184
Short name T788
Test name
Test status
Simulation time 2359273041 ps
CPU time 6.31 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:47:53 PM PDT 24
Peak memory 201140 kb
Host smart-f0845180-9684-4a36-af85-d926fef2a743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261283184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2261283184
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1891163198
Short name T585
Test name
Test status
Simulation time 94806506174 ps
CPU time 38.51 seconds
Started Aug 19 04:47:48 PM PDT 24
Finished Aug 19 04:48:27 PM PDT 24
Peak memory 201352 kb
Host smart-81adab07-b0f2-4b53-b879-46cb53896c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891163198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1891163198
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.316635978
Short name T563
Test name
Test status
Simulation time 4340823825 ps
CPU time 3.5 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 201128 kb
Host smart-996ae155-0dba-4d6c-80c8-7559fb9bed3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316635978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_ec_pwr_on_rst.316635978
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2405537942
Short name T134
Test name
Test status
Simulation time 2682047421 ps
CPU time 7.28 seconds
Started Aug 19 04:47:50 PM PDT 24
Finished Aug 19 04:47:58 PM PDT 24
Peak memory 201124 kb
Host smart-5e50d474-f4cd-4b60-85a9-63ea9300b17c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405537942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.2405537942
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2634445904
Short name T499
Test name
Test status
Simulation time 2609763276 ps
CPU time 6.93 seconds
Started Aug 19 04:47:50 PM PDT 24
Finished Aug 19 04:47:57 PM PDT 24
Peak memory 201176 kb
Host smart-5ba6b167-eaa4-44ba-91a7-8e3c8417e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634445904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2634445904
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3027356610
Short name T504
Test name
Test status
Simulation time 2468677497 ps
CPU time 3.88 seconds
Started Aug 19 04:47:46 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 201048 kb
Host smart-ff74c09a-80a4-431c-89fd-888f5c18a8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027356610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3027356610
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.2864254077
Short name T571
Test name
Test status
Simulation time 2186042708 ps
CPU time 3.44 seconds
Started Aug 19 04:47:47 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 201132 kb
Host smart-34521c4b-aab1-4568-8b2e-bf9d87742dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864254077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2864254077
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.338563541
Short name T126
Test name
Test status
Simulation time 2546798163 ps
CPU time 1.72 seconds
Started Aug 19 04:47:48 PM PDT 24
Finished Aug 19 04:47:50 PM PDT 24
Peak memory 201120 kb
Host smart-07ca9dff-1661-4877-b9c3-cefdb8bab0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338563541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.338563541
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.1090900759
Short name T274
Test name
Test status
Simulation time 2113519969 ps
CPU time 5.6 seconds
Started Aug 19 04:47:46 PM PDT 24
Finished Aug 19 04:47:52 PM PDT 24
Peak memory 201020 kb
Host smart-0cdfd34e-7e39-44a8-a1be-39adb94cd8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090900759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.1090900759
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.4150642840
Short name T430
Test name
Test status
Simulation time 11635999140 ps
CPU time 8.59 seconds
Started Aug 19 04:47:48 PM PDT 24
Finished Aug 19 04:47:56 PM PDT 24
Peak memory 201136 kb
Host smart-2c6364a5-9ef3-41ad-83c2-bd51ea70f9e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150642840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.4150642840
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3987990182
Short name T290
Test name
Test status
Simulation time 5777484571 ps
CPU time 8.15 seconds
Started Aug 19 04:47:49 PM PDT 24
Finished Aug 19 04:47:57 PM PDT 24
Peak memory 201264 kb
Host smart-0de8bb05-b85d-4207-b5fe-454b8bce6133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987990182 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3987990182
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3801237585
Short name T59
Test name
Test status
Simulation time 7950297186 ps
CPU time 5.38 seconds
Started Aug 19 04:47:49 PM PDT 24
Finished Aug 19 04:47:55 PM PDT 24
Peak memory 201128 kb
Host smart-bf1d3666-3d47-4d1f-9b63-628bff31e1da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801237585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.3801237585
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.606949164
Short name T519
Test name
Test status
Simulation time 2014516204 ps
CPU time 5.9 seconds
Started Aug 19 04:49:36 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 201088 kb
Host smart-3e964b6a-f969-4f08-bc83-11104ca97e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606949164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_tes
t.606949164
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3370320617
Short name T401
Test name
Test status
Simulation time 3658506821 ps
CPU time 2.91 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:49:41 PM PDT 24
Peak memory 201228 kb
Host smart-3871384d-f175-4044-8994-c1f2eff8cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370320617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.3
370320617
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.1385029459
Short name T339
Test name
Test status
Simulation time 68118737188 ps
CPU time 158.6 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:52:17 PM PDT 24
Peak memory 201224 kb
Host smart-4198b360-3a11-4caa-812b-589a04c3c15f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385029459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.1385029459
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1209414340
Short name T336
Test name
Test status
Simulation time 39096785027 ps
CPU time 26.25 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:50:05 PM PDT 24
Peak memory 201352 kb
Host smart-6a88b94e-51eb-4845-a5e7-17bc19aaae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209414340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1209414340
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1451526527
Short name T615
Test name
Test status
Simulation time 3133406871 ps
CPU time 4.48 seconds
Started Aug 19 04:49:43 PM PDT 24
Finished Aug 19 04:49:48 PM PDT 24
Peak memory 201136 kb
Host smart-113e9e7b-3bce-4eac-a7be-a9809b23154a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451526527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.1451526527
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1555202198
Short name T135
Test name
Test status
Simulation time 5985561217 ps
CPU time 7.1 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:49:45 PM PDT 24
Peak memory 201128 kb
Host smart-a82d5a75-8de5-4533-8310-19632afd1b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555202198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1555202198
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3374808221
Short name T525
Test name
Test status
Simulation time 2615970887 ps
CPU time 4.23 seconds
Started Aug 19 04:49:41 PM PDT 24
Finished Aug 19 04:49:46 PM PDT 24
Peak memory 201096 kb
Host smart-0192380d-6408-47ed-b7d7-a1042d9f360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374808221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3374808221
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3386515633
Short name T724
Test name
Test status
Simulation time 2495051394 ps
CPU time 2.14 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:41 PM PDT 24
Peak memory 201156 kb
Host smart-717d56f5-ac65-4707-a57b-c294de80e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386515633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3386515633
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3568252079
Short name T129
Test name
Test status
Simulation time 2162508211 ps
CPU time 6.05 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:45 PM PDT 24
Peak memory 201092 kb
Host smart-c77d3a0d-9dd8-4140-9bfe-13931a8ce5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568252079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3568252079
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3594788040
Short name T626
Test name
Test status
Simulation time 2526501056 ps
CPU time 2.2 seconds
Started Aug 19 04:49:40 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 201032 kb
Host smart-77e68261-16c1-4e06-ae1d-64455e2dd64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594788040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3594788040
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.3166839671
Short name T217
Test name
Test status
Simulation time 2136160389 ps
CPU time 1.82 seconds
Started Aug 19 04:49:44 PM PDT 24
Finished Aug 19 04:49:46 PM PDT 24
Peak memory 201068 kb
Host smart-6f5ff439-21a6-4f39-99e5-67be9883ba74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166839671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.3166839671
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.633130975
Short name T187
Test name
Test status
Simulation time 116946151288 ps
CPU time 96.52 seconds
Started Aug 19 04:49:40 PM PDT 24
Finished Aug 19 04:51:17 PM PDT 24
Peak memory 201216 kb
Host smart-442d7d0c-17d5-4694-8ab8-94e8b5747734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633130975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_st
ress_all.633130975
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1458662192
Short name T258
Test name
Test status
Simulation time 17222221007 ps
CPU time 11.21 seconds
Started Aug 19 04:49:43 PM PDT 24
Finished Aug 19 04:49:54 PM PDT 24
Peak memory 211888 kb
Host smart-a4fd26d0-5dd3-4543-b707-1dcfc69833f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458662192 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1458662192
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.477224437
Short name T495
Test name
Test status
Simulation time 4479253491 ps
CPU time 5.75 seconds
Started Aug 19 04:49:40 PM PDT 24
Finished Aug 19 04:49:46 PM PDT 24
Peak memory 201172 kb
Host smart-0b200cb9-001e-41cb-9fcb-fc817cb05a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477224437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ultra_low_pwr.477224437
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.140050194
Short name T671
Test name
Test status
Simulation time 2014245955 ps
CPU time 3.22 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 201136 kb
Host smart-9299726d-989e-4fb1-9463-37be8acdc13a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140050194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.140050194
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1043236562
Short name T437
Test name
Test status
Simulation time 3573054519 ps
CPU time 2.8 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 201180 kb
Host smart-8ba7e2ad-9d91-4280-a94a-d6faf752bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043236562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.1
043236562
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.2523244437
Short name T332
Test name
Test status
Simulation time 67283856627 ps
CPU time 166.71 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:52:26 PM PDT 24
Peak memory 201148 kb
Host smart-59611ac6-9547-4c21-b5bc-271dcf6a9566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523244437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.2523244437
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.800769701
Short name T73
Test name
Test status
Simulation time 23328465553 ps
CPU time 61.39 seconds
Started Aug 19 04:49:37 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201320 kb
Host smart-7eb9d8d7-46fa-420d-8d7f-30567805ecd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800769701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_wi
th_pre_cond.800769701
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.823926447
Short name T391
Test name
Test status
Simulation time 3548484644 ps
CPU time 1.38 seconds
Started Aug 19 04:49:43 PM PDT 24
Finished Aug 19 04:49:45 PM PDT 24
Peak memory 201148 kb
Host smart-03ffe932-4907-418c-8d2b-05a64ecae26f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823926447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ec_pwr_on_rst.823926447
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2129466649
Short name T196
Test name
Test status
Simulation time 2590561044 ps
CPU time 3.99 seconds
Started Aug 19 04:49:41 PM PDT 24
Finished Aug 19 04:49:45 PM PDT 24
Peak memory 201060 kb
Host smart-4118b5a2-1f61-4f18-a3ea-eb632742d174
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129466649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.2129466649
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.675694450
Short name T680
Test name
Test status
Simulation time 2632581113 ps
CPU time 2.33 seconds
Started Aug 19 04:49:37 PM PDT 24
Finished Aug 19 04:49:40 PM PDT 24
Peak memory 201132 kb
Host smart-b72e21cc-4862-46d9-9062-dfc02bf8969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675694450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.675694450
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1720504234
Short name T299
Test name
Test status
Simulation time 2477109838 ps
CPU time 2.41 seconds
Started Aug 19 04:49:37 PM PDT 24
Finished Aug 19 04:49:40 PM PDT 24
Peak memory 201148 kb
Host smart-76902c0f-c3ee-4921-b19f-64e5e34b77d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720504234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1720504234
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2285893966
Short name T528
Test name
Test status
Simulation time 2163310202 ps
CPU time 2.04 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:49:41 PM PDT 24
Peak memory 201100 kb
Host smart-21499cfb-fc95-43f3-9773-63e90653ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285893966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2285893966
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.3955702505
Short name T431
Test name
Test status
Simulation time 2534296486 ps
CPU time 2.31 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 201112 kb
Host smart-081e42bc-5442-4116-8bf2-3eb1b12d3d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955702505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3955702505
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.1254237428
Short name T462
Test name
Test status
Simulation time 2125868703 ps
CPU time 2.04 seconds
Started Aug 19 04:49:41 PM PDT 24
Finished Aug 19 04:49:44 PM PDT 24
Peak memory 201024 kb
Host smart-d0b4110c-07fc-4512-a2a5-d58c2174a657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254237428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.1254237428
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.318037469
Short name T215
Test name
Test status
Simulation time 8887181928 ps
CPU time 22.43 seconds
Started Aug 19 04:49:38 PM PDT 24
Finished Aug 19 04:50:00 PM PDT 24
Peak memory 201120 kb
Host smart-5e69ef53-6c40-43ed-a60e-8a11a4649fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318037469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_st
ress_all.318037469
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3876500365
Short name T278
Test name
Test status
Simulation time 9480955113 ps
CPU time 12.66 seconds
Started Aug 19 04:49:40 PM PDT 24
Finished Aug 19 04:49:53 PM PDT 24
Peak memory 209640 kb
Host smart-565e255e-3bf7-4736-ad53-9e950e8fdad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876500365 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.3876500365
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.4093574895
Short name T79
Test name
Test status
Simulation time 7372539031 ps
CPU time 7.15 seconds
Started Aug 19 04:49:43 PM PDT 24
Finished Aug 19 04:49:50 PM PDT 24
Peak memory 201172 kb
Host smart-0d83ff70-901f-4270-b780-87646c481692
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093574895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.4093574895
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.349162146
Short name T613
Test name
Test status
Simulation time 2033880665 ps
CPU time 1.98 seconds
Started Aug 19 04:49:55 PM PDT 24
Finished Aug 19 04:49:57 PM PDT 24
Peak memory 201092 kb
Host smart-6e2607c5-5a38-4edf-b51e-c81198d2f010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349162146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.349162146
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2927342295
Short name T40
Test name
Test status
Simulation time 3227294780 ps
CPU time 3.02 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:49:51 PM PDT 24
Peak memory 201244 kb
Host smart-960534f2-4463-4adc-a097-2120e063844b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927342295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
927342295
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1478393099
Short name T169
Test name
Test status
Simulation time 47106836041 ps
CPU time 124.25 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:51:52 PM PDT 24
Peak memory 201244 kb
Host smart-103f1694-f596-4e7d-9345-d3e147461d15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478393099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.1478393099
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.728098392
Short name T346
Test name
Test status
Simulation time 59746392497 ps
CPU time 161.13 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:52:29 PM PDT 24
Peak memory 201388 kb
Host smart-3bbfddea-b322-4314-9a7e-84ea8aa1590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728098392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.728098392
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2577425995
Short name T461
Test name
Test status
Simulation time 4166179777 ps
CPU time 3.22 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201128 kb
Host smart-0ed90977-4dfc-4f1c-a270-e9111dcdd99b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577425995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2577425995
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.3836849575
Short name T181
Test name
Test status
Simulation time 2773207467 ps
CPU time 2.32 seconds
Started Aug 19 04:49:54 PM PDT 24
Finished Aug 19 04:49:57 PM PDT 24
Peak memory 201148 kb
Host smart-8df36541-e047-4086-9635-b609c101904e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836849575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.3836849575
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3381814280
Short name T130
Test name
Test status
Simulation time 2614260493 ps
CPU time 7.19 seconds
Started Aug 19 04:49:47 PM PDT 24
Finished Aug 19 04:49:55 PM PDT 24
Peak memory 201152 kb
Host smart-674f6eb7-da60-44c6-88d1-8e46e2f4cb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381814280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3381814280
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3430611046
Short name T717
Test name
Test status
Simulation time 2448367912 ps
CPU time 6.84 seconds
Started Aug 19 04:49:36 PM PDT 24
Finished Aug 19 04:49:43 PM PDT 24
Peak memory 201124 kb
Host smart-e836e6bc-a4fd-4941-be34-b6a19fc86163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430611046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3430611046
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.2674026937
Short name T466
Test name
Test status
Simulation time 2265429858 ps
CPU time 1.4 seconds
Started Aug 19 04:49:39 PM PDT 24
Finished Aug 19 04:49:40 PM PDT 24
Peak memory 201144 kb
Host smart-79c788b3-1cd6-4080-aae9-8c898bf94cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674026937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.2674026937
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1147265438
Short name T503
Test name
Test status
Simulation time 2529307089 ps
CPU time 2.2 seconds
Started Aug 19 04:49:47 PM PDT 24
Finished Aug 19 04:49:49 PM PDT 24
Peak memory 201152 kb
Host smart-987079ce-1d1b-406b-82d4-378ca3fdb7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147265438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1147265438
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.3691605300
Short name T595
Test name
Test status
Simulation time 2135950046 ps
CPU time 1.8 seconds
Started Aug 19 04:49:40 PM PDT 24
Finished Aug 19 04:49:42 PM PDT 24
Peak memory 200952 kb
Host smart-cc24829f-86c2-432f-ab8c-d256cd201234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691605300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3691605300
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.1398708534
Short name T78
Test name
Test status
Simulation time 19204696424 ps
CPU time 19.52 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 201200 kb
Host smart-1edbb5b9-1710-4290-acc7-a5e7d5553601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398708534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.1398708534
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3248355276
Short name T412
Test name
Test status
Simulation time 7414902287 ps
CPU time 5.73 seconds
Started Aug 19 04:49:52 PM PDT 24
Finished Aug 19 04:49:58 PM PDT 24
Peak memory 201244 kb
Host smart-f7119559-8776-4da3-b169-61ab9ef36452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248355276 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3248355276
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2182447997
Short name T780
Test name
Test status
Simulation time 13533116712 ps
CPU time 2.48 seconds
Started Aug 19 04:49:53 PM PDT 24
Finished Aug 19 04:49:56 PM PDT 24
Peak memory 201144 kb
Host smart-63eace49-0d71-4600-b81f-da557a65e395
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182447997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2182447997
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.4230249252
Short name T476
Test name
Test status
Simulation time 2018091360 ps
CPU time 3.32 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201136 kb
Host smart-845f68b2-6160-43ef-aed4-b69dcc574b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230249252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.4230249252
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1919894485
Short name T618
Test name
Test status
Simulation time 3699925108 ps
CPU time 1.91 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:49:50 PM PDT 24
Peak memory 201256 kb
Host smart-ea96658b-15eb-4c58-b91c-f0c06a644403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919894485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1
919894485
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.4114025770
Short name T340
Test name
Test status
Simulation time 128432842734 ps
CPU time 352.35 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:55:41 PM PDT 24
Peak memory 201252 kb
Host smart-7bb67ec1-9bb1-49e8-93fc-10d57f656962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114025770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.4114025770
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2375082852
Short name T423
Test name
Test status
Simulation time 3361869096 ps
CPU time 3.13 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201132 kb
Host smart-d26c3c49-0951-4e65-9870-3177875b74f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375082852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2375082852
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.747225111
Short name T515
Test name
Test status
Simulation time 3101277947 ps
CPU time 4.62 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:54 PM PDT 24
Peak memory 201128 kb
Host smart-561dd567-4fc1-42e7-988f-c271bb2a0b10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747225111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctr
l_edge_detect.747225111
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.141464715
Short name T622
Test name
Test status
Simulation time 2631440277 ps
CPU time 2.46 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:51 PM PDT 24
Peak memory 201140 kb
Host smart-046807be-ea73-45ec-b605-26bdd21c1b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141464715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.141464715
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2219860105
Short name T589
Test name
Test status
Simulation time 2481927378 ps
CPU time 2.17 seconds
Started Aug 19 04:49:56 PM PDT 24
Finished Aug 19 04:49:58 PM PDT 24
Peak memory 201140 kb
Host smart-5384b547-ccef-4ce9-aee0-8e7b7ab374c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219860105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2219860105
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.213929888
Short name T212
Test name
Test status
Simulation time 2130549424 ps
CPU time 1.13 seconds
Started Aug 19 04:49:51 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201072 kb
Host smart-c5334978-40a3-4a00-9376-90fb73383ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213929888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.213929888
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.910956837
Short name T421
Test name
Test status
Simulation time 2519234600 ps
CPU time 2.43 seconds
Started Aug 19 04:49:52 PM PDT 24
Finished Aug 19 04:49:54 PM PDT 24
Peak memory 201128 kb
Host smart-1e131bef-3137-4d5d-95d5-5b4411baba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910956837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.910956837
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.3375218631
Short name T614
Test name
Test status
Simulation time 2125346848 ps
CPU time 2.03 seconds
Started Aug 19 04:49:54 PM PDT 24
Finished Aug 19 04:49:56 PM PDT 24
Peak memory 201028 kb
Host smart-65ddadc0-d637-4205-aefb-3f329ab0ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375218631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.3375218631
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.3777677988
Short name T33
Test name
Test status
Simulation time 15583616667 ps
CPU time 34.19 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:50:24 PM PDT 24
Peak memory 201084 kb
Host smart-30e22003-fd27-4e0e-ac67-25423eb21e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777677988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.3777677988
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3094930478
Short name T311
Test name
Test status
Simulation time 5766441888 ps
CPU time 16.11 seconds
Started Aug 19 04:49:54 PM PDT 24
Finished Aug 19 04:50:10 PM PDT 24
Peak memory 217764 kb
Host smart-ea1e740b-f7f1-451f-83d9-70644f0d50ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094930478 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3094930478
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.2506038288
Short name T456
Test name
Test status
Simulation time 2030514436 ps
CPU time 2.09 seconds
Started Aug 19 04:49:55 PM PDT 24
Finished Aug 19 04:49:58 PM PDT 24
Peak memory 201072 kb
Host smart-dd1c68b9-cf81-419d-95a6-74f68906a2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506038288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.2506038288
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3154280139
Short name T764
Test name
Test status
Simulation time 3191287702 ps
CPU time 9.19 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:58 PM PDT 24
Peak memory 201224 kb
Host smart-a4200675-3a9b-4715-a101-c0e7a775bfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154280139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3
154280139
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.92369296
Short name T233
Test name
Test status
Simulation time 71513358722 ps
CPU time 56.2 seconds
Started Aug 19 04:49:51 PM PDT 24
Finished Aug 19 04:50:47 PM PDT 24
Peak memory 201324 kb
Host smart-18e381b7-aa23-453a-a628-26c1e4ddb7be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92369296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctr
l_combo_detect.92369296
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.4258130112
Short name T378
Test name
Test status
Simulation time 124768959563 ps
CPU time 75.35 seconds
Started Aug 19 04:49:54 PM PDT 24
Finished Aug 19 04:51:10 PM PDT 24
Peak memory 201368 kb
Host smart-4ef58926-151a-444a-804c-9bbee12f21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258130112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.4258130112
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2131037104
Short name T414
Test name
Test status
Simulation time 5703082021 ps
CPU time 2.3 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:51 PM PDT 24
Peak memory 201108 kb
Host smart-43a8dde3-78cb-4074-9120-449a54f15bc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131037104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2131037104
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1982337859
Short name T177
Test name
Test status
Simulation time 90697614960 ps
CPU time 14.66 seconds
Started Aug 19 04:49:57 PM PDT 24
Finished Aug 19 04:50:12 PM PDT 24
Peak memory 201120 kb
Host smart-e5e18874-c61a-4b34-9662-30087970efc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982337859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1982337859
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1913231687
Short name T730
Test name
Test status
Simulation time 2785281660 ps
CPU time 1.01 seconds
Started Aug 19 04:49:47 PM PDT 24
Finished Aug 19 04:49:48 PM PDT 24
Peak memory 201136 kb
Host smart-b7ec6d69-58d7-4978-bad4-7d6de2166b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913231687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1913231687
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.522081375
Short name T682
Test name
Test status
Simulation time 2485442868 ps
CPU time 1.33 seconds
Started Aug 19 04:49:55 PM PDT 24
Finished Aug 19 04:49:57 PM PDT 24
Peak memory 201144 kb
Host smart-e5c0813c-3dcb-4141-86b8-33903f2aaa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522081375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.522081375
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.4136176475
Short name T128
Test name
Test status
Simulation time 2052174492 ps
CPU time 3.36 seconds
Started Aug 19 04:49:56 PM PDT 24
Finished Aug 19 04:49:59 PM PDT 24
Peak memory 201064 kb
Host smart-cedb6305-cb64-4c7f-9c91-3976a710af8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136176475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.4136176475
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.4264860393
Short name T188
Test name
Test status
Simulation time 2529331834 ps
CPU time 1.99 seconds
Started Aug 19 04:49:52 PM PDT 24
Finished Aug 19 04:49:54 PM PDT 24
Peak memory 201152 kb
Host smart-c1332d8c-8bd3-4280-afd8-e258178be352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264860393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.4264860393
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.2591272403
Short name T580
Test name
Test status
Simulation time 2109042560 ps
CPU time 5.71 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:54 PM PDT 24
Peak memory 201068 kb
Host smart-bc6e3020-8ba9-4db5-92cf-ac1b2ca43000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591272403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2591272403
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2379382098
Short name T692
Test name
Test status
Simulation time 13886783127 ps
CPU time 10.18 seconds
Started Aug 19 04:49:52 PM PDT 24
Finished Aug 19 04:50:02 PM PDT 24
Peak memory 201120 kb
Host smart-a98219c2-dbca-45db-9d7c-6a4e2a8bd619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379382098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2379382098
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2960591970
Short name T660
Test name
Test status
Simulation time 4016049868 ps
CPU time 6.88 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:56 PM PDT 24
Peak memory 201176 kb
Host smart-4a5899e0-83cf-4876-8a74-9e35738da5e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960591970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2960591970
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3150966845
Short name T512
Test name
Test status
Simulation time 2024836874 ps
CPU time 3.04 seconds
Started Aug 19 04:50:07 PM PDT 24
Finished Aug 19 04:50:10 PM PDT 24
Peak memory 201140 kb
Host smart-b69c8e93-5f3a-4418-a148-0da7d70d1e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150966845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3150966845
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1533303337
Short name T513
Test name
Test status
Simulation time 73642840775 ps
CPU time 183.01 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:52:51 PM PDT 24
Peak memory 201240 kb
Host smart-2703549e-f2ad-46aa-9b41-e2f81fa98c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533303337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1
533303337
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2944302028
Short name T612
Test name
Test status
Simulation time 26332714152 ps
CPU time 69.84 seconds
Started Aug 19 04:49:57 PM PDT 24
Finished Aug 19 04:51:07 PM PDT 24
Peak memory 201360 kb
Host smart-e6666122-c4d1-4324-8770-360376d5c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944302028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.2944302028
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.808570269
Short name T636
Test name
Test status
Simulation time 4358258686 ps
CPU time 11.1 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:49:59 PM PDT 24
Peak memory 201104 kb
Host smart-091d760a-b61e-4b8e-9dae-fb3dda0b27d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808570269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ec_pwr_on_rst.808570269
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.3755618370
Short name T688
Test name
Test status
Simulation time 2492418570 ps
CPU time 2.14 seconds
Started Aug 19 04:49:55 PM PDT 24
Finished Aug 19 04:49:57 PM PDT 24
Peak memory 201076 kb
Host smart-38d584e4-03b6-4862-b793-0f5eb27ab877
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755618370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.3755618370
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2446432708
Short name T681
Test name
Test status
Simulation time 2624739805 ps
CPU time 2.53 seconds
Started Aug 19 04:49:49 PM PDT 24
Finished Aug 19 04:49:51 PM PDT 24
Peak memory 201160 kb
Host smart-4b5e11f6-1422-496a-a8eb-9b599fb1aabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446432708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2446432708
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.4105891190
Short name T478
Test name
Test status
Simulation time 2462400099 ps
CPU time 7.26 seconds
Started Aug 19 04:49:55 PM PDT 24
Finished Aug 19 04:50:03 PM PDT 24
Peak memory 201072 kb
Host smart-4495e8ea-78e9-4c97-8b7e-375c2e1c3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105891190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.4105891190
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3490928428
Short name T394
Test name
Test status
Simulation time 2199103651 ps
CPU time 3.48 seconds
Started Aug 19 04:49:48 PM PDT 24
Finished Aug 19 04:49:52 PM PDT 24
Peak memory 201092 kb
Host smart-fc1cd95c-0d3d-457b-b4d3-4ca44730617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490928428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3490928428
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3000735650
Short name T382
Test name
Test status
Simulation time 2529486295 ps
CPU time 2.41 seconds
Started Aug 19 04:49:56 PM PDT 24
Finished Aug 19 04:49:58 PM PDT 24
Peak memory 201136 kb
Host smart-cde3755f-c7c1-494c-b4f7-c7dab6c08358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000735650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.3000735650
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.520570760
Short name T464
Test name
Test status
Simulation time 2111721859 ps
CPU time 5.6 seconds
Started Aug 19 04:49:53 PM PDT 24
Finished Aug 19 04:49:59 PM PDT 24
Peak memory 201064 kb
Host smart-ee78b41b-6868-47f0-8465-d3e94dfaae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520570760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.520570760
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.3882818409
Short name T296
Test name
Test status
Simulation time 15649438434 ps
CPU time 7.3 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 201160 kb
Host smart-cd9d426b-16ce-49bf-a980-99c6db8d5b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882818409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.3882818409
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4005863888
Short name T118
Test name
Test status
Simulation time 17099458507 ps
CPU time 5.87 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:04 PM PDT 24
Peak memory 209628 kb
Host smart-30a1e8b3-6025-4cb5-b4c3-643c39f657c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005863888 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.4005863888
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.879886850
Short name T751
Test name
Test status
Simulation time 8098717978 ps
CPU time 7.65 seconds
Started Aug 19 04:49:55 PM PDT 24
Finished Aug 19 04:50:02 PM PDT 24
Peak memory 201128 kb
Host smart-272d2037-e548-4d70-b654-4598197f1dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879886850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ultra_low_pwr.879886850
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.2662237629
Short name T197
Test name
Test status
Simulation time 2103926630 ps
CPU time 0.87 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:50:03 PM PDT 24
Peak memory 201140 kb
Host smart-5273cea0-5f9c-4ce3-9e4e-1fe727fbf0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662237629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.2662237629
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.392419597
Short name T694
Test name
Test status
Simulation time 3588931068 ps
CPU time 5.46 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:03 PM PDT 24
Peak memory 201216 kb
Host smart-d9d17bc4-cd3c-43c7-bdbc-96a4d2fea2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392419597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.392419597
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3542239008
Short name T243
Test name
Test status
Simulation time 38753630070 ps
CPU time 25.74 seconds
Started Aug 19 04:49:59 PM PDT 24
Finished Aug 19 04:50:25 PM PDT 24
Peak memory 201308 kb
Host smart-ad507fad-a15a-4b55-a54f-00e24d677839
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542239008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.3542239008
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3306018544
Short name T569
Test name
Test status
Simulation time 42617155478 ps
CPU time 52.77 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:50:53 PM PDT 24
Peak memory 201360 kb
Host smart-c79b9e10-a5f9-43dd-8de0-e945c5e71419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306018544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.3306018544
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.4287453079
Short name T275
Test name
Test status
Simulation time 3999520533 ps
CPU time 8.89 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:50:11 PM PDT 24
Peak memory 201144 kb
Host smart-59005f1a-b009-4386-b129-d27364855a56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287453079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.4287453079
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1307905480
Short name T154
Test name
Test status
Simulation time 6579427437 ps
CPU time 4.54 seconds
Started Aug 19 04:50:05 PM PDT 24
Finished Aug 19 04:50:10 PM PDT 24
Peak memory 201112 kb
Host smart-74ca8c0d-37cb-4e91-907a-d732a697db39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307905480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1307905480
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4072897005
Short name T707
Test name
Test status
Simulation time 2630568065 ps
CPU time 2.23 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:01 PM PDT 24
Peak memory 201128 kb
Host smart-74048480-74eb-43ad-a106-e068209b8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072897005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.4072897005
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3720797844
Short name T221
Test name
Test status
Simulation time 2462962638 ps
CPU time 7.11 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 201132 kb
Host smart-334099b3-1fd8-4b48-9b24-5b1e24970b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720797844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3720797844
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2214847117
Short name T121
Test name
Test status
Simulation time 2170902781 ps
CPU time 1.77 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:50:03 PM PDT 24
Peak memory 201156 kb
Host smart-ec28cd33-a79d-4381-8195-26fbb8aaf5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214847117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2214847117
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2948748818
Short name T640
Test name
Test status
Simulation time 2514654352 ps
CPU time 4.13 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:03 PM PDT 24
Peak memory 201152 kb
Host smart-cc47f761-6925-4f19-8f4f-c43e543efd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948748818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2948748818
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.2243235372
Short name T395
Test name
Test status
Simulation time 2115078511 ps
CPU time 6.61 seconds
Started Aug 19 04:49:59 PM PDT 24
Finished Aug 19 04:50:06 PM PDT 24
Peak memory 201068 kb
Host smart-38434cf0-b04f-4749-bf4a-9af9366dc2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243235372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2243235372
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.2144910585
Short name T677
Test name
Test status
Simulation time 13483880256 ps
CPU time 9.65 seconds
Started Aug 19 04:50:06 PM PDT 24
Finished Aug 19 04:50:16 PM PDT 24
Peak memory 201152 kb
Host smart-e35980cf-a764-4df9-86fa-cd4897e99cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144910585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.2144910585
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2096322677
Short name T125
Test name
Test status
Simulation time 4384932688 ps
CPU time 7.4 seconds
Started Aug 19 04:50:06 PM PDT 24
Finished Aug 19 04:50:14 PM PDT 24
Peak memory 201108 kb
Host smart-4b65e1ae-47d8-4a28-a811-353d60d7f5f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096322677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2096322677
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.2491569061
Short name T769
Test name
Test status
Simulation time 2043451882 ps
CPU time 1.29 seconds
Started Aug 19 04:50:07 PM PDT 24
Finished Aug 19 04:50:09 PM PDT 24
Peak memory 201140 kb
Host smart-3b1a999d-6923-4c83-9601-29d46650bfa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491569061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.2491569061
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2098218835
Short name T453
Test name
Test status
Simulation time 329498179127 ps
CPU time 200.73 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:53:22 PM PDT 24
Peak memory 201208 kb
Host smart-02ce1654-d91e-4cce-ab8a-96d8cff5c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098218835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
098218835
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.754486207
Short name T186
Test name
Test status
Simulation time 64870613412 ps
CPU time 32.37 seconds
Started Aug 19 04:50:07 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201308 kb
Host smart-88102ad6-35c1-4413-ba00-d73adc6d14a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754486207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_combo_detect.754486207
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2998339133
Short name T173
Test name
Test status
Simulation time 2483140855 ps
CPU time 1.39 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:00 PM PDT 24
Peak memory 201132 kb
Host smart-36e2d226-795d-45e1-ac15-bd913b4e91bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998339133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2998339133
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1478246699
Short name T3
Test name
Test status
Simulation time 6160883950 ps
CPU time 1.66 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:00 PM PDT 24
Peak memory 201144 kb
Host smart-273881a1-84b6-4ebd-a854-602240fd9a13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478246699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.1478246699
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.468477306
Short name T642
Test name
Test status
Simulation time 2609661656 ps
CPU time 7.51 seconds
Started Aug 19 04:49:59 PM PDT 24
Finished Aug 19 04:50:07 PM PDT 24
Peak memory 201120 kb
Host smart-cf1878d8-87f9-43d7-83b7-314b94a3c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468477306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.468477306
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.14088697
Short name T458
Test name
Test status
Simulation time 2534829946 ps
CPU time 1.29 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:50:04 PM PDT 24
Peak memory 201148 kb
Host smart-2b7668a3-d0c4-44f9-a3b7-301b72f8a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14088697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.14088697
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3698161112
Short name T407
Test name
Test status
Simulation time 2124681710 ps
CPU time 5.98 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:04 PM PDT 24
Peak memory 201076 kb
Host smart-b69cd5f5-9e46-424a-81c8-29820ec704b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698161112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3698161112
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2324000608
Short name T473
Test name
Test status
Simulation time 2510594887 ps
CPU time 7.26 seconds
Started Aug 19 04:50:06 PM PDT 24
Finished Aug 19 04:50:13 PM PDT 24
Peak memory 201140 kb
Host smart-4c4bb4da-0461-4024-984e-8e334a13880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324000608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2324000608
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.2794894135
Short name T714
Test name
Test status
Simulation time 2110217745 ps
CPU time 6.11 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 201072 kb
Host smart-507a41f9-6816-4e0b-8645-90110760f308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794894135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.2794894135
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.1651397088
Short name T381
Test name
Test status
Simulation time 14221005928 ps
CPU time 10.06 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:50:12 PM PDT 24
Peak memory 201292 kb
Host smart-3532e61f-fcf5-4601-a730-2a36b424d251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651397088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.1651397088
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1692095662
Short name T279
Test name
Test status
Simulation time 3579802727 ps
CPU time 10.56 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:50:13 PM PDT 24
Peak memory 201272 kb
Host smart-ee8b9245-539b-48d3-8c57-de336b90c73a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692095662 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1692095662
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.22110366
Short name T753
Test name
Test status
Simulation time 3959262091 ps
CPU time 2.26 seconds
Started Aug 19 04:50:03 PM PDT 24
Finished Aug 19 04:50:05 PM PDT 24
Peak memory 201156 kb
Host smart-2ea26fc7-2be2-4b98-9eff-54e45744d4a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22110366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_ultra_low_pwr.22110366
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.2254857191
Short name T686
Test name
Test status
Simulation time 2012849424 ps
CPU time 6.06 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:50:05 PM PDT 24
Peak memory 201148 kb
Host smart-757b6efa-b801-4f11-8b20-826ba91f3e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254857191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.2254857191
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2830278929
Short name T487
Test name
Test status
Simulation time 3383799237 ps
CPU time 5.49 seconds
Started Aug 19 04:49:59 PM PDT 24
Finished Aug 19 04:50:05 PM PDT 24
Peak memory 201208 kb
Host smart-5e7d145e-fefd-46a9-8cb7-91d7c456acb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830278929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2
830278929
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2395768075
Short name T107
Test name
Test status
Simulation time 145340793437 ps
CPU time 375.37 seconds
Started Aug 19 04:49:58 PM PDT 24
Finished Aug 19 04:56:14 PM PDT 24
Peak memory 201280 kb
Host smart-296ee5f2-dd84-4132-b273-3db5048de3ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395768075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2395768075
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.723095798
Short name T641
Test name
Test status
Simulation time 162945210168 ps
CPU time 331.09 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:55:33 PM PDT 24
Peak memory 201272 kb
Host smart-383e5172-b22a-460b-9ffc-fd44b016f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723095798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_wi
th_pre_cond.723095798
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.316700585
Short name T444
Test name
Test status
Simulation time 4694904040 ps
CPU time 6.74 seconds
Started Aug 19 04:50:02 PM PDT 24
Finished Aug 19 04:50:09 PM PDT 24
Peak memory 201140 kb
Host smart-c1b7ddc7-acb4-459c-b630-ee8a165b22c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316700585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.316700585
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3223155128
Short name T153
Test name
Test status
Simulation time 2614735039 ps
CPU time 7.2 seconds
Started Aug 19 04:50:00 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 201164 kb
Host smart-72ca354d-668d-48d8-a230-ad123c584847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223155128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3223155128
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1330012413
Short name T21
Test name
Test status
Simulation time 2496034731 ps
CPU time 1.42 seconds
Started Aug 19 04:50:05 PM PDT 24
Finished Aug 19 04:50:06 PM PDT 24
Peak memory 201140 kb
Host smart-7f7d3158-eca3-471e-bd00-b6d43d7d3ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330012413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1330012413
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1873289213
Short name T510
Test name
Test status
Simulation time 2197963373 ps
CPU time 3.51 seconds
Started Aug 19 04:50:01 PM PDT 24
Finished Aug 19 04:50:04 PM PDT 24
Peak memory 201152 kb
Host smart-ed26134f-6c42-4c08-8399-4d9827516a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873289213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1873289213
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.575315532
Short name T655
Test name
Test status
Simulation time 2514284367 ps
CPU time 4.77 seconds
Started Aug 19 04:49:59 PM PDT 24
Finished Aug 19 04:50:04 PM PDT 24
Peak memory 201132 kb
Host smart-aebfa245-7382-4c8a-a64d-b82ec032a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575315532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.575315532
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1751646512
Short name T398
Test name
Test status
Simulation time 2135512789 ps
CPU time 1.51 seconds
Started Aug 19 04:50:05 PM PDT 24
Finished Aug 19 04:50:06 PM PDT 24
Peak memory 201060 kb
Host smart-7a3ff0d2-a445-4d6d-860b-345d4266b7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751646512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1751646512
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1334866886
Short name T161
Test name
Test status
Simulation time 256473212199 ps
CPU time 681.32 seconds
Started Aug 19 04:50:00 PM PDT 24
Finished Aug 19 05:01:22 PM PDT 24
Peak memory 201276 kb
Host smart-4bc5f274-f50d-4e81-9dc1-587e10691be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334866886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1334866886
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1773461935
Short name T308
Test name
Test status
Simulation time 6976495860 ps
CPU time 10.11 seconds
Started Aug 19 04:50:00 PM PDT 24
Finished Aug 19 04:50:10 PM PDT 24
Peak memory 201296 kb
Host smart-cfadc382-4cfd-4a4b-b50b-38d03edc58f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773461935 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1773461935
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.498879744
Short name T555
Test name
Test status
Simulation time 9714851409 ps
CPU time 8.2 seconds
Started Aug 19 04:50:05 PM PDT 24
Finished Aug 19 04:50:14 PM PDT 24
Peak memory 201148 kb
Host smart-934efa8d-9c97-42f4-8363-99892bd05eb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498879744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.498879744
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.2526384926
Short name T475
Test name
Test status
Simulation time 2013814470 ps
CPU time 5.8 seconds
Started Aug 19 04:50:09 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 201128 kb
Host smart-f2e9d76b-71ce-4590-9723-7980249d5567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526384926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.2526384926
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3058292600
Short name T424
Test name
Test status
Simulation time 2764085918 ps
CPU time 3.2 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 201244 kb
Host smart-ba2d9549-a337-4904-b74b-798459207e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058292600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
058292600
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1319964233
Short name T583
Test name
Test status
Simulation time 32840399303 ps
CPU time 80.48 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:51:30 PM PDT 24
Peak memory 201324 kb
Host smart-3d7d9bea-43b8-4485-b3a6-a1c8e4d6679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319964233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1319964233
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3454761824
Short name T483
Test name
Test status
Simulation time 3687327336 ps
CPU time 3.1 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:14 PM PDT 24
Peak memory 201120 kb
Host smart-fd7ca963-2de2-4384-9d97-2605ce321607
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454761824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3454761824
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.4152727072
Short name T685
Test name
Test status
Simulation time 3307809005 ps
CPU time 1.38 seconds
Started Aug 19 04:50:09 PM PDT 24
Finished Aug 19 04:50:11 PM PDT 24
Peak memory 201072 kb
Host smart-7e504301-2c30-49d3-aa06-b425699b22e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152727072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.4152727072
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1526275931
Short name T601
Test name
Test status
Simulation time 2675397194 ps
CPU time 1.36 seconds
Started Aug 19 04:50:14 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 201136 kb
Host smart-f6d13ea3-a378-4588-afed-784dd207733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526275931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1526275931
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2876079447
Short name T297
Test name
Test status
Simulation time 2467280114 ps
CPU time 7.38 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:17 PM PDT 24
Peak memory 201136 kb
Host smart-1e47cd76-2a90-499d-89ea-ef46dcb85c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876079447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2876079447
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.4229902809
Short name T479
Test name
Test status
Simulation time 2242018052 ps
CPU time 6.42 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:16 PM PDT 24
Peak memory 201140 kb
Host smart-b1b6626b-efd6-42ae-83f0-9ccc3d4fcc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229902809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.4229902809
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.288164588
Short name T450
Test name
Test status
Simulation time 2533725186 ps
CPU time 2.31 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:13 PM PDT 24
Peak memory 201140 kb
Host smart-6c167804-9a4e-450a-9cf1-dcd83a8fb967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288164588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.288164588
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.195927571
Short name T433
Test name
Test status
Simulation time 2136311251 ps
CPU time 2 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:50:13 PM PDT 24
Peak memory 201068 kb
Host smart-285d46b6-419a-451c-ac07-54b6ccfc68f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195927571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.195927571
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3440830771
Short name T765
Test name
Test status
Simulation time 5739907163 ps
CPU time 11.78 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:50:22 PM PDT 24
Peak memory 201272 kb
Host smart-d24d5485-c5ed-4255-b47e-ecba6ec0443d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440830771 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3440830771
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.679177925
Short name T576
Test name
Test status
Simulation time 4965690632 ps
CPU time 2.31 seconds
Started Aug 19 04:50:09 PM PDT 24
Finished Aug 19 04:50:12 PM PDT 24
Peak memory 201176 kb
Host smart-cd194ea6-a5ff-4ed3-86e3-69e165ac7106
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679177925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_ultra_low_pwr.679177925
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.1974900625
Short name T594
Test name
Test status
Simulation time 2030305984 ps
CPU time 2.03 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:47:58 PM PDT 24
Peak memory 201140 kb
Host smart-60e67786-8fdb-4c11-8574-678fc35e7564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974900625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.1974900625
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3716199623
Short name T211
Test name
Test status
Simulation time 3292860964 ps
CPU time 5.18 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:48:02 PM PDT 24
Peak memory 201232 kb
Host smart-8865a795-d023-491f-9d71-9f84a7fcad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716199623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3716199623
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1540479131
Short name T246
Test name
Test status
Simulation time 153309634754 ps
CPU time 24.37 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201312 kb
Host smart-217d3fb5-7337-4783-a6ba-c331bb0e14f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540479131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1540479131
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3060951220
Short name T109
Test name
Test status
Simulation time 2430454679 ps
CPU time 2.08 seconds
Started Aug 19 04:47:58 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201024 kb
Host smart-6c845976-bc88-4c83-a65f-13c3bf6d3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060951220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.3060951220
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3777294995
Short name T481
Test name
Test status
Simulation time 2273803144 ps
CPU time 6.67 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201144 kb
Host smart-2bfebd07-6645-4186-ab89-7faaf12d8450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777294995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3777294995
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2687253923
Short name T355
Test name
Test status
Simulation time 125914681037 ps
CPU time 334.41 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:53:29 PM PDT 24
Peak memory 201352 kb
Host smart-e703b957-1d4a-4c1a-9205-2033f1223f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687253923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.2687253923
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1209515995
Short name T778
Test name
Test status
Simulation time 18650444770 ps
CPU time 7.11 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201108 kb
Host smart-4b3b7028-a56d-4457-8ce6-c57174352745
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209515995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1209515995
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2236183340
Short name T756
Test name
Test status
Simulation time 3160193366 ps
CPU time 8.46 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:48:03 PM PDT 24
Peak memory 201148 kb
Host smart-7b223794-ea03-4428-80c3-7d037a44cd83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236183340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2236183340
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.377005241
Short name T470
Test name
Test status
Simulation time 2627607812 ps
CPU time 2.25 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:47:59 PM PDT 24
Peak memory 201156 kb
Host smart-eef36ddd-05f9-462f-aa0e-0a49ded49d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377005241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.377005241
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3203607035
Short name T578
Test name
Test status
Simulation time 2452154727 ps
CPU time 7.06 seconds
Started Aug 19 04:47:57 PM PDT 24
Finished Aug 19 04:48:05 PM PDT 24
Peak memory 201140 kb
Host smart-fce543f3-f991-442e-b912-1a71bd5017a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203607035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3203607035
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.654834648
Short name T491
Test name
Test status
Simulation time 2207015307 ps
CPU time 1.96 seconds
Started Aug 19 04:48:00 PM PDT 24
Finished Aug 19 04:48:02 PM PDT 24
Peak memory 201144 kb
Host smart-7b8302c4-4e5f-421f-82d2-930e1c33cb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654834648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.654834648
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3597315588
Short name T609
Test name
Test status
Simulation time 2513016901 ps
CPU time 7.35 seconds
Started Aug 19 04:47:59 PM PDT 24
Finished Aug 19 04:48:06 PM PDT 24
Peak memory 201168 kb
Host smart-3cd8f101-f456-47de-b48f-77199c43e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597315588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3597315588
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1996975765
Short name T268
Test name
Test status
Simulation time 22010486435 ps
CPU time 55.14 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:48:49 PM PDT 24
Peak memory 220932 kb
Host smart-29a21f4f-68c0-4d5a-9baf-c61b7c1ab88b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996975765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1996975765
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2342405547
Short name T406
Test name
Test status
Simulation time 2137706628 ps
CPU time 1.46 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:47:57 PM PDT 24
Peak memory 201072 kb
Host smart-e03f5859-b03a-46e1-9da7-a31324e3c605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342405547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2342405547
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.1414836289
Short name T64
Test name
Test status
Simulation time 9108106322 ps
CPU time 13.14 seconds
Started Aug 19 04:48:00 PM PDT 24
Finished Aug 19 04:48:13 PM PDT 24
Peak memory 201152 kb
Host smart-019f9c2e-42d8-44c8-938f-3be60e4c7748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414836289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.1414836289
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2290741141
Short name T287
Test name
Test status
Simulation time 7051726616 ps
CPU time 10.58 seconds
Started Aug 19 04:47:57 PM PDT 24
Finished Aug 19 04:48:08 PM PDT 24
Peak memory 209596 kb
Host smart-72584a47-bc46-405a-97b4-7ea6a059329c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290741141 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2290741141
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2496301908
Short name T111
Test name
Test status
Simulation time 4843132857 ps
CPU time 4.35 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:48:00 PM PDT 24
Peak memory 201176 kb
Host smart-4fe1205d-dd41-49eb-a169-06dbec1c661d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496301908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.2496301908
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.364108002
Short name T537
Test name
Test status
Simulation time 2018448268 ps
CPU time 3.03 seconds
Started Aug 19 04:50:12 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 201136 kb
Host smart-26a00dfd-15b0-4d21-92d5-21b2dd9da50c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364108002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.364108002
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1053478727
Short name T432
Test name
Test status
Simulation time 201026107659 ps
CPU time 510.76 seconds
Started Aug 19 04:50:13 PM PDT 24
Finished Aug 19 04:58:44 PM PDT 24
Peak memory 201208 kb
Host smart-8950e032-9185-46a8-8dd2-115f2b87e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053478727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
053478727
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.4079938628
Short name T238
Test name
Test status
Simulation time 183474297636 ps
CPU time 115.35 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:52:06 PM PDT 24
Peak memory 201304 kb
Host smart-f1f63070-6861-452f-a40f-d8362e2a3951
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079938628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.4079938628
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2704296050
Short name T648
Test name
Test status
Simulation time 65167443890 ps
CPU time 167.64 seconds
Started Aug 19 04:50:12 PM PDT 24
Finished Aug 19 04:52:59 PM PDT 24
Peak memory 201352 kb
Host smart-28ee22ed-36d8-4cd0-bab2-63613102e1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704296050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.2704296050
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3128124178
Short name T402
Test name
Test status
Simulation time 3106314140 ps
CPU time 4.35 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:14 PM PDT 24
Peak memory 201128 kb
Host smart-2dcbc4a1-b6b8-4a74-a6a0-947bf722c8a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128124178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.3128124178
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.885736164
Short name T155
Test name
Test status
Simulation time 3621460495 ps
CPU time 3.43 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 201164 kb
Host smart-09d72ca1-2f20-4b2d-b440-60a1357519bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885736164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.885736164
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.287133012
Short name T68
Test name
Test status
Simulation time 2630760614 ps
CPU time 2.21 seconds
Started Aug 19 04:50:14 PM PDT 24
Finished Aug 19 04:50:16 PM PDT 24
Peak memory 201136 kb
Host smart-f84db62d-9ed7-4201-b426-facce848b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287133012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.287133012
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1094003846
Short name T727
Test name
Test status
Simulation time 2475512250 ps
CPU time 8.09 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:18 PM PDT 24
Peak memory 201128 kb
Host smart-471d4d39-ba3c-4132-8097-7cd495631c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094003846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1094003846
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1874837101
Short name T710
Test name
Test status
Simulation time 2202011947 ps
CPU time 1.38 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:50:12 PM PDT 24
Peak memory 201128 kb
Host smart-893a0c44-2da1-40ec-9c8b-ec144d8056d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874837101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1874837101
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2591356194
Short name T419
Test name
Test status
Simulation time 2534620925 ps
CPU time 2.4 seconds
Started Aug 19 04:50:09 PM PDT 24
Finished Aug 19 04:50:12 PM PDT 24
Peak memory 201092 kb
Host smart-86c86659-7ca4-499e-b920-9a6323f52623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591356194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2591356194
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.146241338
Short name T218
Test name
Test status
Simulation time 2108832662 ps
CPU time 6.05 seconds
Started Aug 19 04:50:14 PM PDT 24
Finished Aug 19 04:50:21 PM PDT 24
Peak memory 201068 kb
Host smart-fcfd6aa8-da15-4297-a445-6cbeb294284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146241338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.146241338
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3169383341
Short name T547
Test name
Test status
Simulation time 4114141724 ps
CPU time 9.52 seconds
Started Aug 19 04:50:12 PM PDT 24
Finished Aug 19 04:50:22 PM PDT 24
Peak memory 201264 kb
Host smart-954d43c1-f2ee-4b49-b4ac-7e9dc60f101a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169383341 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.3169383341
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1516431972
Short name T665
Test name
Test status
Simulation time 5702465916 ps
CPU time 7.95 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:19 PM PDT 24
Peak memory 201164 kb
Host smart-02d0b698-a5c0-4774-ac82-96edf8b41e39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516431972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.1516431972
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.1716351
Short name T554
Test name
Test status
Simulation time 2032684975 ps
CPU time 1.89 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:26 PM PDT 24
Peak memory 201072 kb
Host smart-173a5b58-4667-4d59-a685-f81eb71f0a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.1716351
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.547467733
Short name T472
Test name
Test status
Simulation time 3374155956 ps
CPU time 2.34 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:26 PM PDT 24
Peak memory 201200 kb
Host smart-632e836f-ae6c-42c0-933d-be5bfbd1a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547467733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.547467733
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1546744911
Short name T242
Test name
Test status
Simulation time 144536053326 ps
CPU time 30.71 seconds
Started Aug 19 04:50:25 PM PDT 24
Finished Aug 19 04:50:56 PM PDT 24
Peak memory 201188 kb
Host smart-9c2c3591-fc73-439b-a6e7-f060f09c0521
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546744911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.1546744911
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1093853446
Short name T230
Test name
Test status
Simulation time 62432977764 ps
CPU time 40.43 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:51:03 PM PDT 24
Peak memory 201372 kb
Host smart-62499ecf-6242-45f4-99ff-937cc022b34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093853446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1093853446
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3185312391
Short name T124
Test name
Test status
Simulation time 3901116324 ps
CPU time 2.32 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:26 PM PDT 24
Peak memory 201132 kb
Host smart-e9e2bc50-c68c-4e29-8bb3-a3631a52cd92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185312391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.3185312391
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.922546154
Short name T6
Test name
Test status
Simulation time 3147208136 ps
CPU time 1.86 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:26 PM PDT 24
Peak memory 201148 kb
Host smart-2c2d92a0-ad1c-438f-a4b4-e2d46e352018
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922546154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.922546154
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3235330092
Short name T457
Test name
Test status
Simulation time 2610598049 ps
CPU time 7.58 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:50:18 PM PDT 24
Peak memory 201144 kb
Host smart-fe81d84f-26ae-4812-aed3-39a0db662ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235330092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3235330092
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1296635277
Short name T749
Test name
Test status
Simulation time 2467782481 ps
CPU time 6.86 seconds
Started Aug 19 04:50:09 PM PDT 24
Finished Aug 19 04:50:16 PM PDT 24
Peak memory 201028 kb
Host smart-b51f68d3-cf3d-45d1-8b90-4e69c1978f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296635277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1296635277
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.446673486
Short name T493
Test name
Test status
Simulation time 2238098610 ps
CPU time 6.38 seconds
Started Aug 19 04:50:12 PM PDT 24
Finished Aug 19 04:50:18 PM PDT 24
Peak memory 201148 kb
Host smart-bdbd506c-b242-409b-b33d-0a4434114074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446673486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.446673486
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3341147214
Short name T490
Test name
Test status
Simulation time 2517996527 ps
CPU time 4.24 seconds
Started Aug 19 04:50:10 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 201156 kb
Host smart-56a1fe07-0829-4c77-b5f8-dff942402889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341147214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3341147214
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3146989784
Short name T429
Test name
Test status
Simulation time 2110976832 ps
CPU time 6.3 seconds
Started Aug 19 04:50:11 PM PDT 24
Finished Aug 19 04:50:17 PM PDT 24
Peak memory 201060 kb
Host smart-7c7eeebd-2686-4549-84b2-e0e1c3997446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146989784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3146989784
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.3616461777
Short name T291
Test name
Test status
Simulation time 9374553565 ps
CPU time 7.21 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:30 PM PDT 24
Peak memory 201040 kb
Host smart-e55a98ee-5c9b-47b4-8d4c-5d9ac161361d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616461777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.3616461777
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4170841121
Short name T420
Test name
Test status
Simulation time 2390529057 ps
CPU time 5.42 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:50:28 PM PDT 24
Peak memory 201180 kb
Host smart-9374b49e-4797-483b-a344-bf7084a1984e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170841121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.4170841121
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.158748978
Short name T699
Test name
Test status
Simulation time 2014079699 ps
CPU time 3.12 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:28 PM PDT 24
Peak memory 201136 kb
Host smart-0e6b3ab9-28cf-4993-9e2a-9196e3896277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158748978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_tes
t.158748978
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.801120926
Short name T119
Test name
Test status
Simulation time 3596807919 ps
CPU time 2.97 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:27 PM PDT 24
Peak memory 201192 kb
Host smart-2907caf8-3b47-4ec4-b0eb-2a00d7dbf9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801120926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.801120926
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3249721221
Short name T775
Test name
Test status
Simulation time 71591973055 ps
CPU time 183.31 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:53:28 PM PDT 24
Peak memory 201280 kb
Host smart-616054b9-c045-48a3-8bf2-c5d9c272f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249721221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.3249721221
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2520085333
Short name T568
Test name
Test status
Simulation time 2761259730 ps
CPU time 7.24 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 201144 kb
Host smart-c8ffd27c-104b-4c5b-95d9-564d93c984b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520085333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.2520085333
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.542855154
Short name T144
Test name
Test status
Simulation time 3930592446 ps
CPU time 4.59 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 201172 kb
Host smart-24ddd78e-9dc4-4bd9-9d75-0a437a8401ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542855154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.542855154
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4017328258
Short name T71
Test name
Test status
Simulation time 2620665438 ps
CPU time 4.15 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 201108 kb
Host smart-dd2f3048-ec56-44ee-9cdb-a9cf152f06d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017328258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.4017328258
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3203393201
Short name T66
Test name
Test status
Simulation time 2461347615 ps
CPU time 3.93 seconds
Started Aug 19 04:50:26 PM PDT 24
Finished Aug 19 04:50:30 PM PDT 24
Peak memory 201128 kb
Host smart-f1fc3359-efa9-4b06-9c93-41bd2ec8de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203393201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3203393201
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1890237085
Short name T192
Test name
Test status
Simulation time 2254530803 ps
CPU time 2.61 seconds
Started Aug 19 04:50:21 PM PDT 24
Finished Aug 19 04:50:24 PM PDT 24
Peak memory 201156 kb
Host smart-c6b78a31-0c2a-4606-86a7-bb15f7d1b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890237085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1890237085
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1910246578
Short name T587
Test name
Test status
Simulation time 2510469943 ps
CPU time 6 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:30 PM PDT 24
Peak memory 201136 kb
Host smart-47e40abc-91b0-4f4d-b372-af88dcb68f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910246578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.1910246578
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1795143155
Short name T742
Test name
Test status
Simulation time 2135283449 ps
CPU time 2.15 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:27 PM PDT 24
Peak memory 200996 kb
Host smart-e66055f5-1e94-491b-aee8-ff29111cd73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795143155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1795143155
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1465979230
Short name T471
Test name
Test status
Simulation time 7040519794 ps
CPU time 9.6 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:50:32 PM PDT 24
Peak memory 201136 kb
Host smart-2dbe1f37-5e17-450b-8863-d7e7f31f48b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465979230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1465979230
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2157806919
Short name T310
Test name
Test status
Simulation time 4322951225 ps
CPU time 12.35 seconds
Started Aug 19 04:50:26 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 211216 kb
Host smart-5f60bf4b-d4b1-4f5b-a24e-a791558f2482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157806919 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2157806919
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1522593634
Short name T61
Test name
Test status
Simulation time 3574527488 ps
CPU time 6.36 seconds
Started Aug 19 04:50:21 PM PDT 24
Finished Aug 19 04:50:28 PM PDT 24
Peak memory 201184 kb
Host smart-aff01169-3001-49b1-aa5c-eb00340c57b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522593634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1522593634
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.1823273596
Short name T592
Test name
Test status
Simulation time 2012107027 ps
CPU time 5.57 seconds
Started Aug 19 04:50:25 PM PDT 24
Finished Aug 19 04:50:30 PM PDT 24
Peak memory 200952 kb
Host smart-38c66065-ca62-4d38-95d6-28493f1ae6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823273596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.1823273596
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.439172432
Short name T13
Test name
Test status
Simulation time 280317283582 ps
CPU time 52.63 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:51:15 PM PDT 24
Peak memory 201232 kb
Host smart-3deebc94-4d79-4785-a05f-f01f75c39cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439172432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.439172432
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1883005291
Short name T474
Test name
Test status
Simulation time 71367445776 ps
CPU time 10.15 seconds
Started Aug 19 04:50:25 PM PDT 24
Finished Aug 19 04:50:35 PM PDT 24
Peak memory 201236 kb
Host smart-40ebc2db-b442-451c-8be9-8827f5982263
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883005291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1883005291
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2886393628
Short name T738
Test name
Test status
Simulation time 2707615471 ps
CPU time 7.38 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:32 PM PDT 24
Peak memory 201128 kb
Host smart-b601fdff-9533-4e74-ad1f-7b6ce62cb00b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886393628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.2886393628
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2468324868
Short name T138
Test name
Test status
Simulation time 4830074426 ps
CPU time 8.45 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:31 PM PDT 24
Peak memory 201152 kb
Host smart-68ed3bcf-05bc-426b-a6b5-26beca0ffc1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468324868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2468324868
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2606474305
Short name T427
Test name
Test status
Simulation time 2614368373 ps
CPU time 7.12 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:31 PM PDT 24
Peak memory 201132 kb
Host smart-e9f9e182-6a0b-4b6e-9fa0-73cefc2a88e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606474305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2606474305
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1608926915
Short name T63
Test name
Test status
Simulation time 2477083633 ps
CPU time 2.59 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:26 PM PDT 24
Peak memory 201148 kb
Host smart-77881bb3-b482-4238-9baa-2ec767e15e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608926915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1608926915
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.572176530
Short name T51
Test name
Test status
Simulation time 2183818460 ps
CPU time 1.79 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:25 PM PDT 24
Peak memory 201132 kb
Host smart-dcc051cd-365c-4713-b5c9-8fa6f1f1fddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572176530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.572176530
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2534192204
Short name T123
Test name
Test status
Simulation time 2514311224 ps
CPU time 4.13 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:27 PM PDT 24
Peak memory 201156 kb
Host smart-d2c9ed2a-ebc5-4014-9f5e-fbb69bf10644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534192204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2534192204
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2588953104
Short name T489
Test name
Test status
Simulation time 2111999603 ps
CPU time 6.21 seconds
Started Aug 19 04:50:26 PM PDT 24
Finished Aug 19 04:50:33 PM PDT 24
Peak memory 201064 kb
Host smart-9c0849c5-2d81-4c93-8574-c7b5e009143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588953104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2588953104
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.630039024
Short name T768
Test name
Test status
Simulation time 13820646225 ps
CPU time 9.72 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:33 PM PDT 24
Peak memory 201096 kb
Host smart-0693b27d-1ced-4a7b-8b25-6b540c668c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630039024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_st
ress_all.630039024
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3914025042
Short name T207
Test name
Test status
Simulation time 15772946884 ps
CPU time 3.07 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:28 PM PDT 24
Peak memory 209616 kb
Host smart-44598bc5-8203-42cf-9537-6e71a5044318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914025042 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3914025042
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.621115208
Short name T77
Test name
Test status
Simulation time 5532329506 ps
CPU time 2.19 seconds
Started Aug 19 04:50:26 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 201180 kb
Host smart-a17e4596-d76f-4bdb-a8f1-640bf86240dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621115208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_ultra_low_pwr.621115208
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2339790304
Short name T737
Test name
Test status
Simulation time 2012879498 ps
CPU time 3.85 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:50:42 PM PDT 24
Peak memory 201136 kb
Host smart-1b9665f8-da6f-4c2f-9505-b8e9cf744b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339790304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2339790304
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.381633866
Short name T408
Test name
Test status
Simulation time 3769697830 ps
CPU time 10.17 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:34 PM PDT 24
Peak memory 201204 kb
Host smart-2c4278b2-6c03-4d54-8292-09bd8c87b6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381633866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.381633866
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.2197792013
Short name T146
Test name
Test status
Simulation time 57873880608 ps
CPU time 34.49 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:50:56 PM PDT 24
Peak memory 201288 kb
Host smart-b30d009d-f108-45ca-9e97-0b60cf765b31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197792013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.2197792013
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1229642647
Short name T715
Test name
Test status
Simulation time 33075495360 ps
CPU time 87.53 seconds
Started Aug 19 04:50:41 PM PDT 24
Finished Aug 19 04:52:09 PM PDT 24
Peak memory 201332 kb
Host smart-77301884-78e3-48fd-bb60-70e9c1372fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229642647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1229642647
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3760270782
Short name T703
Test name
Test status
Simulation time 4215531963 ps
CPU time 11.08 seconds
Started Aug 19 04:50:25 PM PDT 24
Finished Aug 19 04:50:36 PM PDT 24
Peak memory 201140 kb
Host smart-25ed0fc3-f5b5-4c88-a69a-5ecd35706acd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760270782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.3760270782
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3085355299
Short name T7
Test name
Test status
Simulation time 4725052479 ps
CPU time 5.27 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:42 PM PDT 24
Peak memory 201164 kb
Host smart-ee4dc76d-aa10-496b-a93d-4683bd30fa61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085355299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3085355299
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.791372376
Short name T385
Test name
Test status
Simulation time 2625353988 ps
CPU time 2.34 seconds
Started Aug 19 04:50:23 PM PDT 24
Finished Aug 19 04:50:25 PM PDT 24
Peak memory 201112 kb
Host smart-ddc5b9cf-8026-456d-a897-81b47ea876de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791372376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.791372376
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2851372250
Short name T540
Test name
Test status
Simulation time 2474501752 ps
CPU time 1.82 seconds
Started Aug 19 04:50:25 PM PDT 24
Finished Aug 19 04:50:27 PM PDT 24
Peak memory 200924 kb
Host smart-63b0f748-6bde-4085-ad7a-26c4a2b6846a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851372250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2851372250
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4106457002
Short name T532
Test name
Test status
Simulation time 2265783065 ps
CPU time 2.07 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:50:25 PM PDT 24
Peak memory 201140 kb
Host smart-e8fcee5b-a375-4ff9-be71-89c13c41ffcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106457002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.4106457002
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3416883148
Short name T669
Test name
Test status
Simulation time 2510660108 ps
CPU time 6.71 seconds
Started Aug 19 04:50:22 PM PDT 24
Finished Aug 19 04:50:29 PM PDT 24
Peak memory 201136 kb
Host smart-7a8332db-fcb6-4fb6-83df-b5e56c991570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416883148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3416883148
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.2040079105
Short name T165
Test name
Test status
Simulation time 2135135608 ps
CPU time 1.89 seconds
Started Aug 19 04:50:24 PM PDT 24
Finished Aug 19 04:50:26 PM PDT 24
Peak memory 201024 kb
Host smart-faf7cb5d-69b2-42fe-95ec-fa9c8277cf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040079105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2040079105
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.814351538
Short name T300
Test name
Test status
Simulation time 7120886977 ps
CPU time 18.05 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:54 PM PDT 24
Peak memory 201072 kb
Host smart-17814659-f271-423d-95aa-b5f25c274dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814351538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_st
ress_all.814351538
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3184332981
Short name T396
Test name
Test status
Simulation time 2026260528 ps
CPU time 2.03 seconds
Started Aug 19 04:50:42 PM PDT 24
Finished Aug 19 04:50:44 PM PDT 24
Peak memory 200892 kb
Host smart-7175e52d-ac1b-433f-b144-2751eae74a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184332981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3184332981
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3517469363
Short name T280
Test name
Test status
Simulation time 3357837520 ps
CPU time 9.2 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:46 PM PDT 24
Peak memory 201200 kb
Host smart-2b674982-eeba-457b-8704-1beb4d587052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517469363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.3
517469363
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4242829930
Short name T505
Test name
Test status
Simulation time 76032359716 ps
CPU time 52.76 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:51:30 PM PDT 24
Peak memory 201304 kb
Host smart-a2c97752-d471-4a06-b921-762709e46940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242829930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.4242829930
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2609367025
Short name T704
Test name
Test status
Simulation time 3965827522 ps
CPU time 5.67 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:42 PM PDT 24
Peak memory 201144 kb
Host smart-88fd6d85-b77f-454f-821d-dde4a986dfe2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609367025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2609367025
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.582986997
Short name T37
Test name
Test status
Simulation time 3549327656 ps
CPU time 3.8 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:41 PM PDT 24
Peak memory 201104 kb
Host smart-462a5ae9-1133-4769-9911-0fa2f984d20c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582986997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctr
l_edge_detect.582986997
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4227141834
Short name T507
Test name
Test status
Simulation time 2622915199 ps
CPU time 2.27 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:38 PM PDT 24
Peak memory 201148 kb
Host smart-bb9bf9b6-dfcf-436f-9790-8e16e8fe6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227141834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.4227141834
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2154124068
Short name T149
Test name
Test status
Simulation time 2490344204 ps
CPU time 2.19 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201156 kb
Host smart-64ec6574-12ab-4bad-92e9-04fa0e58ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154124068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.2154124068
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2035878381
Short name T101
Test name
Test status
Simulation time 2095733510 ps
CPU time 6.39 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:46 PM PDT 24
Peak memory 201004 kb
Host smart-ae6cc04f-db4d-4b58-afd5-9b97d26fc5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035878381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2035878381
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1858820434
Short name T624
Test name
Test status
Simulation time 2511614254 ps
CPU time 6.81 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:46 PM PDT 24
Peak memory 201096 kb
Host smart-c1eb3035-34fe-44b3-8a6a-db08060f9d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858820434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.1858820434
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.1634035644
Short name T683
Test name
Test status
Simulation time 2112749845 ps
CPU time 5.61 seconds
Started Aug 19 04:50:35 PM PDT 24
Finished Aug 19 04:50:41 PM PDT 24
Peak memory 201072 kb
Host smart-a5a85099-74bc-4264-9a1b-c75ab3bd4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634035644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.1634035644
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2198280155
Short name T527
Test name
Test status
Simulation time 6679341260 ps
CPU time 18.99 seconds
Started Aug 19 04:50:41 PM PDT 24
Finished Aug 19 04:51:00 PM PDT 24
Peak memory 201028 kb
Host smart-beb2330c-fe60-441c-9c1e-1d23e15358bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198280155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2198280155
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2193542825
Short name T535
Test name
Test status
Simulation time 2580281497 ps
CPU time 1.97 seconds
Started Aug 19 04:50:35 PM PDT 24
Finished Aug 19 04:50:37 PM PDT 24
Peak memory 201148 kb
Host smart-7dc0bbe2-c88d-436c-a357-ee61ef4501e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193542825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.2193542825
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.2315383941
Short name T556
Test name
Test status
Simulation time 2039847458 ps
CPU time 1.92 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:38 PM PDT 24
Peak memory 201004 kb
Host smart-609636ee-9e8c-4429-97bb-9e55caae0690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315383941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.2315383941
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.113313658
Short name T281
Test name
Test status
Simulation time 3673963832 ps
CPU time 10.08 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:50 PM PDT 24
Peak memory 201232 kb
Host smart-6dca4c39-1999-43fe-bb45-c34c048b294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113313658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.113313658
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.1067614681
Short name T100
Test name
Test status
Simulation time 35598216408 ps
CPU time 96.27 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:52:14 PM PDT 24
Peak memory 201316 kb
Host smart-e416e22d-77fe-41e0-9fcb-0a0c0f691bfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067614681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.1067614681
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.350586918
Short name T781
Test name
Test status
Simulation time 3397516519 ps
CPU time 2.49 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201116 kb
Host smart-ccc44899-a63a-4995-bd90-698157b68169
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350586918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.350586918
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3271868920
Short name T205
Test name
Test status
Simulation time 3455406606 ps
CPU time 2.85 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:42 PM PDT 24
Peak memory 201144 kb
Host smart-41aace07-7eb0-4d9d-b485-aafbd5675661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271868920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3271868920
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.866418375
Short name T627
Test name
Test status
Simulation time 2622080497 ps
CPU time 2.39 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:50:41 PM PDT 24
Peak memory 201132 kb
Host smart-9d90edce-5809-4cb3-9103-8e3fd924551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866418375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.866418375
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2439741254
Short name T635
Test name
Test status
Simulation time 2562461161 ps
CPU time 1.28 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201096 kb
Host smart-6ac4cac2-879a-486f-a09c-cf18a4b9bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439741254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2439741254
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3048944612
Short name T774
Test name
Test status
Simulation time 2239751271 ps
CPU time 1.88 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201128 kb
Host smart-06cf8063-1589-47de-86b9-bf36ec177bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048944612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3048944612
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3683490684
Short name T449
Test name
Test status
Simulation time 2525544473 ps
CPU time 2.71 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:43 PM PDT 24
Peak memory 201144 kb
Host smart-37d42847-49ae-40cb-8f5a-b43fb6884e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683490684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3683490684
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2053299922
Short name T518
Test name
Test status
Simulation time 2120293338 ps
CPU time 1.93 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201108 kb
Host smart-4caab76e-0a90-4973-b725-716ba6006f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053299922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2053299922
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2594619946
Short name T342
Test name
Test status
Simulation time 83755405813 ps
CPU time 31.45 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:51:08 PM PDT 24
Peak memory 201268 kb
Host smart-d1808e95-6681-4536-a0ee-d5f82442dc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594619946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2594619946
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.549453880
Short name T86
Test name
Test status
Simulation time 12817694592 ps
CPU time 9.52 seconds
Started Aug 19 04:50:35 PM PDT 24
Finished Aug 19 04:50:45 PM PDT 24
Peak memory 201416 kb
Host smart-7fac8eb6-fa06-40fe-8c6d-8329d85eace9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549453880 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.549453880
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1342907323
Short name T567
Test name
Test status
Simulation time 6400042907 ps
CPU time 7.48 seconds
Started Aug 19 04:50:35 PM PDT 24
Finished Aug 19 04:50:43 PM PDT 24
Peak memory 201132 kb
Host smart-46828ccb-d6f6-49f0-af8b-0466033b58b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342907323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.1342907323
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1704654711
Short name T105
Test name
Test status
Simulation time 2014853412 ps
CPU time 6.08 seconds
Started Aug 19 04:50:41 PM PDT 24
Finished Aug 19 04:50:47 PM PDT 24
Peak memory 200980 kb
Host smart-488e0848-7586-45df-87fe-38ddcb10e990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704654711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1704654711
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1189436974
Short name T460
Test name
Test status
Simulation time 3172167031 ps
CPU time 4.76 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:44 PM PDT 24
Peak memory 201240 kb
Host smart-a81cb79e-c723-4478-be10-6e851c3d088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189436974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
189436974
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2320889307
Short name T97
Test name
Test status
Simulation time 126436818326 ps
CPU time 134.87 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:52:52 PM PDT 24
Peak memory 201256 kb
Host smart-c0d32ba1-cb3d-4fd9-a388-eed26cf49b92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320889307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2320889307
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2609450652
Short name T354
Test name
Test status
Simulation time 142234947149 ps
CPU time 176.24 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:53:37 PM PDT 24
Peak memory 201340 kb
Host smart-76c050db-2ef9-4b5d-8d49-9abc82dc623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609450652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2609450652
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3676893449
Short name T273
Test name
Test status
Simulation time 2897373042 ps
CPU time 2.35 seconds
Started Aug 19 04:50:38 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201140 kb
Host smart-abc26de6-a559-4082-9249-6672113f37bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676893449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3676893449
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.458606948
Short name T611
Test name
Test status
Simulation time 2389172456 ps
CPU time 6.66 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:47 PM PDT 24
Peak memory 201076 kb
Host smart-69b4f0f4-fa28-498f-bd16-a8fa87d1bd48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458606948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctr
l_edge_detect.458606948
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1420167005
Short name T651
Test name
Test status
Simulation time 2638943882 ps
CPU time 2.17 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201136 kb
Host smart-e4d8afe6-6e2b-46dc-96ce-74e769ca549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420167005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1420167005
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3551450008
Short name T698
Test name
Test status
Simulation time 2491306055 ps
CPU time 1.62 seconds
Started Aug 19 04:50:37 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201136 kb
Host smart-e869146d-e90a-4a44-8ef0-0fc2485d01d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551450008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.3551450008
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3030146370
Short name T438
Test name
Test status
Simulation time 2098632079 ps
CPU time 3.5 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:40 PM PDT 24
Peak memory 201060 kb
Host smart-e4f19f27-d4ac-4f61-abc0-bd29efb3a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030146370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3030146370
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3243452213
Short name T643
Test name
Test status
Simulation time 2511870833 ps
CPU time 6.29 seconds
Started Aug 19 04:50:42 PM PDT 24
Finished Aug 19 04:50:48 PM PDT 24
Peak memory 201152 kb
Host smart-add104fe-e9f8-478d-81b1-332a5b59e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243452213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3243452213
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2953424524
Short name T784
Test name
Test status
Simulation time 2141896479 ps
CPU time 1.52 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:41 PM PDT 24
Peak memory 201076 kb
Host smart-3440ac4a-a2b4-47b3-bb88-44df38257572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953424524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2953424524
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.2545774047
Short name T36
Test name
Test status
Simulation time 120543018767 ps
CPU time 147.55 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:53:07 PM PDT 24
Peak memory 201220 kb
Host smart-5f895d3c-b032-47ab-90b4-01ccef5672d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545774047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.2545774047
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.354961020
Short name T370
Test name
Test status
Simulation time 16973111401 ps
CPU time 11.32 seconds
Started Aug 19 04:50:35 PM PDT 24
Finished Aug 19 04:50:46 PM PDT 24
Peak memory 209640 kb
Host smart-68cc06a6-5679-4680-977d-8100e15b36dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354961020 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.354961020
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.1882548390
Short name T104
Test name
Test status
Simulation time 2023917965 ps
CPU time 2.54 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:50:50 PM PDT 24
Peak memory 201148 kb
Host smart-c8c4e062-d543-4e83-a47f-b25f97d029da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882548390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.1882548390
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.655062031
Short name T276
Test name
Test status
Simulation time 3622040142 ps
CPU time 10.52 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:50 PM PDT 24
Peak memory 201208 kb
Host smart-2d6d5ac3-2a3b-4a4c-8cd9-091d441a4136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655062031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.655062031
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.4016836964
Short name T588
Test name
Test status
Simulation time 179623873394 ps
CPU time 194.29 seconds
Started Aug 19 04:50:42 PM PDT 24
Finished Aug 19 04:53:56 PM PDT 24
Peak memory 201236 kb
Host smart-01a3d2b2-cb06-4e81-9f0b-b04df18f578d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016836964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.4016836964
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1983426829
Short name T24
Test name
Test status
Simulation time 3018526212 ps
CPU time 4.74 seconds
Started Aug 19 04:50:41 PM PDT 24
Finished Aug 19 04:50:46 PM PDT 24
Peak memory 201024 kb
Host smart-ec186281-181d-48f5-89b4-ec12bfba003b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983426829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.1983426829
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1287159290
Short name T31
Test name
Test status
Simulation time 5949275043 ps
CPU time 7.25 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:48 PM PDT 24
Peak memory 201160 kb
Host smart-de9ea8a1-6b59-43af-8800-653af952cb82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287159290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1287159290
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1840444062
Short name T711
Test name
Test status
Simulation time 2633517448 ps
CPU time 2.39 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:39 PM PDT 24
Peak memory 201152 kb
Host smart-1fd34f72-df3c-4887-977c-d1ea0ac44ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840444062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1840444062
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3517205420
Short name T591
Test name
Test status
Simulation time 2474719787 ps
CPU time 7.23 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:43 PM PDT 24
Peak memory 201148 kb
Host smart-7b02d02f-332c-4744-b082-791c9227c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517205420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3517205420
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1428178808
Short name T455
Test name
Test status
Simulation time 2058681906 ps
CPU time 6.01 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:45 PM PDT 24
Peak memory 201056 kb
Host smart-a633c8c1-0ec2-46b5-871c-cf3b65d4a94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428178808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1428178808
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4053052160
Short name T302
Test name
Test status
Simulation time 2511497974 ps
CPU time 6.74 seconds
Started Aug 19 04:50:36 PM PDT 24
Finished Aug 19 04:50:43 PM PDT 24
Peak memory 201136 kb
Host smart-224467f2-257e-4293-b8e6-252b9483a045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053052160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.4053052160
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2582083788
Short name T447
Test name
Test status
Simulation time 2116588561 ps
CPU time 2.92 seconds
Started Aug 19 04:50:39 PM PDT 24
Finished Aug 19 04:50:42 PM PDT 24
Peak memory 200248 kb
Host smart-8301205c-f94d-4b6f-87bd-5b9236bdefda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582083788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2582083788
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1473102188
Short name T570
Test name
Test status
Simulation time 21646497376 ps
CPU time 13.01 seconds
Started Aug 19 04:50:40 PM PDT 24
Finished Aug 19 04:50:53 PM PDT 24
Peak memory 209632 kb
Host smart-691a8efe-0a4e-4840-8392-ccba8968e568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473102188 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1473102188
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.881748590
Short name T619
Test name
Test status
Simulation time 3380941917 ps
CPU time 5.9 seconds
Started Aug 19 04:50:41 PM PDT 24
Finished Aug 19 04:50:47 PM PDT 24
Peak memory 201076 kb
Host smart-5e990c0a-c67e-4515-95dd-9e92756c18c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881748590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_ultra_low_pwr.881748590
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.3544434807
Short name T708
Test name
Test status
Simulation time 2016037246 ps
CPU time 5.52 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:52 PM PDT 24
Peak memory 201140 kb
Host smart-06879a4d-5c2e-4fe3-8c4b-16e675a45f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544434807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.3544434807
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1984162760
Short name T701
Test name
Test status
Simulation time 3967885378 ps
CPU time 8.48 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:55 PM PDT 24
Peak memory 201204 kb
Host smart-67ca63c7-bf4d-4887-b2cf-7fad90bae9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984162760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1
984162760
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1162679065
Short name T334
Test name
Test status
Simulation time 56334024669 ps
CPU time 39.73 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:51:27 PM PDT 24
Peak memory 201256 kb
Host smart-a9645429-103e-494f-9ba5-7942bb3aa68d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162679065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1162679065
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.4036195446
Short name T373
Test name
Test status
Simulation time 75503491206 ps
CPU time 206.01 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:54:12 PM PDT 24
Peak memory 201316 kb
Host smart-88844f7e-bd25-4f5c-958d-043669800103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036195446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.4036195446
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2485737412
Short name T673
Test name
Test status
Simulation time 3067198804 ps
CPU time 8.4 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:50:55 PM PDT 24
Peak memory 201116 kb
Host smart-6b2d845e-463d-4180-b35e-ddb48658bdf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485737412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.2485737412
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.528460958
Short name T160
Test name
Test status
Simulation time 2868172664 ps
CPU time 4.39 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:50:51 PM PDT 24
Peak memory 201184 kb
Host smart-2d282efd-2cc5-4ead-b326-33bcf90c9934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528460958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctr
l_edge_detect.528460958
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1645519732
Short name T384
Test name
Test status
Simulation time 2628156780 ps
CPU time 2.55 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:50:51 PM PDT 24
Peak memory 201160 kb
Host smart-4a6ba5cf-1cc6-4f2b-bd62-3cd492b08b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645519732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1645519732
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3823871754
Short name T760
Test name
Test status
Simulation time 2472587708 ps
CPU time 7.55 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:50:55 PM PDT 24
Peak memory 201136 kb
Host smart-ea0cbcc3-b493-4139-a54a-34698d998d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823871754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3823871754
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3247511079
Short name T174
Test name
Test status
Simulation time 2059725436 ps
CPU time 3.34 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:50 PM PDT 24
Peak memory 201068 kb
Host smart-f85c4320-1d7a-466a-b97c-7c13f48edb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247511079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3247511079
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2252947857
Short name T541
Test name
Test status
Simulation time 2512765527 ps
CPU time 6.89 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:50:55 PM PDT 24
Peak memory 201104 kb
Host smart-b40d3009-bb23-4775-b02e-c8f2a4581b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252947857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2252947857
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3377206288
Short name T700
Test name
Test status
Simulation time 2155612249 ps
CPU time 1.2 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:48 PM PDT 24
Peak memory 201132 kb
Host smart-0220bed0-52cd-4781-9e89-ef301d388e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377206288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3377206288
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.263945891
Short name T536
Test name
Test status
Simulation time 2633986246 ps
CPU time 7.62 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:54 PM PDT 24
Peak memory 201280 kb
Host smart-35ce5e00-6326-4549-87f1-d570d6e3e70d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263945891 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.263945891
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2634330440
Short name T60
Test name
Test status
Simulation time 4914433940 ps
CPU time 6.22 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:52 PM PDT 24
Peak memory 201164 kb
Host smart-d488321a-dc88-45d8-8945-efc51cdcdf0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634330440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.2634330440
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.4129683400
Short name T185
Test name
Test status
Simulation time 2016775049 ps
CPU time 3.2 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:47:59 PM PDT 24
Peak memory 201348 kb
Host smart-174cfd21-eae7-4279-a592-331369a692fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129683400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.4129683400
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2655037722
Short name T451
Test name
Test status
Simulation time 3144856120 ps
CPU time 1.05 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:47:56 PM PDT 24
Peak memory 201200 kb
Host smart-28c2284d-3a7c-4b72-8bbf-b7d2f3afaab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655037722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2655037722
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3677460267
Short name T772
Test name
Test status
Simulation time 54964446090 ps
CPU time 144.99 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:50:20 PM PDT 24
Peak memory 201248 kb
Host smart-69c76d8d-81b1-4efb-8bbe-7ba14e12ed82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677460267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3677460267
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2317835456
Short name T239
Test name
Test status
Simulation time 74045980042 ps
CPU time 98.38 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:49:35 PM PDT 24
Peak memory 201296 kb
Host smart-ccea47db-0253-488a-987d-eecb337a952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317835456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.2317835456
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2121534587
Short name T533
Test name
Test status
Simulation time 2861996105 ps
CPU time 6.66 seconds
Started Aug 19 04:47:52 PM PDT 24
Finished Aug 19 04:47:59 PM PDT 24
Peak memory 201140 kb
Host smart-912c4ec8-f917-417d-8649-2edb18e469bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121534587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.2121534587
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.791537561
Short name T141
Test name
Test status
Simulation time 3862264874 ps
CPU time 8.18 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:48:04 PM PDT 24
Peak memory 201360 kb
Host smart-6caf5063-766b-465f-89a8-36a9ffa89e0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791537561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_edge_detect.791537561
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1952347041
Short name T550
Test name
Test status
Simulation time 2631916980 ps
CPU time 2.41 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:47:59 PM PDT 24
Peak memory 201140 kb
Host smart-da96d61a-2966-4983-87a2-3da20a72976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952347041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1952347041
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.826994186
Short name T480
Test name
Test status
Simulation time 2467987519 ps
CPU time 2.7 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:47:58 PM PDT 24
Peak memory 201156 kb
Host smart-c356493b-d901-4770-99a2-7e0437bb7378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826994186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.826994186
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1791712820
Short name T600
Test name
Test status
Simulation time 2185571177 ps
CPU time 5.21 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:48:00 PM PDT 24
Peak memory 201096 kb
Host smart-1aa08495-5d99-4fea-a7b1-a369dbace3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791712820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1791712820
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3968162107
Short name T301
Test name
Test status
Simulation time 2588478086 ps
CPU time 1.25 seconds
Started Aug 19 04:48:00 PM PDT 24
Finished Aug 19 04:48:02 PM PDT 24
Peak memory 201168 kb
Host smart-1f5a0a1e-78f6-42c5-ab44-5324a0650def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968162107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.3968162107
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1071871556
Short name T506
Test name
Test status
Simulation time 2108760824 ps
CPU time 5.83 seconds
Started Aug 19 04:47:55 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 199940 kb
Host smart-fe4507c2-d586-4d1b-a1ea-6a9f397456ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071871556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1071871556
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.4163638475
Short name T546
Test name
Test status
Simulation time 6188133992 ps
CPU time 3.97 seconds
Started Aug 19 04:47:57 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201140 kb
Host smart-a9f9ab6d-dafc-431d-8990-37d6c1592775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163638475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.4163638475
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.443959962
Short name T607
Test name
Test status
Simulation time 8836808122 ps
CPU time 11.1 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:48:05 PM PDT 24
Peak memory 209516 kb
Host smart-fd548ceb-63c3-4204-b67d-19dfbf088dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443959962 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.443959962
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1366332708
Short name T575
Test name
Test status
Simulation time 9555434795 ps
CPU time 3.36 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:47:58 PM PDT 24
Peak memory 201136 kb
Host smart-f1662a45-ae63-4678-a11b-472e3cfa3734
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366332708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.1366332708
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3646609305
Short name T729
Test name
Test status
Simulation time 100896357540 ps
CPU time 63.97 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:51:52 PM PDT 24
Peak memory 201372 kb
Host smart-0d1ed79b-b706-409b-b9d5-eb8137fe02ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646609305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.3646609305
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1217367484
Short name T45
Test name
Test status
Simulation time 75941824844 ps
CPU time 108.22 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:52:35 PM PDT 24
Peak memory 201332 kb
Host smart-0ed7ce60-4435-482c-a638-fd3b8239b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217367484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.1217367484
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1542569625
Short name T516
Test name
Test status
Simulation time 26838749000 ps
CPU time 32.75 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:51:20 PM PDT 24
Peak memory 201300 kb
Host smart-76b63b14-7852-4c65-a0fd-f25923fadc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542569625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.1542569625
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2403735040
Short name T240
Test name
Test status
Simulation time 52198148620 ps
CPU time 140.62 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:53:07 PM PDT 24
Peak memory 201308 kb
Host smart-414676a2-8ce2-4da3-8525-66b610855b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403735040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2403735040
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2266982815
Short name T530
Test name
Test status
Simulation time 26100998730 ps
CPU time 19.93 seconds
Started Aug 19 04:50:51 PM PDT 24
Finished Aug 19 04:51:11 PM PDT 24
Peak memory 201396 kb
Host smart-6a67ad1a-58ce-4d22-9548-637d4fcc4312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266982815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.2266982815
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2277250017
Short name T573
Test name
Test status
Simulation time 28351031312 ps
CPU time 21.74 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:51:10 PM PDT 24
Peak memory 201388 kb
Host smart-36203dde-ba94-4f6e-8caf-8854982e6d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277250017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.2277250017
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3617090477
Short name T718
Test name
Test status
Simulation time 24837019389 ps
CPU time 34.03 seconds
Started Aug 19 04:50:49 PM PDT 24
Finished Aug 19 04:51:23 PM PDT 24
Peak memory 201364 kb
Host smart-517f909d-89e9-45eb-84fe-bd8530b9716e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617090477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.3617090477
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.3905358567
Short name T732
Test name
Test status
Simulation time 2014759582 ps
CPU time 3.27 seconds
Started Aug 19 04:48:07 PM PDT 24
Finished Aug 19 04:48:11 PM PDT 24
Peak memory 201048 kb
Host smart-9ae4cb20-49d0-4e56-aac5-e0a2ad5bfca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905358567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.3905358567
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.435385815
Short name T112
Test name
Test status
Simulation time 3488606280 ps
CPU time 4.78 seconds
Started Aug 19 04:47:56 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 201200 kb
Host smart-017a1a66-4137-4ac9-9cfd-1273a0822cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435385815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.435385815
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1893786093
Short name T366
Test name
Test status
Simulation time 75109217986 ps
CPU time 96.73 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:49:31 PM PDT 24
Peak memory 201256 kb
Host smart-34204809-52aa-4e4c-afd6-b5c58fc78684
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893786093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1893786093
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4106106997
Short name T623
Test name
Test status
Simulation time 26108810363 ps
CPU time 15.59 seconds
Started Aug 19 04:48:08 PM PDT 24
Finished Aug 19 04:48:23 PM PDT 24
Peak memory 201384 kb
Host smart-d86ad097-b350-4691-b81d-91993db34f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106106997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.4106106997
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3914381294
Short name T404
Test name
Test status
Simulation time 2678305139 ps
CPU time 8.09 seconds
Started Aug 19 04:47:57 PM PDT 24
Finished Aug 19 04:48:05 PM PDT 24
Peak memory 201036 kb
Host smart-0fbdf3b6-eb57-4e73-ac0a-4a0ada4d989b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914381294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.3914381294
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3663314405
Short name T675
Test name
Test status
Simulation time 2724709368 ps
CPU time 1.18 seconds
Started Aug 19 04:47:57 PM PDT 24
Finished Aug 19 04:47:58 PM PDT 24
Peak memory 201136 kb
Host smart-37408b0d-1f07-481f-9233-eba03a16f54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663314405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3663314405
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2683795041
Short name T712
Test name
Test status
Simulation time 2492168486 ps
CPU time 7.73 seconds
Started Aug 19 04:47:57 PM PDT 24
Finished Aug 19 04:48:05 PM PDT 24
Peak memory 201164 kb
Host smart-220c4bd0-6a38-4842-b201-a0c27765fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683795041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.2683795041
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3093191580
Short name T120
Test name
Test status
Simulation time 2223727724 ps
CPU time 3.43 seconds
Started Aug 19 04:48:00 PM PDT 24
Finished Aug 19 04:48:03 PM PDT 24
Peak memory 201156 kb
Host smart-d4ad9cad-6243-4ff8-8a1e-c7fcbecfefd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093191580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3093191580
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.4183266119
Short name T696
Test name
Test status
Simulation time 2533491863 ps
CPU time 2.21 seconds
Started Aug 19 04:47:54 PM PDT 24
Finished Aug 19 04:47:56 PM PDT 24
Peak memory 201152 kb
Host smart-582cb67e-71e8-4207-b8e6-1f6b0f7290ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183266119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.4183266119
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.1691040620
Short name T416
Test name
Test status
Simulation time 2134414726 ps
CPU time 1.94 seconds
Started Aug 19 04:47:58 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 200964 kb
Host smart-bbfdbf9c-e7e0-4671-ab7d-dcbbcf284850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691040620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1691040620
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1963252619
Short name T206
Test name
Test status
Simulation time 17499372037 ps
CPU time 11.8 seconds
Started Aug 19 04:48:08 PM PDT 24
Finished Aug 19 04:48:20 PM PDT 24
Peak memory 217752 kb
Host smart-5cad0351-d82a-4a93-8a7b-ed80ce9a8a89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963252619 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1963252619
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2652251384
Short name T2
Test name
Test status
Simulation time 6449290236 ps
CPU time 2.76 seconds
Started Aug 19 04:48:00 PM PDT 24
Finished Aug 19 04:48:03 PM PDT 24
Peak memory 201148 kb
Host smart-4171dba6-dc4d-400f-85dd-c21fc2f3c5b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652251384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.2652251384
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.777278098
Short name T787
Test name
Test status
Simulation time 52804674625 ps
CPU time 138.69 seconds
Started Aug 19 04:50:52 PM PDT 24
Finished Aug 19 04:53:11 PM PDT 24
Peak memory 201256 kb
Host smart-d647306d-b6a3-4dd1-bc6b-7be4b3756ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777278098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.777278098
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2350002059
Short name T343
Test name
Test status
Simulation time 53801544717 ps
CPU time 38.49 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:51:26 PM PDT 24
Peak memory 201312 kb
Host smart-d7ee5ba3-9194-4511-8afc-c926873978e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350002059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2350002059
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2762661827
Short name T89
Test name
Test status
Simulation time 26105094788 ps
CPU time 13.24 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:50:59 PM PDT 24
Peak memory 200224 kb
Host smart-711498b4-24c4-4ac4-838f-eaed41da21eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762661827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.2762661827
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.222723458
Short name T709
Test name
Test status
Simulation time 44096011951 ps
CPU time 109.89 seconds
Started Aug 19 04:50:52 PM PDT 24
Finished Aug 19 04:52:42 PM PDT 24
Peak memory 201316 kb
Host smart-47c6da0c-020f-4c6f-a924-93f12f298a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222723458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_wi
th_pre_cond.222723458
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.276757616
Short name T337
Test name
Test status
Simulation time 94286632280 ps
CPU time 61.36 seconds
Started Aug 19 04:50:46 PM PDT 24
Finished Aug 19 04:51:48 PM PDT 24
Peak memory 201380 kb
Host smart-80022baf-23e8-436b-a3eb-cc974b4f2d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276757616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_wi
th_pre_cond.276757616
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2281625759
Short name T553
Test name
Test status
Simulation time 29636552750 ps
CPU time 21.24 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:51:09 PM PDT 24
Peak memory 201400 kb
Host smart-923092c2-20aa-43c6-beac-4202a4a16e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281625759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2281625759
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.107051509
Short name T721
Test name
Test status
Simulation time 2034987741 ps
CPU time 2.01 seconds
Started Aug 19 04:48:06 PM PDT 24
Finished Aug 19 04:48:08 PM PDT 24
Peak memory 201136 kb
Host smart-389f27d2-7554-4a36-85eb-3c8bc4bcf212
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107051509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test
.107051509
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3849740983
Short name T558
Test name
Test status
Simulation time 157814304837 ps
CPU time 24.82 seconds
Started Aug 19 04:48:06 PM PDT 24
Finished Aug 19 04:48:31 PM PDT 24
Peak memory 201272 kb
Host smart-ea3f8b43-1719-42b5-bff8-098b9a516715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849740983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3849740983
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3309399393
Short name T773
Test name
Test status
Simulation time 78711731609 ps
CPU time 51.56 seconds
Started Aug 19 04:48:06 PM PDT 24
Finished Aug 19 04:48:58 PM PDT 24
Peak memory 201308 kb
Host smart-37c7a249-cabf-43f9-80d0-93e9d70f9136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309399393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.3309399393
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1796934601
Short name T203
Test name
Test status
Simulation time 2735277193 ps
CPU time 7.73 seconds
Started Aug 19 04:48:06 PM PDT 24
Finished Aug 19 04:48:14 PM PDT 24
Peak memory 201088 kb
Host smart-36d7363e-8ea0-4623-8ea6-093d520b3f3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796934601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1796934601
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2237217716
Short name T132
Test name
Test status
Simulation time 5204629095 ps
CPU time 3.34 seconds
Started Aug 19 04:48:04 PM PDT 24
Finished Aug 19 04:48:08 PM PDT 24
Peak memory 201152 kb
Host smart-57e9e592-3be9-47c2-8f4b-614501990166
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237217716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2237217716
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1157337519
Short name T170
Test name
Test status
Simulation time 2609246112 ps
CPU time 7.7 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:48:13 PM PDT 24
Peak memory 201152 kb
Host smart-67f1835c-b3e4-4a75-85ca-255b85bfc61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157337519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1157337519
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.67731778
Short name T657
Test name
Test status
Simulation time 2473782677 ps
CPU time 3.9 seconds
Started Aug 19 04:48:08 PM PDT 24
Finished Aug 19 04:48:11 PM PDT 24
Peak memory 201112 kb
Host smart-43307442-46e6-4751-b9df-c123f0b6dde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67731778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.67731778
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1445171327
Short name T581
Test name
Test status
Simulation time 2203909573 ps
CPU time 2.09 seconds
Started Aug 19 04:48:07 PM PDT 24
Finished Aug 19 04:48:10 PM PDT 24
Peak memory 201132 kb
Host smart-b97dc9e3-964c-42fb-aa93-267272a32494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445171327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1445171327
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3626279125
Short name T599
Test name
Test status
Simulation time 2512535388 ps
CPU time 7.35 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:48:12 PM PDT 24
Peak memory 201136 kb
Host smart-f025bc28-669e-489a-8639-0885e3e1c54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626279125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.3626279125
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.2598512773
Short name T102
Test name
Test status
Simulation time 2118454201 ps
CPU time 3.33 seconds
Started Aug 19 04:48:06 PM PDT 24
Finished Aug 19 04:48:09 PM PDT 24
Peak memory 201024 kb
Host smart-0293923c-af29-4cc2-b90d-bb4c40720479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598512773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2598512773
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1991276272
Short name T650
Test name
Test status
Simulation time 12647013181 ps
CPU time 6.68 seconds
Started Aug 19 04:48:07 PM PDT 24
Finished Aug 19 04:48:14 PM PDT 24
Peak memory 201364 kb
Host smart-3c06a367-0ce5-48c5-9ce9-0cfa1b3a6747
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991276272 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1991276272
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.360764541
Short name T544
Test name
Test status
Simulation time 3873015345 ps
CPU time 1.66 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:48:07 PM PDT 24
Peak memory 201136 kb
Host smart-754eec5e-40e8-4c4e-8666-4499bd7387fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360764541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ultra_low_pwr.360764541
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3657771504
Short name T341
Test name
Test status
Simulation time 97952389958 ps
CPU time 137.12 seconds
Started Aug 19 04:50:53 PM PDT 24
Finished Aug 19 04:53:10 PM PDT 24
Peak memory 201304 kb
Host smart-59634d3e-7d6f-4799-a8fe-e52e4617a468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657771504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.3657771504
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1438334052
Short name T226
Test name
Test status
Simulation time 26331706116 ps
CPU time 63.77 seconds
Started Aug 19 04:50:54 PM PDT 24
Finished Aug 19 04:51:57 PM PDT 24
Peak memory 200896 kb
Host smart-a02da692-1af1-4ce2-9a7d-b35afbdd1336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438334052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1438334052
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.406266007
Short name T148
Test name
Test status
Simulation time 173747822767 ps
CPU time 116.37 seconds
Started Aug 19 04:50:51 PM PDT 24
Finished Aug 19 04:52:47 PM PDT 24
Peak memory 201324 kb
Host smart-930f34fe-2782-4d3d-b9e6-5c0d1395c0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406266007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.406266007
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3194377393
Short name T361
Test name
Test status
Simulation time 30033989940 ps
CPU time 20.49 seconds
Started Aug 19 04:50:49 PM PDT 24
Finished Aug 19 04:51:10 PM PDT 24
Peak memory 201308 kb
Host smart-83992ddc-681b-4d36-b2eb-2d817ba89865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194377393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.3194377393
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.781265062
Short name T374
Test name
Test status
Simulation time 58888752503 ps
CPU time 39.74 seconds
Started Aug 19 04:50:53 PM PDT 24
Finished Aug 19 04:51:33 PM PDT 24
Peak memory 201320 kb
Host smart-be4ac478-b919-456c-b0d2-639e77a166b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781265062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_wi
th_pre_cond.781265062
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3935658752
Short name T151
Test name
Test status
Simulation time 52305169957 ps
CPU time 66.59 seconds
Started Aug 19 04:50:54 PM PDT 24
Finished Aug 19 04:52:00 PM PDT 24
Peak memory 201384 kb
Host smart-141177d0-a8a3-4dcc-b879-4d77fe8dd66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935658752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.3935658752
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1819293505
Short name T736
Test name
Test status
Simulation time 117407778494 ps
CPU time 67.87 seconds
Started Aug 19 04:50:47 PM PDT 24
Finished Aug 19 04:51:55 PM PDT 24
Peak memory 201408 kb
Host smart-af78ef4a-0741-41f0-a8e6-b6e6aec00d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819293505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1819293505
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1430087255
Short name T459
Test name
Test status
Simulation time 2011260296 ps
CPU time 5.56 seconds
Started Aug 19 04:48:20 PM PDT 24
Finished Aug 19 04:48:26 PM PDT 24
Peak memory 201072 kb
Host smart-366cd99b-b336-490b-9eba-6d17d4dc6173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430087255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1430087255
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2725583937
Short name T44
Test name
Test status
Simulation time 3698637474 ps
CPU time 5.46 seconds
Started Aug 19 04:48:04 PM PDT 24
Finished Aug 19 04:48:10 PM PDT 24
Peak memory 201200 kb
Host smart-69668090-13a8-473e-a1c4-817c457fdb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725583937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2725583937
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1067603748
Short name T365
Test name
Test status
Simulation time 55740518040 ps
CPU time 68.59 seconds
Started Aug 19 04:48:04 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 201252 kb
Host smart-caee6478-8002-4b59-92fd-bf9a16dba421
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067603748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1067603748
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1265116061
Short name T8
Test name
Test status
Simulation time 50398406946 ps
CPU time 35.03 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:48:54 PM PDT 24
Peak memory 201356 kb
Host smart-989db686-3733-4be4-a3df-f5a60f2c33bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265116061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.1265116061
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.211073038
Short name T158
Test name
Test status
Simulation time 969435050882 ps
CPU time 1187.8 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 05:07:53 PM PDT 24
Peak memory 201076 kb
Host smart-1183e1d9-63f9-43db-a490-0a1927438b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211073038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ec_pwr_on_rst.211073038
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.307432929
Short name T179
Test name
Test status
Simulation time 2822915034 ps
CPU time 2.05 seconds
Started Aug 19 04:48:18 PM PDT 24
Finished Aug 19 04:48:20 PM PDT 24
Peak memory 201160 kb
Host smart-9454fe82-069d-4d49-b1d8-3f6412659930
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307432929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl
_edge_detect.307432929
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2369640698
Short name T389
Test name
Test status
Simulation time 2623728983 ps
CPU time 2.24 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:48:07 PM PDT 24
Peak memory 201092 kb
Host smart-906c350b-7f91-4af9-b4ae-930129b80969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369640698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2369640698
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1162430502
Short name T664
Test name
Test status
Simulation time 2456235556 ps
CPU time 7.89 seconds
Started Aug 19 04:48:04 PM PDT 24
Finished Aug 19 04:48:12 PM PDT 24
Peak memory 201156 kb
Host smart-c53571e7-c420-43aa-9472-49b96209f95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162430502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1162430502
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3412530617
Short name T418
Test name
Test status
Simulation time 2016606261 ps
CPU time 5.43 seconds
Started Aug 19 04:48:06 PM PDT 24
Finished Aug 19 04:48:11 PM PDT 24
Peak memory 201068 kb
Host smart-d7204433-350e-4815-a375-1f6a9c7714f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412530617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3412530617
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.669780188
Short name T147
Test name
Test status
Simulation time 2512661840 ps
CPU time 3.59 seconds
Started Aug 19 04:48:05 PM PDT 24
Finished Aug 19 04:48:09 PM PDT 24
Peak memory 201152 kb
Host smart-a71b2d60-ac8f-4ccf-9d00-94bfe53f61a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669780188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.669780188
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.596210717
Short name T439
Test name
Test status
Simulation time 2114120382 ps
CPU time 3.36 seconds
Started Aug 19 04:48:07 PM PDT 24
Finished Aug 19 04:48:10 PM PDT 24
Peak memory 201080 kb
Host smart-95a1b523-0785-40b4-8492-bd6fd1c21a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596210717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.596210717
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.281348850
Short name T608
Test name
Test status
Simulation time 14567565958 ps
CPU time 7.52 seconds
Started Aug 19 04:48:20 PM PDT 24
Finished Aug 19 04:48:28 PM PDT 24
Peak memory 201060 kb
Host smart-c23f9688-3b4f-4828-9779-4f6c4a52b029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281348850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str
ess_all.281348850
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3359184273
Short name T306
Test name
Test status
Simulation time 4115713935 ps
CPU time 11.47 seconds
Started Aug 19 04:48:18 PM PDT 24
Finished Aug 19 04:48:30 PM PDT 24
Peak memory 209444 kb
Host smart-f918cf7c-9283-41a9-89d1-f316bb17d7d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359184273 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3359184273
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1701780168
Short name T697
Test name
Test status
Simulation time 6009205884 ps
CPU time 2.06 seconds
Started Aug 19 04:48:08 PM PDT 24
Finished Aug 19 04:48:10 PM PDT 24
Peak memory 201144 kb
Host smart-e3535acc-d6d8-4da9-a2e0-bbd4b1f37f0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701780168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1701780168
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2900436346
Short name T666
Test name
Test status
Simulation time 93122329937 ps
CPU time 242.46 seconds
Started Aug 19 04:50:53 PM PDT 24
Finished Aug 19 04:54:56 PM PDT 24
Peak memory 201364 kb
Host smart-996f76d0-f523-451d-948d-309e924b95dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900436346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.2900436346
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.338064880
Short name T371
Test name
Test status
Simulation time 88982556670 ps
CPU time 233.52 seconds
Started Aug 19 04:50:52 PM PDT 24
Finished Aug 19 04:54:45 PM PDT 24
Peak memory 201288 kb
Host smart-e16f48ac-bdf3-4605-882f-2d4d84939422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338064880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_wi
th_pre_cond.338064880
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.34539862
Short name T360
Test name
Test status
Simulation time 65768080697 ps
CPU time 46.43 seconds
Started Aug 19 04:50:48 PM PDT 24
Finished Aug 19 04:51:34 PM PDT 24
Peak memory 201588 kb
Host smart-02b045ab-a3a1-43e5-bfe1-80c8004ef029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34539862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_wit
h_pre_cond.34539862
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1868396296
Short name T227
Test name
Test status
Simulation time 25581828056 ps
CPU time 62.43 seconds
Started Aug 19 04:50:52 PM PDT 24
Finished Aug 19 04:51:54 PM PDT 24
Peak memory 201360 kb
Host smart-01de271b-1ea7-433c-9da5-1c8d2dbe761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868396296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1868396296
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1993471499
Short name T348
Test name
Test status
Simulation time 80615247487 ps
CPU time 205.76 seconds
Started Aug 19 04:50:50 PM PDT 24
Finished Aug 19 04:54:15 PM PDT 24
Peak memory 201360 kb
Host smart-2fb50aad-2142-4baa-8df9-8ff04aee000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993471499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.1993471499
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2982844598
Short name T41
Test name
Test status
Simulation time 23608326074 ps
CPU time 16.06 seconds
Started Aug 19 04:50:53 PM PDT 24
Finished Aug 19 04:51:09 PM PDT 24
Peak memory 201340 kb
Host smart-a0d3932c-123a-4fd2-815b-ae80f2fecee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982844598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.2982844598
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1393656336
Short name T766
Test name
Test status
Simulation time 25587991072 ps
CPU time 31.35 seconds
Started Aug 19 04:50:49 PM PDT 24
Finished Aug 19 04:51:20 PM PDT 24
Peak memory 201332 kb
Host smart-1a06dc71-dd04-4fef-bf3f-e14a25f2adc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393656336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.1393656336
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3539532836
Short name T353
Test name
Test status
Simulation time 53852590969 ps
CPU time 68.54 seconds
Started Aug 19 04:50:54 PM PDT 24
Finished Aug 19 04:52:02 PM PDT 24
Peak memory 200948 kb
Host smart-8cd69a16-4884-4851-87a8-496d78f03e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539532836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3539532836
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.2632431177
Short name T521
Test name
Test status
Simulation time 2017970883 ps
CPU time 3.95 seconds
Started Aug 19 04:48:14 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201136 kb
Host smart-86b7e085-f4d8-4353-8cc8-1fa08de1dd9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632431177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.2632431177
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3037700672
Short name T726
Test name
Test status
Simulation time 3546019035 ps
CPU time 10.15 seconds
Started Aug 19 04:48:18 PM PDT 24
Finished Aug 19 04:48:29 PM PDT 24
Peak memory 201204 kb
Host smart-2fa88ef3-a28f-4fc8-8ff5-6df5725df371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037700672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3037700672
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2959952454
Short name T347
Test name
Test status
Simulation time 114318681904 ps
CPU time 267.43 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:52:47 PM PDT 24
Peak memory 201252 kb
Host smart-d2951bce-33fe-4012-bf82-c745cdbac282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959952454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2959952454
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1896379495
Short name T410
Test name
Test status
Simulation time 3369857447 ps
CPU time 9.4 seconds
Started Aug 19 04:48:15 PM PDT 24
Finished Aug 19 04:48:24 PM PDT 24
Peak memory 201132 kb
Host smart-495e5dcd-6ff5-4150-b215-75b3a947be33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896379495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.1896379495
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.4122098887
Short name T216
Test name
Test status
Simulation time 3740242451 ps
CPU time 1.81 seconds
Started Aug 19 04:48:19 PM PDT 24
Finished Aug 19 04:48:21 PM PDT 24
Peak memory 201140 kb
Host smart-09c0f941-23ec-4090-8cfd-3aedf99f0681
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122098887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.4122098887
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3743693297
Short name T574
Test name
Test status
Simulation time 2619796795 ps
CPU time 4.15 seconds
Started Aug 19 04:48:18 PM PDT 24
Finished Aug 19 04:48:23 PM PDT 24
Peak memory 201128 kb
Host smart-ec212a0a-178d-4ac5-b7d7-25b7ec551f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743693297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.3743693297
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.4206781701
Short name T213
Test name
Test status
Simulation time 2476589907 ps
CPU time 2.05 seconds
Started Aug 19 04:48:16 PM PDT 24
Finished Aug 19 04:48:18 PM PDT 24
Peak memory 201144 kb
Host smart-aef20a45-11ee-440f-bd9d-69b6b7608ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206781701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.4206781701
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2560566384
Short name T782
Test name
Test status
Simulation time 2128618556 ps
CPU time 6.08 seconds
Started Aug 19 04:48:18 PM PDT 24
Finished Aug 19 04:48:24 PM PDT 24
Peak memory 201052 kb
Host smart-f16c737c-c425-487c-beed-ed70393f0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560566384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2560566384
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3190186415
Short name T577
Test name
Test status
Simulation time 2509142386 ps
CPU time 7.36 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:25 PM PDT 24
Peak memory 201132 kb
Host smart-f2577be3-49e6-4808-8d44-c79ec55e22cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190186415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3190186415
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.578958372
Short name T634
Test name
Test status
Simulation time 2162681335 ps
CPU time 1.16 seconds
Started Aug 19 04:48:20 PM PDT 24
Finished Aug 19 04:48:22 PM PDT 24
Peak memory 201148 kb
Host smart-04c51a3f-f6f9-4cfa-ace3-3e28e3df458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578958372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.578958372
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2862059844
Short name T114
Test name
Test status
Simulation time 4315875361 ps
CPU time 7.17 seconds
Started Aug 19 04:48:17 PM PDT 24
Finished Aug 19 04:48:25 PM PDT 24
Peak memory 201160 kb
Host smart-3e7f1019-4a10-4d4f-92a3-b56632f63ca9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862059844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.2862059844
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3697940343
Short name T90
Test name
Test status
Simulation time 31416624146 ps
CPU time 37.35 seconds
Started Aug 19 04:50:59 PM PDT 24
Finished Aug 19 04:51:36 PM PDT 24
Peak memory 201332 kb
Host smart-f7071b86-17b6-4479-bb64-ed831caec85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697940343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.3697940343
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2973226051
Short name T779
Test name
Test status
Simulation time 64858522546 ps
CPU time 87.54 seconds
Started Aug 19 04:50:58 PM PDT 24
Finished Aug 19 04:52:26 PM PDT 24
Peak memory 201336 kb
Host smart-74ab8570-f9a3-4851-9d02-d86a6e8d6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973226051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.2973226051
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3252354599
Short name T269
Test name
Test status
Simulation time 58882395105 ps
CPU time 13.89 seconds
Started Aug 19 04:50:57 PM PDT 24
Finished Aug 19 04:51:11 PM PDT 24
Peak memory 201312 kb
Host smart-ca41f17a-fb37-4a94-adc9-86128e28f356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252354599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.3252354599
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3075067370
Short name T363
Test name
Test status
Simulation time 87187767202 ps
CPU time 53.24 seconds
Started Aug 19 04:51:03 PM PDT 24
Finished Aug 19 04:51:56 PM PDT 24
Peak memory 201368 kb
Host smart-267cc91a-58f9-4b72-9057-cf7b12be6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075067370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3075067370
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2104823822
Short name T224
Test name
Test status
Simulation time 23583432621 ps
CPU time 61.48 seconds
Started Aug 19 04:50:58 PM PDT 24
Finished Aug 19 04:51:59 PM PDT 24
Peak memory 201340 kb
Host smart-323cbce2-efd5-4633-9601-4899960970ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104823822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.2104823822
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.367587421
Short name T72
Test name
Test status
Simulation time 72376137438 ps
CPU time 94.05 seconds
Started Aug 19 04:50:59 PM PDT 24
Finished Aug 19 04:52:33 PM PDT 24
Peak memory 201196 kb
Host smart-20cf9aa5-bb9e-4f6d-8cc1-409bdbfbcbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367587421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_wi
th_pre_cond.367587421
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3632548127
Short name T496
Test name
Test status
Simulation time 45852618586 ps
CPU time 116.38 seconds
Started Aug 19 04:50:58 PM PDT 24
Finished Aug 19 04:52:55 PM PDT 24
Peak memory 201308 kb
Host smart-853b407f-51ed-478f-b2c6-4cd8cf56e6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632548127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3632548127
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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