Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.85 99.23 96.33 100.00 96.79 98.60 99.33 87.66


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.84 60.84 78.84 78.84 67.95 67.95 92.47 92.47 17.31 17.31 79.30 79.30 69.65 69.65 20.37 20.37 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3446431279
68.60 7.76 83.15 4.31 73.41 5.46 92.92 0.46 33.97 16.67 83.84 4.55 75.63 5.97 37.25 16.88 /workspace/coverage/default/1.sysrst_ctrl_stress_all.1536247814
75.08 6.49 90.09 6.94 83.77 10.36 95.66 2.74 36.54 2.56 90.46 6.62 79.87 4.24 49.19 11.93 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2190500232
79.42 4.34 92.44 2.35 85.92 2.15 95.66 0.00 51.92 15.38 92.50 2.03 86.42 6.55 51.11 1.92 /workspace/coverage/default/49.sysrst_ctrl_stress_all.930024926
82.95 3.53 95.15 2.71 89.31 3.39 96.80 1.14 61.54 9.62 94.71 2.22 91.71 5.30 51.46 0.35 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1962379023
86.32 3.36 96.70 1.55 91.28 1.97 96.80 0.00 78.85 17.31 96.34 1.63 92.68 0.96 51.57 0.12 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1570672246
87.69 1.37 96.77 0.07 92.64 1.37 97.49 0.68 78.85 0.00 96.45 0.11 92.77 0.10 58.85 7.28 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1372474232
88.91 1.22 96.87 0.09 92.80 0.15 97.49 0.00 79.49 0.64 96.49 0.04 92.87 0.10 66.36 7.51 /workspace/coverage/default/39.sysrst_ctrl_stress_all.712349503
89.95 1.04 97.42 0.56 93.35 0.56 97.49 0.00 82.05 2.56 96.86 0.37 93.83 0.96 68.63 2.27 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2851731521
90.96 1.02 98.00 0.58 93.96 0.61 97.49 0.00 85.90 3.85 97.26 0.41 95.28 1.45 68.86 0.23 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1072810885
91.41 0.44 98.19 0.19 94.19 0.23 97.49 0.00 87.82 1.92 97.45 0.18 95.86 0.58 68.86 0.00 /workspace/coverage/default/25.sysrst_ctrl_stress_all.1019458573
91.84 0.43 98.21 0.02 94.19 0.00 97.49 0.00 88.46 0.64 97.49 0.04 95.86 0.00 71.19 2.33 /workspace/coverage/default/9.sysrst_ctrl_stress_all.1003574590
92.24 0.40 98.34 0.13 94.26 0.08 97.49 0.00 90.38 1.92 97.60 0.11 96.15 0.29 71.48 0.29 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.903552931
92.58 0.34 98.41 0.07 94.34 0.08 97.72 0.23 90.38 0.00 97.63 0.04 97.11 0.96 72.47 0.99 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2897547631
92.90 0.32 98.43 0.02 94.46 0.13 97.72 0.00 90.38 0.00 97.63 0.00 97.11 0.00 74.56 2.10 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2364424068
93.20 0.30 98.49 0.06 94.57 0.10 98.17 0.46 91.03 0.64 97.71 0.07 97.50 0.39 74.97 0.41 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1033897945
93.49 0.29 98.49 0.00 94.59 0.03 99.77 1.60 91.03 0.00 97.71 0.00 97.59 0.10 75.26 0.29 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3472463833
93.76 0.27 98.58 0.09 94.69 0.10 99.77 0.00 92.31 1.28 97.82 0.11 97.88 0.29 75.26 0.00 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2761236022
94.00 0.24 98.66 0.07 94.74 0.05 99.77 0.00 93.59 1.28 97.89 0.07 98.07 0.19 75.26 0.00 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3827700194
94.21 0.22 98.66 0.00 94.74 0.00 99.77 0.00 93.59 0.00 97.89 0.00 98.07 0.00 76.78 1.51 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2983221041
94.42 0.21 98.69 0.04 94.77 0.03 99.77 0.00 93.59 0.00 97.97 0.07 98.17 0.10 78.00 1.22 /workspace/coverage/default/40.sysrst_ctrl_stress_all.2422142917
94.60 0.18 98.69 0.00 95.45 0.68 99.77 0.00 93.59 0.00 97.97 0.00 98.17 0.00 78.58 0.58 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1086057486
94.78 0.17 98.69 0.00 95.58 0.13 99.77 0.00 93.59 0.00 98.00 0.04 98.17 0.00 79.63 1.05 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.588713295
94.94 0.17 98.69 0.00 95.58 0.00 99.77 0.00 93.59 0.00 98.00 0.00 98.17 0.00 80.79 1.16 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3190006122
95.09 0.14 98.73 0.04 95.60 0.03 99.77 0.00 94.23 0.64 98.04 0.04 98.27 0.10 80.97 0.17 /workspace/coverage/default/48.sysrst_ctrl_stress_all.1716527783
95.21 0.13 98.79 0.06 95.63 0.03 99.77 0.00 94.87 0.64 98.11 0.07 98.36 0.10 80.97 0.00 /workspace/coverage/default/10.sysrst_ctrl_stress_all.3315711620
95.34 0.13 98.90 0.11 95.65 0.03 99.77 0.00 95.51 0.64 98.23 0.11 98.36 0.00 80.97 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1094454550
95.47 0.12 98.96 0.06 95.65 0.00 99.77 0.00 95.51 0.00 98.23 0.00 98.36 0.00 81.78 0.81 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1973547589
95.59 0.12 98.99 0.04 95.68 0.03 99.77 0.00 96.15 0.64 98.26 0.04 98.46 0.10 81.78 0.00 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2348876913
95.70 0.12 99.03 0.04 95.70 0.03 99.77 0.00 96.79 0.64 98.30 0.04 98.55 0.10 81.78 0.00 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1057183552
95.82 0.12 99.05 0.02 95.70 0.00 99.77 0.00 96.79 0.00 98.30 0.00 98.55 0.00 82.60 0.81 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3170934204
95.94 0.11 99.09 0.04 95.96 0.25 99.77 0.00 96.79 0.00 98.37 0.07 98.75 0.19 82.83 0.23 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.1745598058
96.02 0.08 99.09 0.00 95.96 0.00 99.77 0.00 96.79 0.00 98.37 0.00 98.75 0.00 83.41 0.58 /workspace/coverage/default/6.sysrst_ctrl_stress_all.2890257983
96.10 0.08 99.09 0.00 95.96 0.00 99.77 0.00 96.79 0.00 98.37 0.00 99.33 0.58 83.41 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4225746240
96.18 0.07 99.09 0.00 95.96 0.00 99.77 0.00 96.79 0.00 98.37 0.00 99.33 0.00 83.93 0.52 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1809555903
96.24 0.07 99.09 0.00 95.96 0.00 99.77 0.00 96.79 0.00 98.37 0.00 99.33 0.00 84.40 0.47 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.1893971894
96.30 0.05 99.14 0.06 96.03 0.08 100.00 0.23 96.79 0.00 98.37 0.00 99.33 0.00 84.40 0.00 /workspace/coverage/default/16.sysrst_ctrl_alert_test.302003800
96.35 0.05 99.14 0.00 96.03 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 84.75 0.35 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1600527660
96.39 0.04 99.14 0.00 96.03 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 85.04 0.29 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.508318582
96.43 0.04 99.14 0.00 96.03 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 85.33 0.29 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3851803841
96.46 0.04 99.14 0.00 96.28 0.25 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 85.33 0.00 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.2527133584
96.50 0.03 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 85.56 0.23 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2398427605
96.52 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 85.74 0.17 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2110234538
96.55 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 85.91 0.17 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.728774172
96.57 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 86.09 0.17 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1803495003
96.60 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.37 0.00 99.33 0.00 86.26 0.17 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2526918225
96.62 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.41 0.04 99.33 0.00 86.38 0.12 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3978311665
96.64 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 86.50 0.12 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.936966014
96.65 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 86.61 0.12 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.976788352
96.67 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 86.73 0.12 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3748336135
96.69 0.02 99.14 0.00 96.28 0.00 100.00 0.00 96.79 0.00 98.41 0.00 99.33 0.00 86.85 0.12 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3792128656
96.70 0.02 99.18 0.04 96.28 0.00 100.00 0.00 96.79 0.00 98.48 0.07 99.33 0.00 86.85 0.00 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2430162781
96.71 0.01 99.20 0.02 96.31 0.03 100.00 0.00 96.79 0.00 98.52 0.04 99.33 0.00 86.85 0.00 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2799094751
96.72 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 86.90 0.06 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3991605781
96.73 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 86.96 0.06 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3476716571
96.74 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.02 0.06 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4255542626
96.75 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.08 0.06 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.337267298
96.75 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.14 0.06 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3436556253
96.76 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.19 0.06 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3220236486
96.77 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.25 0.06 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2859563644
96.78 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.31 0.06 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1436032156
96.79 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.37 0.06 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3297692780
96.80 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.43 0.06 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4238123471
96.80 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.49 0.06 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.646323702
96.81 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.54 0.06 /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4170615126
96.82 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.60 0.06 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1299492099
96.83 0.01 99.20 0.00 96.31 0.00 100.00 0.00 96.79 0.00 98.52 0.00 99.33 0.00 87.66 0.06 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1683089849
96.84 0.01 99.22 0.02 96.31 0.00 100.00 0.00 96.79 0.00 98.56 0.04 99.33 0.00 87.66 0.00 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2488805407
96.85 0.01 99.23 0.02 96.31 0.00 100.00 0.00 96.79 0.00 98.60 0.04 99.33 0.00 87.66 0.00 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3020590234


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2172928109
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.882804194
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2585555291
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3205285822
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3922078969
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.596398277
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2548800864
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4180114783
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3847819111
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2785864932
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4260337258
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2995420254
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1530150892
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2867860882
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.139767786
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2001860794
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1084802412
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1628388559
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3770529754
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.691470926
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.17465374
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2829772656
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1121255355
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3359177105
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2083974321
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.870585751
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.799386204
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3712349788
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2273309920
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3657558719
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3195135564
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2501255410
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3399810587
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1871248349
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4293138595
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3687346341
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.604629181
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3228498000
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2405836988
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.693584089
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3301649713
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.812729667
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3472040044
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3874805494
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3103171490
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1971795858
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4252507339
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.950395509
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1615144464
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2045629272
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2493848467
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1297275809
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.550639816
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2048919038
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3312128606
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3438684334
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2894434227
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1282631222
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1807206953
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1910907726
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.407164508
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2491137055
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3947138625
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.584914616
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3875938735
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2224159325
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2601409353
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4017060585
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1201605978
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.288953312
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2791530659
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1376752650
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3241137822
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2163567493
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2534166754
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3924660069
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.104723740
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1829320777
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1568821719
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2777280461
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/workspace/coverage/default/41.sysrst_ctrl_alert_test.1716351
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.547467733
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.1546744911
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1093853446
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3185312391
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.922546154
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3235330092
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1296635277
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.446673486
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3341147214
/workspace/coverage/default/41.sysrst_ctrl_smoke.3146989784
/workspace/coverage/default/41.sysrst_ctrl_stress_all.3616461777
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4170841121
/workspace/coverage/default/42.sysrst_ctrl_alert_test.158748978
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.801120926
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3249721221
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2520085333
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.542855154
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4017328258
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3203393201
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1890237085
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1910246578
/workspace/coverage/default/42.sysrst_ctrl_smoke.1795143155
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1465979230
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2157806919
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1522593634
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1823273596
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.439172432
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1883005291
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2886393628
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2468324868
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2606474305
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1608926915
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.572176530
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2534192204
/workspace/coverage/default/43.sysrst_ctrl_smoke.2588953104
/workspace/coverage/default/43.sysrst_ctrl_stress_all.630039024
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3914025042
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.621115208
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2339790304
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.381633866
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2197792013
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1229642647
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3760270782
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3085355299
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.791372376
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2851372250
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4106457002
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3416883148
/workspace/coverage/default/44.sysrst_ctrl_smoke.2040079105
/workspace/coverage/default/44.sysrst_ctrl_stress_all.814351538
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3184332981
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3517469363
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4242829930
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2609367025
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.582986997
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4227141834
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2154124068
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2035878381
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1858820434
/workspace/coverage/default/45.sysrst_ctrl_smoke.1634035644
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2198280155
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2193542825
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2315383941
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.113313658
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1067614681
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.350586918
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3271868920
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.866418375
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2439741254
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3048944612
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3683490684
/workspace/coverage/default/46.sysrst_ctrl_smoke.2053299922
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2594619946
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.549453880
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1342907323
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1704654711
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1189436974
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2320889307
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2609450652
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3676893449
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.458606948
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1420167005
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.3551450008
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3030146370
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3243452213
/workspace/coverage/default/47.sysrst_ctrl_smoke.2953424524
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2545774047
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.354961020
/workspace/coverage/default/48.sysrst_ctrl_alert_test.1882548390
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.655062031
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.4016836964
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1983426829
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1287159290
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1840444062
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3517205420
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1428178808
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4053052160
/workspace/coverage/default/48.sysrst_ctrl_smoke.2582083788
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1473102188
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.881748590
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3544434807
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1984162760
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1162679065
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.4036195446
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2485737412
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.528460958
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1645519732
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3823871754
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3247511079
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2252947857
/workspace/coverage/default/49.sysrst_ctrl_smoke.3377206288
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.263945891
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2634330440
/workspace/coverage/default/5.sysrst_ctrl_alert_test.4129683400
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2655037722
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3677460267
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2317835456
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2121534587
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.791537561
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1952347041
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.826994186
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1791712820
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3968162107
/workspace/coverage/default/5.sysrst_ctrl_smoke.1071871556
/workspace/coverage/default/5.sysrst_ctrl_stress_all.4163638475
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.443959962
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1366332708
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3646609305
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1217367484
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1542569625
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2403735040
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2266982815
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2277250017
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3617090477
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3905358567
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.435385815
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.1893786093
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4106106997
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3914381294
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3663314405
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2683795041
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3093191580
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.4183266119
/workspace/coverage/default/6.sysrst_ctrl_smoke.1691040620
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1963252619
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2652251384
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.777278098
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2350002059
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2762661827
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.222723458
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.276757616
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2281625759
/workspace/coverage/default/7.sysrst_ctrl_alert_test.107051509
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3849740983
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3309399393
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1796934601
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2237217716
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1157337519
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.67731778
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1445171327
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3626279125
/workspace/coverage/default/7.sysrst_ctrl_smoke.2598512773
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1991276272
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.360764541
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3657771504
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1438334052
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.406266007
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3194377393
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.781265062
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3935658752
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1819293505
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1430087255
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2725583937
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1067603748
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1265116061
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.211073038
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.307432929
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2369640698
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1162430502
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3412530617
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.669780188
/workspace/coverage/default/8.sysrst_ctrl_smoke.596210717
/workspace/coverage/default/8.sysrst_ctrl_stress_all.281348850
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3359184273
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1701780168
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2900436346
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.338064880
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.34539862
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1868396296
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1993471499
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2982844598
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1393656336
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3539532836
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2632431177
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3037700672
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2959952454
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1896379495
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.4122098887
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3743693297
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.4206781701
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2560566384
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3190186415
/workspace/coverage/default/9.sysrst_ctrl_smoke.578958372
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2862059844
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3697940343
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2973226051
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3252354599
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3075067370
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2104823822
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.367587421
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3632548127




Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3446431279 Aug 19 04:50:48 PM PDT 24 Aug 19 04:53:01 PM PDT 24 102837752740 ps
T4 /workspace/coverage/default/28.sysrst_ctrl_alert_test.2257035587 Aug 19 04:49:37 PM PDT 24 Aug 19 04:49:39 PM PDT 24 2031350176 ps
T5 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.958784639 Aug 19 04:49:20 PM PDT 24 Aug 19 04:49:25 PM PDT 24 2517929778 ps
T2 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2652251384 Aug 19 04:48:00 PM PDT 24 Aug 19 04:48:03 PM PDT 24 6449290236 ps
T13 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.439172432 Aug 19 04:50:22 PM PDT 24 Aug 19 04:51:15 PM PDT 24 280317283582 ps
T14 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2190500232 Aug 19 04:50:37 PM PDT 24 Aug 19 04:50:55 PM PDT 24 23115070871 ps
T15 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2878755154 Aug 19 04:48:51 PM PDT 24 Aug 19 04:48:57 PM PDT 24 7796459735 ps
T3 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1478246699 Aug 19 04:49:58 PM PDT 24 Aug 19 04:50:00 PM PDT 24 6160883950 ps
T6 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.922546154 Aug 19 04:50:24 PM PDT 24 Aug 19 04:50:26 PM PDT 24 3147208136 ps
T16 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3462404897 Aug 19 04:48:59 PM PDT 24 Aug 19 04:49:05 PM PDT 24 2467238090 ps
T21 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1330012413 Aug 19 04:50:05 PM PDT 24 Aug 19 04:50:06 PM PDT 24 2496034731 ps
T7 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3085355299 Aug 19 04:50:37 PM PDT 24 Aug 19 04:50:42 PM PDT 24 4725052479 ps
T50 /workspace/coverage/default/19.sysrst_ctrl_alert_test.2672932200 Aug 19 04:49:03 PM PDT 24 Aug 19 04:49:09 PM PDT 24 2018917898 ps
T51 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.572176530 Aug 19 04:50:23 PM PDT 24 Aug 19 04:50:25 PM PDT 24 2183818460 ps
T24 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1983426829 Aug 19 04:50:41 PM PDT 24 Aug 19 04:50:46 PM PDT 24 3018526212 ps
T52 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1428465366 Aug 19 04:48:49 PM PDT 24 Aug 19 04:48:59 PM PDT 24 3775282340 ps
T53 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3794859556 Aug 19 04:48:33 PM PDT 24 Aug 19 04:48:45 PM PDT 24 4394283606 ps
T22 /workspace/coverage/default/48.sysrst_ctrl_stress_all.1716527783 Aug 19 04:50:46 PM PDT 24 Aug 19 04:51:55 PM PDT 24 233519795151 ps
T40 /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2927342295 Aug 19 04:49:48 PM PDT 24 Aug 19 04:49:51 PM PDT 24 3227294780 ps
T101 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2035878381 Aug 19 04:50:40 PM PDT 24 Aug 19 04:50:46 PM PDT 24 2095733510 ps
T25 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.588713295 Aug 19 04:50:23 PM PDT 24 Aug 19 04:50:36 PM PDT 24 23584456182 ps
T102 /workspace/coverage/default/7.sysrst_ctrl_smoke.2598512773 Aug 19 04:48:06 PM PDT 24 Aug 19 04:48:09 PM PDT 24 2118454201 ps
T8 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1265116061 Aug 19 04:48:19 PM PDT 24 Aug 19 04:48:54 PM PDT 24 50398406946 ps
T9 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3170934204 Aug 19 04:48:05 PM PDT 24 Aug 19 04:49:20 PM PDT 24 109709652874 ps
T68 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.287133012 Aug 19 04:50:14 PM PDT 24 Aug 19 04:50:16 PM PDT 24 2630760614 ps
T62 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3652263003 Aug 19 04:48:43 PM PDT 24 Aug 19 04:48:50 PM PDT 24 2476440888 ps
T10 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3748336135 Aug 19 04:50:48 PM PDT 24 Aug 19 04:52:10 PM PDT 24 81982490403 ps
T63 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1608926915 Aug 19 04:50:23 PM PDT 24 Aug 19 04:50:26 PM PDT 24 2477083633 ps
T55 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2603880532 Aug 19 04:49:08 PM PDT 24 Aug 19 04:49:12 PM PDT 24 5223629594 ps
T11 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.728774172 Aug 19 04:50:12 PM PDT 24 Aug 19 04:51:49 PM PDT 24 145861343408 ps
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T190 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1358809908 Aug 19 04:48:28 PM PDT 24 Aug 19 04:48:36 PM PDT 24 2632877747 ps
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T382 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3000735650 Aug 19 04:49:56 PM PDT 24 Aug 19 04:49:58 PM PDT 24 2529486295 ps
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T278 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3876500365 Aug 19 04:49:40 PM PDT 24 Aug 19 04:49:53 PM PDT 24 9480955113 ps
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T61 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1522593634 Aug 19 04:50:21 PM PDT 24 Aug 19 04:50:28 PM PDT 24 3574527488 ps
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T240 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2403735040 Aug 19 04:50:46 PM PDT 24 Aug 19 04:53:07 PM PDT 24 52198148620 ps
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T273 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3676893449 Aug 19 04:50:38 PM PDT 24 Aug 19 04:50:40 PM PDT 24 2897373042 ps
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T408 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.381633866 Aug 19 04:50:23 PM PDT 24 Aug 19 04:50:34 PM PDT 24 3769697830 ps
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T448 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2003133832 Aug 19 04:48:15 PM PDT 24 Aug 19 04:48:18 PM PDT 24 2490024162 ps
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