Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered111.07
Success101798.93
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091391300
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001222337344245344300
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001222336775700400
tb.dut.tlul_assert_device.gen_device.contigMask_M 0012223373441016999900
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00122233734415528300
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001222336775725700
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012223373441171083300
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00122233734449606600
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012223373441171083300
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00122233734449606600
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00122233734449606600
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00122233734449606600
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001222336775432200
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001222336775427000
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091391300
tb.dut.u_reg.en2addrHit 00122233677524128500
tb.dut.u_reg.reAfterRv 00122233677524128400
tb.dut.u_reg.rePulse 00122233677513038300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 00122233677594734500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001222336775112200
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775112200
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703112200
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703105600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775113400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 00122233677586227900
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 00122233677599500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00122233677599500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00799970399500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 00799970392700
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775100600
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091391300
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001222336775146306600
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001222336775169600
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775169600
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703169600
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703163100
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775171000
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001222336775133508000
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001222336775160400
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775160400
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703160400
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703153800
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775161400
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001222336775138246500
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001222336775165100
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775165100
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703165100
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703158200
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775166100
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001222336775137526400
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001222336775166000
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775166000
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703166000
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703160100
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775167100
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001222336775139171800
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001222336775165500
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775165500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703165500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703159100
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775166700
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001222336775134663700
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001222336775162900
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775162900
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703162900
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703156500
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775164100
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001222336775134974700
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001222336775161500
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775161500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703161500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703155200
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775162700
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001222336775134708500
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001222336775163600
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775163600
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703163600
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703157000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775164900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001222336775100454600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001222336775114200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775114200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703114200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703107800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775115300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001222336775102218500
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001222336775114800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775114800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703114800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703108400
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775116200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 00122233677595797500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001222336775111800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775111800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703111800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703105200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775112900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 00122233677598762400
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001222336775113100
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775113100
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703113100
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703106500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775114200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001222336775640310500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001222336775689200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775689200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703689200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703682100
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775690100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001222336775631470300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001222336775683200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775683200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703683200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703676300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775684400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001222336775622823900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001222336775681000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775681000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703681000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703674100
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775682100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001222336775618720400
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001222336775677800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775677800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703677800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703670800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775679000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001222336775687197000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001222336775741000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775741000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703741000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007999703734200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001222336775742200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001222336775672135000
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 007999703734134200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001222336775732400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001222336775122193308900
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001222336775732400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007999703732400
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