Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h.DetectStDropOut_A	0	0	7758203	0	0	0
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present.DetectStDropOut_A	0	0	7758203	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.BatOEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.BatOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.ECRSTOEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.ECRSTOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.FlashWpOEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.FlashWpOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	1156367120	70	0	0
tb.dut.IntrEventOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.Key0OEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.Key0OKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.Key1OEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.Key1OKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.Key2OEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.Key2OKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.OTRstOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.OTWkOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.PwrbOEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.PwrbOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.TlOAReadyKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.TlODValidKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.Z3WakeupOEnIsOne_A	0	0	1156367120	1156005809	0	0
tb.dut.Z3WwakupOKnown_A	0	0	1156367120	1156005809	0	0
tb.dut.sysrst_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	1222336775	13114	0	0
tb.dut.sysrst_ctrl_csr_assert.auto_block_debounce_ctl_rd_A	0	0	1222336775	1451	0	0
tb.dut.sysrst_ctrl_csr_assert.auto_block_out_ctl_rd_A	0	0	1222336775	1920	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_0_rd_A	0	0	1222336775	3045	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_1_rd_A	0	0	1222336775	3136	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_2_rd_A	0	0	1222336775	3142	0	0
tb.dut.sysrst_ctrl_csr_assert.com_det_ctl_3_rd_A	0	0	1222336775	3227	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_0_rd_A	0	0	1222336775	3299	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_1_rd_A	0	0	1222336775	3555	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_2_rd_A	0	0	1222336775	3642	0	0
tb.dut.sysrst_ctrl_csr_assert.com_out_ctl_3_rd_A	0	0	1222336775	3757	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_0_rd_A	0	0	1222336775	1162	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_1_rd_A	0	0	1222336775	1043	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_2_rd_A	0	0	1222336775	965	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_det_ctl_3_rd_A	0	0	1222336775	965	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_0_rd_A	0	0	1222336775	3706	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_1_rd_A	0	0	1222336775	3801	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_2_rd_A	0	0	1222336775	3484	0	0
tb.dut.sysrst_ctrl_csr_assert.com_pre_sel_ctl_3_rd_A	0	0	1222336775	3745	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_0_rd_A	0	0	1222336775	3714	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_1_rd_A	0	0	1222336775	3672	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_2_rd_A	0	0	1222336775	3574	0	0
tb.dut.sysrst_ctrl_csr_assert.com_sel_ctl_3_rd_A	0	0	1222336775	3969	0	0
tb.dut.sysrst_ctrl_csr_assert.ec_rst_ctl_rd_A	0	0	1222336775	1726	0	0
tb.dut.sysrst_ctrl_csr_assert.intr_enable_rd_A	0	0	1222336775	1515	0	0
tb.dut.sysrst_ctrl_csr_assert.key_intr_ctl_rd_A	0	0	1222336775	3103	0	0
tb.dut.sysrst_ctrl_csr_assert.key_intr_debounce_ctl_rd_A	0	0	1222336775	1040	0	0
tb.dut.sysrst_ctrl_csr_assert.key_invert_ctl_rd_A	0	0	1222336775	4347	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_allowed_ctl_rd_A	0	0	1222336775	5108	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_out_ctl_rd_A	0	0	1222336775	3697	0	0
tb.dut.sysrst_ctrl_csr_assert.pin_out_value_rd_A	0	0	1222336775	4104	0	0
tb.dut.sysrst_ctrl_csr_assert.regwen_rd_A	0	0	1222336775	1139	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_ac_debounce_ctl_rd_A	0	0	1222336775	1177	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_ctl_rd_A	0	0	1222336775	1067	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_lid_debounce_ctl_rd_A	0	0	1222336775	1153	0	0
tb.dut.sysrst_ctrl_csr_assert.ulp_pwrb_debounce_ctl_rd_A	0	0	1222336775	1177	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	1222336775	11710727	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	1222336775	1221933089	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	1222336775	1221933089	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	1222336775	495975	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	1222336775	1221933089	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	1222336775	1221933089	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	913	913	0	0
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