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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[0]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[1]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 44 1 T39 1 T40 4 T261 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 23 1 T44 1 T42 1 T259 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 46 1 T57 1 T40 1 T42 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 23 1 T56 1 T44 2 T259 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 52 1 T12 1 T39 3 T40 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 16 1 T41 1 T259 1 T155 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 39 1 T43 1 T41 1 T39 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 22 1 T44 3 T279 1 T259 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 34 1 T12 1 T39 1 T40 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 25 1 T41 1 T56 2 T44 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 39 1 T12 1 T87 1 T261 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 18 1 T41 1 T44 3 T42 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 48 1 T40 1 T240 1 T249 4
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 31 1 T41 2 T56 1 T279 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 43 1 T40 1 T261 1 T105 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 22 1 T44 1 T42 1 T259 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 53 1 T12 3 T30 1 T43 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 20 1 T44 3 T104 1 T107 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 39 1 T12 2 T43 1 T89 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 19 1 T56 1 T42 1 T104 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 42 1 T12 2 T43 2 T257 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 31 1 T56 3 T44 3 T104 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 52 1 T12 1 T257 10 T105 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 33 1 T41 1 T56 1 T279 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 34 1 T12 1 T87 1 T39 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 20 1 T41 1 T44 1 T39 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 45 1 T43 1 T87 1 T261 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 29 1 T41 1 T44 1 T279 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 42 1 T12 1 T261 1 T105 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 43 1 T41 1 T56 2 T42 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 106 1 T43 2 T261 1 T105 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 76 1 T56 2 T89 9 T259 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 34 1 T30 1 T43 1 T261 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T41 1 T42 2 T104 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 43 1 T12 1 T30 1 T43 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 36 1 T41 1 T56 1 T44 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 32 1 T12 1 T43 1 T87 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 30 1 T41 1 T56 1 T44 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 43 1 T44 1 T240 1 T274 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 31 1 T41 1 T44 1 T39 6
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 34 1 T43 3 T40 1 T105 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 28 1 T44 1 T279 1 T42 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 37 1 T43 1 T87 1 T261 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 36 1 T41 1 T44 2 T87 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 48 1 T43 1 T40 1 T261 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 33 1 T41 1 T56 1 T104 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 54 1 T56 1 T40 7 T105 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 42 1 T41 1 T44 1 T40 6
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 41 1 T12 1 T43 1 T240 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 23 1 T41 1 T42 2 T104 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 61 1 T12 1 T43 2 T57 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 26 1 T87 1 T104 1 T259 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 37 1 T279 1 T240 2 T106 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 29 1 T56 2 T44 1 T279 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 46 1 T12 2 T57 1 T261 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 59 1 T41 1 T57 9 T44 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 33 1 T44 1 T240 2 T105 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 39 1 T42 1 T259 2 T260 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 32 1 T261 1 T240 1 T106 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 59 1 T30 9 T56 1 T44 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 75 1 T12 1 T269 2 T274 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 41 1 T41 1 T44 3 T42 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 133 1 T12 1 T43 1 T41 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 87 1 T41 10 T56 8 T44 3
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1 1 T362 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 23 1 T42 3 T259 4 T260 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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