| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.68 | 99.10 | 96.56 | 100.00 | 92.95 | 98.56 | 98.94 | 83.65 |
| T34 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1476710538 | Aug 21 08:48:45 AM UTC 24 | Aug 21 08:48:49 AM UTC 24 | 2090114914 ps | ||
| T35 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2307981536 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:49 AM UTC 24 | 4069244987 ps | ||
| T800 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3460651062 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:49 AM UTC 24 | 2031739721 ps | ||
| T36 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3305791392 | Aug 21 08:48:44 AM UTC 24 | Aug 21 08:48:50 AM UTC 24 | 2690104407 ps | ||
| T284 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2100824370 | Aug 21 08:48:44 AM UTC 24 | Aug 21 08:48:50 AM UTC 24 | 2153160433 ps | ||
| T37 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3806339430 | Aug 21 08:48:44 AM UTC 24 | Aug 21 08:48:51 AM UTC 24 | 4058448045 ps | ||
| T285 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3574317922 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:53 AM UTC 24 | 2268711274 ps | ||
| T293 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.467388489 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:54 AM UTC 24 | 3164240218 ps | ||
| T21 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3843176869 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:54 AM UTC 24 | 2061735124 ps | ||
| T300 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.92103531 | Aug 21 08:48:50 AM UTC 24 | Aug 21 08:48:55 AM UTC 24 | 2093760064 ps | ||
| T294 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.413861511 | Aug 21 08:48:50 AM UTC 24 | Aug 21 08:48:55 AM UTC 24 | 2581857705 ps | ||
| T286 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1277540171 | Aug 21 08:48:50 AM UTC 24 | Aug 21 08:48:56 AM UTC 24 | 2423488386 ps | ||
| T295 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4118872899 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:56 AM UTC 24 | 2082334343 ps | ||
| T297 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1530480944 | Aug 21 08:48:45 AM UTC 24 | Aug 21 08:48:56 AM UTC 24 | 2030320360 ps | ||
| T801 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1816982684 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:48:58 AM UTC 24 | 2018161833 ps | ||
| T334 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3473117411 | Aug 21 08:48:51 AM UTC 24 | Aug 21 08:48:58 AM UTC 24 | 4026841268 ps | ||
| T335 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.128912845 | Aug 21 08:48:52 AM UTC 24 | Aug 21 08:48:59 AM UTC 24 | 2031372721 ps | ||
| T802 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1299491055 | Aug 21 08:48:51 AM UTC 24 | Aug 21 08:48:59 AM UTC 24 | 2011802607 ps | ||
| T347 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.279603214 | Aug 21 08:48:48 AM UTC 24 | Aug 21 08:48:59 AM UTC 24 | 2036782142 ps | ||
| T395 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3481489427 | Aug 21 08:48:56 AM UTC 24 | Aug 21 08:49:00 AM UTC 24 | 2139727735 ps | ||
| T298 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1275998626 | Aug 21 08:48:56 AM UTC 24 | Aug 21 08:49:02 AM UTC 24 | 2160928419 ps | ||
| T803 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1272036262 | Aug 21 08:48:57 AM UTC 24 | Aug 21 08:49:03 AM UTC 24 | 6110379253 ps | ||
| T348 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2927637857 | Aug 21 08:48:58 AM UTC 24 | Aug 21 08:49:03 AM UTC 24 | 2050626120 ps | ||
| T804 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3401348994 | Aug 21 08:48:57 AM UTC 24 | Aug 21 08:49:04 AM UTC 24 | 2021638513 ps | ||
| T22 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2876967028 | Aug 21 08:48:56 AM UTC 24 | Aug 21 08:49:05 AM UTC 24 | 8772945136 ps | ||
| T336 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2269241694 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:49:05 AM UTC 24 | 6021347051 ps | ||
| T337 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2714491949 | Aug 21 08:48:49 AM UTC 24 | Aug 21 08:49:07 AM UTC 24 | 31354429610 ps | ||
| T23 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.327163667 | Aug 21 08:49:00 AM UTC 24 | Aug 21 08:49:08 AM UTC 24 | 4575631840 ps | ||
| T24 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3673448972 | Aug 21 08:48:50 AM UTC 24 | Aug 21 08:49:08 AM UTC 24 | 5142400936 ps | ||
| T396 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3453383036 | Aug 21 08:49:05 AM UTC 24 | Aug 21 08:49:10 AM UTC 24 | 2181990651 ps | ||
| T338 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3364271618 | Aug 21 08:48:55 AM UTC 24 | Aug 21 08:49:10 AM UTC 24 | 3233265160 ps | ||
| T339 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3262678446 | Aug 21 08:49:04 AM UTC 24 | Aug 21 08:49:10 AM UTC 24 | 2062422547 ps | ||
| T805 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3457689468 | Aug 21 08:49:00 AM UTC 24 | Aug 21 08:49:10 AM UTC 24 | 2505882140 ps | ||
| T806 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2821803491 | Aug 21 08:49:01 AM UTC 24 | Aug 21 08:49:12 AM UTC 24 | 2037200266 ps | ||
| T299 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1849699588 | Aug 21 08:49:01 AM UTC 24 | Aug 21 08:49:12 AM UTC 24 | 2166048453 ps | ||
| T301 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1849140696 | Aug 21 08:49:07 AM UTC 24 | Aug 21 08:49:12 AM UTC 24 | 2558095616 ps | ||
| T349 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.450000524 | Aug 21 08:48:45 AM UTC 24 | Aug 21 08:49:13 AM UTC 24 | 7554646106 ps | ||
| T807 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2166305687 | Aug 21 08:49:03 AM UTC 24 | Aug 21 08:49:13 AM UTC 24 | 2016241469 ps | ||
| T398 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1631793577 | Aug 21 08:49:09 AM UTC 24 | Aug 21 08:49:14 AM UTC 24 | 2134370797 ps | ||
| T808 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1774170075 | Aug 21 08:49:08 AM UTC 24 | Aug 21 08:49:15 AM UTC 24 | 2052120509 ps | ||
| T809 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4250508698 | Aug 21 08:49:05 AM UTC 24 | Aug 21 08:49:15 AM UTC 24 | 7799449359 ps | ||
| T810 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2030072290 | Aug 21 08:49:08 AM UTC 24 | Aug 21 08:49:17 AM UTC 24 | 2013061910 ps | ||
| T811 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1868902688 | Aug 21 08:49:14 AM UTC 24 | Aug 21 08:49:18 AM UTC 24 | 2210424366 ps | ||
| T812 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3483447798 | Aug 21 08:49:14 AM UTC 24 | Aug 21 08:49:19 AM UTC 24 | 2036895260 ps | ||
| T813 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2088357807 | Aug 21 08:49:09 AM UTC 24 | Aug 21 08:49:19 AM UTC 24 | 4755399602 ps | ||
| T814 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1415071930 | Aug 21 08:49:11 AM UTC 24 | Aug 21 08:49:19 AM UTC 24 | 2018611308 ps | ||
| T815 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2052470219 | Aug 21 08:49:10 AM UTC 24 | Aug 21 08:49:23 AM UTC 24 | 2043916247 ps | ||
| T816 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3250777120 | Aug 21 08:49:20 AM UTC 24 | Aug 21 08:49:23 AM UTC 24 | 2050406841 ps | ||
| T817 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.801804203 | Aug 21 08:49:11 AM UTC 24 | Aug 21 08:49:23 AM UTC 24 | 2056566057 ps | ||
| T400 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2217761490 | Aug 21 08:49:15 AM UTC 24 | Aug 21 08:49:24 AM UTC 24 | 2033839686 ps | ||
| T818 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1196147220 | Aug 21 08:49:16 AM UTC 24 | Aug 21 08:49:24 AM UTC 24 | 2068871777 ps | ||
| T819 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4044235176 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:49:25 AM UTC 24 | 5394727409 ps | ||
| T340 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2045104070 | Aug 21 08:49:20 AM UTC 24 | Aug 21 08:49:25 AM UTC 24 | 2040302489 ps | ||
| T399 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.446285609 | Aug 21 08:49:00 AM UTC 24 | Aug 21 08:49:25 AM UTC 24 | 39440850785 ps | ||
| T397 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3433787278 | Aug 21 08:49:14 AM UTC 24 | Aug 21 08:49:26 AM UTC 24 | 2063885739 ps | ||
| T820 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3572087244 | Aug 21 08:49:16 AM UTC 24 | Aug 21 08:49:26 AM UTC 24 | 4723761756 ps | ||
| T821 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1958606047 | Aug 21 08:49:13 AM UTC 24 | Aug 21 08:49:27 AM UTC 24 | 4981032476 ps | ||
| T822 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3214585407 | Aug 21 08:49:18 AM UTC 24 | Aug 21 08:49:28 AM UTC 24 | 2226662635 ps | ||
| T823 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1965749038 | Aug 21 08:49:25 AM UTC 24 | Aug 21 08:49:29 AM UTC 24 | 2063637868 ps | ||
| T824 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2523078833 | Aug 21 08:49:24 AM UTC 24 | Aug 21 08:49:29 AM UTC 24 | 2141872381 ps | ||
| T825 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3446952491 | Aug 21 08:49:25 AM UTC 24 | Aug 21 08:49:29 AM UTC 24 | 2298272587 ps | ||
| T826 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3621867500 | Aug 21 08:49:25 AM UTC 24 | Aug 21 08:49:30 AM UTC 24 | 2029409901 ps | ||
| T401 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2856833663 | Aug 21 08:49:24 AM UTC 24 | Aug 21 08:49:31 AM UTC 24 | 2085878879 ps | ||
| T827 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3828312259 | Aug 21 08:49:26 AM UTC 24 | Aug 21 08:49:32 AM UTC 24 | 2016770373 ps | ||
| T344 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1169348538 | Aug 21 08:49:28 AM UTC 24 | Aug 21 08:49:32 AM UTC 24 | 2074364650 ps | ||
| T828 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1733502683 | Aug 21 08:49:29 AM UTC 24 | Aug 21 08:49:33 AM UTC 24 | 2123499457 ps | ||
| T829 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4006682038 | Aug 21 08:49:29 AM UTC 24 | Aug 21 08:49:34 AM UTC 24 | 2065656071 ps | ||
| T830 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1414862413 | Aug 21 08:49:21 AM UTC 24 | Aug 21 08:49:35 AM UTC 24 | 9175793466 ps | ||
| T287 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1185726457 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:49:35 AM UTC 24 | 42818203562 ps | ||
| T831 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1529677702 | Aug 21 08:49:25 AM UTC 24 | Aug 21 08:49:36 AM UTC 24 | 7723869010 ps | ||
| T832 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2574515531 | Aug 21 08:48:55 AM UTC 24 | Aug 21 08:49:36 AM UTC 24 | 39999863563 ps | ||
| T833 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4204001918 | Aug 21 08:49:30 AM UTC 24 | Aug 21 08:49:36 AM UTC 24 | 2015719630 ps | ||
| T341 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4121630125 | Aug 21 08:48:46 AM UTC 24 | Aug 21 08:49:38 AM UTC 24 | 38116611639 ps | ||
| T345 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1784972495 | Aug 21 08:49:30 AM UTC 24 | Aug 21 08:49:38 AM UTC 24 | 2051148590 ps | ||
| T834 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2559398840 | Aug 21 08:49:36 AM UTC 24 | Aug 21 08:49:40 AM UTC 24 | 2098894855 ps | ||
| T835 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3467619572 | Aug 21 08:49:25 AM UTC 24 | Aug 21 08:49:41 AM UTC 24 | 2111883008 ps | ||
| T836 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2403057235 | Aug 21 08:49:37 AM UTC 24 | Aug 21 08:49:42 AM UTC 24 | 2154463085 ps | ||
| T288 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.847014892 | Aug 21 08:49:24 AM UTC 24 | Aug 21 08:49:42 AM UTC 24 | 22701045221 ps | ||
| T837 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3122175270 | Aug 21 08:49:36 AM UTC 24 | Aug 21 08:49:43 AM UTC 24 | 2030806873 ps | ||
| T289 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1199266263 | Aug 21 08:48:56 AM UTC 24 | Aug 21 08:49:43 AM UTC 24 | 42527099723 ps | ||
| T838 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.904279214 | Aug 21 08:49:31 AM UTC 24 | Aug 21 08:49:43 AM UTC 24 | 2056966184 ps | ||
| T839 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3978826916 | Aug 21 08:49:34 AM UTC 24 | Aug 21 08:49:44 AM UTC 24 | 2008526107 ps | ||
| T840 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1120590788 | Aug 21 08:49:34 AM UTC 24 | Aug 21 08:49:44 AM UTC 24 | 2085016894 ps | ||
| T841 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4165475391 | Aug 21 08:49:39 AM UTC 24 | Aug 21 08:49:45 AM UTC 24 | 2037764198 ps | ||
| T842 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.885068561 | Aug 21 08:49:31 AM UTC 24 | Aug 21 08:49:45 AM UTC 24 | 10292986533 ps | ||
| T843 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.231243259 | Aug 21 08:49:37 AM UTC 24 | Aug 21 08:49:47 AM UTC 24 | 2014404518 ps | ||
| T363 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3022631257 | Aug 21 08:48:45 AM UTC 24 | Aug 21 08:49:47 AM UTC 24 | 22188192918 ps | ||
| T844 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1028058719 | Aug 21 08:49:42 AM UTC 24 | Aug 21 08:49:48 AM UTC 24 | 2547285257 ps | ||
| T845 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3353569831 | Aug 21 08:49:45 AM UTC 24 | Aug 21 08:49:49 AM UTC 24 | 2185991751 ps | ||
| T846 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3394611130 | Aug 21 08:49:45 AM UTC 24 | Aug 21 08:49:50 AM UTC 24 | 2020470868 ps | ||
| T847 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3728487347 | Aug 21 08:49:41 AM UTC 24 | Aug 21 08:49:51 AM UTC 24 | 2061590044 ps | ||
| T848 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2385672973 | Aug 21 08:49:44 AM UTC 24 | Aug 21 08:49:52 AM UTC 24 | 2012504337 ps | ||
| T364 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1950083201 | Aug 21 08:49:43 AM UTC 24 | Aug 21 08:49:52 AM UTC 24 | 22833951910 ps | ||
| T849 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.694559891 | Aug 21 08:49:48 AM UTC 24 | Aug 21 08:49:52 AM UTC 24 | 2115714614 ps | ||
| T342 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3289770798 | Aug 21 08:49:46 AM UTC 24 | Aug 21 08:49:53 AM UTC 24 | 2040384919 ps | ||
| T850 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1470006399 | Aug 21 08:49:45 AM UTC 24 | Aug 21 08:49:54 AM UTC 24 | 23159896871 ps | ||
| T851 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.448976266 | Aug 21 08:49:44 AM UTC 24 | Aug 21 08:49:54 AM UTC 24 | 2032188993 ps | ||
| T852 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2855771897 | Aug 21 08:49:44 AM UTC 24 | Aug 21 08:49:54 AM UTC 24 | 4697340286 ps | ||
| T853 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.964746538 | Aug 21 08:49:52 AM UTC 24 | Aug 21 08:49:55 AM UTC 24 | 2279733646 ps | ||
| T854 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.261432688 | Aug 21 08:49:45 AM UTC 24 | Aug 21 08:49:55 AM UTC 24 | 2082624545 ps | ||
| T855 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.211279231 | Aug 21 08:49:49 AM UTC 24 | Aug 21 08:49:55 AM UTC 24 | 2086924416 ps | ||
| T856 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4183041022 | Aug 21 08:49:29 AM UTC 24 | Aug 21 08:49:57 AM UTC 24 | 5319670977 ps | ||
| T365 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1403258335 | Aug 21 08:49:34 AM UTC 24 | Aug 21 08:49:57 AM UTC 24 | 22266791975 ps | ||
| T857 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2197602173 | Aug 21 08:49:53 AM UTC 24 | Aug 21 08:49:59 AM UTC 24 | 2279947273 ps | ||
| T858 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1142339324 | Aug 21 08:49:55 AM UTC 24 | Aug 21 08:50:00 AM UTC 24 | 2036522705 ps | ||
| T343 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1562491911 | Aug 21 08:49:57 AM UTC 24 | Aug 21 08:50:00 AM UTC 24 | 2558575473 ps | ||
| T859 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3016382137 | Aug 21 08:49:36 AM UTC 24 | Aug 21 08:50:00 AM UTC 24 | 4113467294 ps | ||
| T346 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.850717082 | Aug 21 08:49:52 AM UTC 24 | Aug 21 08:50:02 AM UTC 24 | 2052706136 ps | ||
| T860 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.477154109 | Aug 21 08:49:51 AM UTC 24 | Aug 21 08:50:02 AM UTC 24 | 2011617368 ps | ||
| T861 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3175207924 | Aug 21 08:49:56 AM UTC 24 | Aug 21 08:50:03 AM UTC 24 | 2090033382 ps | ||
| T862 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.92121176 | Aug 21 08:49:39 AM UTC 24 | Aug 21 08:50:03 AM UTC 24 | 5331691712 ps | ||
| T863 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3761792225 | Aug 21 08:49:57 AM UTC 24 | Aug 21 08:50:03 AM UTC 24 | 4866209447 ps | ||
| T864 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.865638982 | Aug 21 08:50:00 AM UTC 24 | Aug 21 08:50:05 AM UTC 24 | 2148617281 ps | ||
| T366 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3646510626 | Aug 21 08:49:03 AM UTC 24 | Aug 21 08:50:05 AM UTC 24 | 22227762175 ps | ||
| T865 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2091786382 | Aug 21 08:49:56 AM UTC 24 | Aug 21 08:50:06 AM UTC 24 | 2014391342 ps | ||
| T866 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.182351579 | Aug 21 08:48:44 AM UTC 24 | Aug 21 08:50:07 AM UTC 24 | 42382565783 ps | ||
| T867 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1743682178 | Aug 21 08:50:12 AM UTC 24 | Aug 21 08:50:17 AM UTC 24 | 2023750418 ps | ||
| T868 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.153807898 | Aug 21 08:50:03 AM UTC 24 | Aug 21 08:50:08 AM UTC 24 | 2031900592 ps | ||
| T869 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3082293906 | Aug 21 08:50:04 AM UTC 24 | Aug 21 08:50:08 AM UTC 24 | 2093492079 ps | ||
| T870 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2706023104 | Aug 21 08:49:55 AM UTC 24 | Aug 21 08:50:08 AM UTC 24 | 2045205139 ps | ||
| T871 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.998085509 | Aug 21 08:50:04 AM UTC 24 | Aug 21 08:50:08 AM UTC 24 | 2037818248 ps | ||
| T872 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1568688000 | Aug 21 08:50:01 AM UTC 24 | Aug 21 08:50:09 AM UTC 24 | 2014676993 ps | ||
| T873 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.500032837 | Aug 21 08:50:04 AM UTC 24 | Aug 21 08:50:09 AM UTC 24 | 2036347818 ps | ||
| T874 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.861815924 | Aug 21 08:50:06 AM UTC 24 | Aug 21 08:50:09 AM UTC 24 | 2055311005 ps | ||
| T875 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.365806085 | Aug 21 08:50:03 AM UTC 24 | Aug 21 08:50:10 AM UTC 24 | 2025325422 ps | ||
| T876 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.4224470001 | Aug 21 08:49:08 AM UTC 24 | Aug 21 08:50:10 AM UTC 24 | 22204093303 ps | ||
| T877 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3197047827 | Aug 21 08:49:56 AM UTC 24 | Aug 21 08:50:10 AM UTC 24 | 2092269479 ps | ||
| T878 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3318959868 | Aug 21 08:49:48 AM UTC 24 | Aug 21 08:50:10 AM UTC 24 | 4702937704 ps | ||
| T879 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3023280223 | Aug 21 08:50:03 AM UTC 24 | Aug 21 08:50:10 AM UTC 24 | 2017436392 ps | ||
| T880 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1407851730 | Aug 21 08:50:01 AM UTC 24 | Aug 21 08:50:10 AM UTC 24 | 2013242562 ps | ||
| T881 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.4022892982 | Aug 21 08:49:52 AM UTC 24 | Aug 21 08:50:11 AM UTC 24 | 4710344778 ps | ||
| T882 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.257715098 | Aug 21 08:50:08 AM UTC 24 | Aug 21 08:50:11 AM UTC 24 | 2037723392 ps | ||
| T883 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1989948523 | Aug 21 08:49:30 AM UTC 24 | Aug 21 08:50:11 AM UTC 24 | 22323843824 ps | ||
| T884 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.978946359 | Aug 21 08:50:02 AM UTC 24 | Aug 21 08:50:11 AM UTC 24 | 2015875358 ps | ||
| T885 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.431763506 | Aug 21 08:50:09 AM UTC 24 | Aug 21 08:50:12 AM UTC 24 | 2065981203 ps | ||
| T886 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.971336811 | Aug 21 08:50:09 AM UTC 24 | Aug 21 08:50:13 AM UTC 24 | 2038262564 ps | ||
| T887 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1278121308 | Aug 21 08:50:08 AM UTC 24 | Aug 21 08:50:13 AM UTC 24 | 2024271400 ps | ||
| T888 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2789749702 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:13 AM UTC 24 | 2101357837 ps | ||
| T889 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3580889515 | Aug 21 08:50:09 AM UTC 24 | Aug 21 08:50:13 AM UTC 24 | 2047009430 ps | ||
| T890 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.29866510 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:14 AM UTC 24 | 2039621618 ps | ||
| T891 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3981526361 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:14 AM UTC 24 | 2069154336 ps | ||
| T892 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3428361698 | Aug 21 08:50:07 AM UTC 24 | Aug 21 08:50:14 AM UTC 24 | 2012643550 ps | ||
| T893 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3949838420 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:14 AM UTC 24 | 2026380368 ps | ||
| T894 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.4212418660 | Aug 21 08:50:09 AM UTC 24 | Aug 21 08:50:14 AM UTC 24 | 2023662157 ps | ||
| T895 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1402264285 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:14 AM UTC 24 | 2032650225 ps | ||
| T896 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4278226804 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:15 AM UTC 24 | 2056343962 ps | ||
| T897 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3035755227 | Aug 21 08:50:12 AM UTC 24 | Aug 21 08:50:16 AM UTC 24 | 2035688343 ps | ||
| T898 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1391056928 | Aug 21 08:48:50 AM UTC 24 | Aug 21 08:50:16 AM UTC 24 | 22219527270 ps | ||
| T899 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.971680009 | Aug 21 08:50:12 AM UTC 24 | Aug 21 08:50:17 AM UTC 24 | 2039197630 ps | ||
| T900 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2856756007 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:17 AM UTC 24 | 2020698969 ps | ||
| T901 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1442265944 | Aug 21 08:50:09 AM UTC 24 | Aug 21 08:50:17 AM UTC 24 | 2013488022 ps | ||
| T902 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.831852349 | Aug 21 08:50:09 AM UTC 24 | Aug 21 08:50:18 AM UTC 24 | 2011725414 ps | ||
| T903 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2231623555 | Aug 21 08:50:11 AM UTC 24 | Aug 21 08:50:19 AM UTC 24 | 2020214284 ps | ||
| T904 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1988248978 | Aug 21 08:49:37 AM UTC 24 | Aug 21 08:50:27 AM UTC 24 | 42631148645 ps | ||
| T905 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2569550901 | Aug 21 08:49:26 AM UTC 24 | Aug 21 08:50:28 AM UTC 24 | 22243048977 ps | ||
| T906 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2776342859 | Aug 21 08:49:55 AM UTC 24 | Aug 21 08:50:29 AM UTC 24 | 7401854415 ps | ||
| T907 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3363060080 | Aug 21 08:48:44 AM UTC 24 | Aug 21 08:50:30 AM UTC 24 | 39897664721 ps | ||
| T908 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.493618581 | Aug 21 08:49:56 AM UTC 24 | Aug 21 08:50:31 AM UTC 24 | 42492402190 ps | ||
| T909 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2021827455 | Aug 21 08:49:50 AM UTC 24 | Aug 21 08:50:57 AM UTC 24 | 22210838294 ps | ||
| T910 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.89371676 | Aug 21 08:49:14 AM UTC 24 | Aug 21 08:51:10 AM UTC 24 | 42391571227 ps | ||
| T911 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3876256440 | Aug 21 08:49:11 AM UTC 24 | Aug 21 08:51:20 AM UTC 24 | 42417985760 ps | ||
| T912 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3757056045 | Aug 21 08:49:18 AM UTC 24 | Aug 21 08:51:47 AM UTC 24 | 42463526661 ps | ||
| T913 | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3005903230 | Aug 21 08:49:53 AM UTC 24 | Aug 21 08:52:08 AM UTC 24 | 42485767230 ps |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.626134856 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 12449174942 ps |
| CPU time | 6.27 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:39 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62613 4856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.sysrst_ctrl_ultra_low_pwr.626134856 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1744520400 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 34936853608 ps |
| CPU time | 126 seconds |
| Started | Aug 21 07:26:55 AM UTC 24 |
| Finished | Aug 21 07:29:04 AM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1744520400 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disa ble.1744520400 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.767306026 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 41196599571 ps |
| CPU time | 28.68 seconds |
| Started | Aug 21 07:28:52 AM UTC 24 |
| Finished | Aug 21 07:29:23 AM UTC 24 |
| Peak memory | 226680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767306026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.767306026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.193156349 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 36575346156 ps |
| CPU time | 40.42 seconds |
| Started | Aug 21 07:26:35 AM UTC 24 |
| Finished | Aug 21 07:27:17 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=193156349 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.193156349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3148859332 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2532940809 ps |
| CPU time | 4.57 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:37 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3148859332 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_te st.3148859332 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3853188032 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 176158839346 ps |
| CPU time | 68.06 seconds |
| Started | Aug 21 07:28:20 AM UTC 24 |
| Finished | Aug 21 07:29:29 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38531880 32 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4. sysrst_ctrl_stress_all.3853188032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1963769124 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 39160842882 ps |
| CPU time | 66.03 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:27:39 AM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19637 69124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 0.sysrst_ctrl_combo_detect.1963769124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.333413606 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 6544178123 ps |
| CPU time | 8.07 seconds |
| Started | Aug 21 07:26:58 AM UTC 24 |
| Finished | Aug 21 07:27:07 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33341360 6 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.s ysrst_ctrl_stress_all.333413606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3843176869 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2061735124 ps |
| CPU time | 7.22 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:54 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3843176869 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sys rst_ctrl_csr_rw.3843176869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.502047442 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 399955450720 ps |
| CPU time | 182.26 seconds |
| Started | Aug 21 07:36:12 AM UTC 24 |
| Finished | Aug 21 07:39:17 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=50204744 2 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30. sysrst_ctrl_stress_all.502047442 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3554261745 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 130068589451 ps |
| CPU time | 233.78 seconds |
| Started | Aug 21 07:26:35 AM UTC 24 |
| Finished | Aug 21 07:30:32 AM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554261745 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_c ombo_detect_with_pre_cond.3554261745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.4015729012 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 30885724261 ps |
| CPU time | 106.49 seconds |
| Started | Aug 21 07:27:22 AM UTC 24 |
| Finished | Aug 21 07:29:11 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40157 29012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 2.sysrst_ctrl_combo_detect.4015729012 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3529805453 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 22014402776 ps |
| CPU time | 50.32 seconds |
| Started | Aug 21 07:26:36 AM UTC 24 |
| Finished | Aug 21 07:27:28 AM UTC 24 |
| Peak memory | 238304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3529805453 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c trl_sec_cm.3529805453 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2100824370 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2153160433 ps |
| CPU time | 4.86 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:48:50 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100824370 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst _ctrl_tl_errors.2100824370 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1185726457 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 42818203562 ps |
| CPU time | 46.93 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:49:35 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1185 726457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.sysrst_ctrl_tl_intg_err.1185726457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1734703438 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3235369589 ps |
| CPU time | 3.46 seconds |
| Started | Aug 21 07:29:39 AM UTC 24 |
| Finished | Aug 21 07:29:43 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1734703438 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk _key_output.1734703438 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2915820765 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 161047349494 ps |
| CPU time | 108.38 seconds |
| Started | Aug 21 07:36:06 AM UTC 24 |
| Finished | Aug 21 07:37:57 AM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29158207 65 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29 .sysrst_ctrl_stress_all.2915820765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1181631200 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 27586353476 ps |
| CPU time | 22.38 seconds |
| Started | Aug 21 07:38:12 AM UTC 24 |
| Finished | Aug 21 07:38:35 AM UTC 24 |
| Peak memory | 227080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1181631200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1181631200 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2974061051 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 11335162515 ps |
| CPU time | 4.41 seconds |
| Started | Aug 21 07:36:33 AM UTC 24 |
| Finished | Aug 21 07:36:39 AM UTC 24 |
| Peak memory | 220456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974061051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.2974061051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.445020593 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 118546096926 ps |
| CPU time | 185.91 seconds |
| Started | Aug 21 07:31:22 AM UTC 24 |
| Finished | Aug 21 07:34:31 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=445020593 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_c ombo_detect_with_pre_cond.445020593 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.3120669953 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 163462727013 ps |
| CPU time | 92.25 seconds |
| Started | Aug 21 07:30:37 AM UTC 24 |
| Finished | Aug 21 07:32:11 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31206 69953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 10.sysrst_ctrl_combo_detect.3120669953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3035843772 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 19630822925 ps |
| CPU time | 14.05 seconds |
| Started | Aug 21 07:36:06 AM UTC 24 |
| Finished | Aug 21 07:36:22 AM UTC 24 |
| Peak memory | 220740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3035843772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3035843772 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.844651591 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1551567962390 ps |
| CPU time | 15.41 seconds |
| Started | Aug 21 07:31:10 AM UTC 24 |
| Finished | Aug 21 07:31:26 AM UTC 24 |
| Peak memory | 224952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=844651591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.844651591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.4241891120 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3479909810 ps |
| CPU time | 3.41 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:40 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42418 91120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.sysrst_ctrl_edge_detect.4241891120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1661094649 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 99461547700 ps |
| CPU time | 129.6 seconds |
| Started | Aug 21 07:32:40 AM UTC 24 |
| Finished | Aug 21 07:34:52 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661094649 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ combo_detect_with_pre_cond.1661094649 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1647358132 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 69554287296 ps |
| CPU time | 30.49 seconds |
| Started | Aug 21 07:36:05 AM UTC 24 |
| Finished | Aug 21 07:36:37 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16473 58132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 29.sysrst_ctrl_combo_detect.1647358132 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2714491949 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 31354429610 ps |
| CPU time | 16.82 seconds |
| Started | Aug 21 08:48:49 AM UTC 24 |
| Finished | Aug 21 08:49:07 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2714491 949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.2714491949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1004188307 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2545149210 ps |
| CPU time | 2.93 seconds |
| Started | Aug 21 07:26:46 AM UTC 24 |
| Finished | Aug 21 07:26:50 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1004188307 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_te st.1004188307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.1550032335 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 109917380908 ps |
| CPU time | 171 seconds |
| Started | Aug 21 07:29:54 AM UTC 24 |
| Finished | Aug 21 07:32:47 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15500 32335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 8.sysrst_ctrl_combo_detect.1550032335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1637422327 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 152983418043 ps |
| CPU time | 75.74 seconds |
| Started | Aug 21 07:31:10 AM UTC 24 |
| Finished | Aug 21 07:32:27 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1637422327 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ combo_detect_with_pre_cond.1637422327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3174139713 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2037626019 ps |
| CPU time | 3.94 seconds |
| Started | Aug 21 07:26:37 AM UTC 24 |
| Finished | Aug 21 07:26:42 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3174139713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ ctrl_alert_test.3174139713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4123517991 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 163449206551 ps |
| CPU time | 188.13 seconds |
| Started | Aug 21 07:36:32 AM UTC 24 |
| Finished | Aug 21 07:39:43 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123517991 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ combo_detect_with_pre_cond.4123517991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.3001543607 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4740815279 ps |
| CPU time | 15 seconds |
| Started | Aug 21 07:29:24 AM UTC 24 |
| Finished | Aug 21 07:29:40 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30015 43607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.sysrst_ctrl_edge_detect.3001543607 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3478416018 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3930409585 ps |
| CPU time | 2.52 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:36 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34784 16018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.sysrst_ctrl_edge_detect.3478416018 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.2399785446 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 109673530989 ps |
| CPU time | 29.12 seconds |
| Started | Aug 21 07:31:42 AM UTC 24 |
| Finished | Aug 21 07:32:12 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23997 85446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 15.sysrst_ctrl_combo_detect.2399785446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2891827574 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 51441291495 ps |
| CPU time | 46.09 seconds |
| Started | Aug 21 07:26:55 AM UTC 24 |
| Finished | Aug 21 07:27:43 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2891827574 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_c ombo_detect_with_pre_cond.2891827574 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2523078833 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2141872381 ps |
| CPU time | 3.74 seconds |
| Started | Aug 21 08:49:24 AM UTC 24 |
| Finished | Aug 21 08:49:29 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2523078833 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrs t_ctrl_tl_errors.2523078833 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2674678679 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3098669333 ps |
| CPU time | 14.22 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:47 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2674678679 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk _key_output.2674678679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3287808009 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 80610977012 ps |
| CPU time | 219.44 seconds |
| Started | Aug 21 07:32:28 AM UTC 24 |
| Finished | Aug 21 07:36:10 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32878080 09 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18 .sysrst_ctrl_stress_all.3287808009 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3802218794 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2565041734 ps |
| CPU time | 2.19 seconds |
| Started | Aug 21 07:27:16 AM UTC 24 |
| Finished | Aug 21 07:27:20 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802218794 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_te st.3802218794 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3996525304 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 104247172633 ps |
| CPU time | 131.22 seconds |
| Started | Aug 21 07:35:06 AM UTC 24 |
| Finished | Aug 21 07:37:20 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39965253 04 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sysrst_ctrl_stress_all.3996525304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2283381367 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 4899643996 ps |
| CPU time | 13.41 seconds |
| Started | Aug 21 07:31:09 AM UTC 24 |
| Finished | Aug 21 07:31:23 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22833 81367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 12.sysrst_ctrl_ultra_low_pwr.2283381367 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.847014892 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 22701045221 ps |
| CPU time | 17.19 seconds |
| Started | Aug 21 08:49:24 AM UTC 24 |
| Finished | Aug 21 08:49:42 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8470 14892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 10.sysrst_ctrl_tl_intg_err.847014892 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.700353291 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 84860480312 ps |
| CPU time | 254.79 seconds |
| Started | Aug 21 07:34:29 AM UTC 24 |
| Finished | Aug 21 07:38:47 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=700353291 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_c ombo_detect_with_pre_cond.700353291 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.4156551744 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 187874196857 ps |
| CPU time | 496.35 seconds |
| Started | Aug 21 07:40:46 AM UTC 24 |
| Finished | Aug 21 07:49:08 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156551744 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_ combo_detect_with_pre_cond.4156551744 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.238824464 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 210258214338 ps |
| CPU time | 20.8 seconds |
| Started | Aug 21 07:30:29 AM UTC 24 |
| Finished | Aug 21 07:30:51 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23882 4464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 10.sysrst_ctrl_ultra_low_pwr.238824464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.182351579 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 42382565783 ps |
| CPU time | 80.9 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:50:07 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1823 51579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.sysrst_ctrl_tl_intg_err.182351579 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.243090773 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 12012635157 ps |
| CPU time | 17.61 seconds |
| Started | Aug 21 07:27:28 AM UTC 24 |
| Finished | Aug 21 07:27:47 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24309077 3 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ysrst_ctrl_stress_all.243090773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1035690439 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 99148047957 ps |
| CPU time | 290.87 seconds |
| Started | Aug 21 07:35:45 AM UTC 24 |
| Finished | Aug 21 07:40:40 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1035690439 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ combo_detect_with_pre_cond.1035690439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2288299660 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 47140434259 ps |
| CPU time | 21.55 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:37:32 AM UTC 24 |
| Peak memory | 220860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2288299660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.2288299660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.3336405413 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 72715404828 ps |
| CPU time | 19.65 seconds |
| Started | Aug 21 07:38:56 AM UTC 24 |
| Finished | Aug 21 07:39:17 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33364 05413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 42.sysrst_ctrl_combo_detect.3336405413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.748530494 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 86774067304 ps |
| CPU time | 243.08 seconds |
| Started | Aug 21 07:40:51 AM UTC 24 |
| Finished | Aug 21 07:44:57 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=748530494 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_c ombo_detect_with_pre_cond.748530494 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3848219903 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3723380286 ps |
| CPU time | 8.33 seconds |
| Started | Aug 21 07:26:51 AM UTC 24 |
| Finished | Aug 21 07:27:01 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38482 19903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.sysrst_ctrl_edge_detect.3848219903 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2817316445 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 541666232621 ps |
| CPU time | 1068.12 seconds |
| Started | Aug 21 07:30:37 AM UTC 24 |
| Finished | Aug 21 07:48:37 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28173 16445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.sysrst_ctrl_edge_detect.2817316445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.2292046748 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3404418709 ps |
| CPU time | 4.05 seconds |
| Started | Aug 21 07:35:30 AM UTC 24 |
| Finished | Aug 21 07:35:35 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22920 46748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.sysrst_ctrl_edge_detect.2292046748 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.1220430533 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3443406504 ps |
| CPU time | 12.69 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:37:23 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12204 30533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.sysrst_ctrl_edge_detect.1220430533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3365207839 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3747373315 ps |
| CPU time | 14.27 seconds |
| Started | Aug 21 07:28:11 AM UTC 24 |
| Finished | Aug 21 07:28:27 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33652 07839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.sysrst_ctrl_edge_detect.3365207839 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1928267968 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 286322866447 ps |
| CPU time | 68.7 seconds |
| Started | Aug 21 07:39:14 AM UTC 24 |
| Finished | Aug 21 07:40:25 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19282 67968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.sysrst_ctrl_edge_detect.1928267968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1895762504 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 89738422328 ps |
| CPU time | 266.77 seconds |
| Started | Aug 21 07:31:34 AM UTC 24 |
| Finished | Aug 21 07:36:04 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1895762504 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ combo_detect_with_pre_cond.1895762504 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1942611889 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 504271480520 ps |
| CPU time | 11.67 seconds |
| Started | Aug 21 07:31:59 AM UTC 24 |
| Finished | Aug 21 07:32:12 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19426 11889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sysrst_ctrl_ultra_low_pwr.1942611889 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.246719770 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 98834360418 ps |
| CPU time | 330.3 seconds |
| Started | Aug 21 07:27:47 AM UTC 24 |
| Finished | Aug 21 07:33:21 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24671977 0 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ysrst_ctrl_stress_all.246719770 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.145709732 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 20846935084 ps |
| CPU time | 44.48 seconds |
| Started | Aug 21 07:36:11 AM UTC 24 |
| Finished | Aug 21 07:36:57 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145709732 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_c ombo_detect_with_pre_cond.145709732 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4048068315 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 64212324778 ps |
| CPU time | 181.6 seconds |
| Started | Aug 21 07:36:39 AM UTC 24 |
| Finished | Aug 21 07:39:44 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4048068315 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ combo_detect_with_pre_cond.4048068315 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2095328765 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 114046950705 ps |
| CPU time | 109.72 seconds |
| Started | Aug 21 07:28:13 AM UTC 24 |
| Finished | Aug 21 07:30:05 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2095328765 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_c ombo_detect_with_pre_cond.2095328765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2118106450 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 109143945899 ps |
| CPU time | 100.25 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:40:28 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2118106450 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ combo_detect_with_pre_cond.2118106450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1953246248 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 139442093846 ps |
| CPU time | 29.41 seconds |
| Started | Aug 21 07:39:54 AM UTC 24 |
| Finished | Aug 21 07:40:25 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953246248 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ combo_detect_with_pre_cond.1953246248 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1941796355 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 45683948370 ps |
| CPU time | 79.4 seconds |
| Started | Aug 21 07:40:57 AM UTC 24 |
| Finished | Aug 21 07:42:18 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1941796355 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_ combo_detect_with_pre_cond.1941796355 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.3392610961 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 166676830671 ps |
| CPU time | 447.69 seconds |
| Started | Aug 21 07:29:40 AM UTC 24 |
| Finished | Aug 21 07:37:12 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33926 10961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 7.sysrst_ctrl_combo_detect.3392610961 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.895955073 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 65598912486 ps |
| CPU time | 161.59 seconds |
| Started | Aug 21 07:42:05 AM UTC 24 |
| Finished | Aug 21 07:44:49 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=895955073 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_c ombo_detect_with_pre_cond.895955073 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.450000524 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 7554646106 ps |
| CPU time | 27.21 seconds |
| Started | Aug 21 08:48:45 AM UTC 24 |
| Finished | Aug 21 08:49:13 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=450000524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.sysrst_ctrl_same_csr_outstanding.450000524 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1353446414 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 62858745553 ps |
| CPU time | 16.2 seconds |
| Started | Aug 21 07:32:02 AM UTC 24 |
| Finished | Aug 21 07:32:20 AM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1353446414 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ combo_detect_with_pre_cond.1353446414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3305791392 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2690104407 ps |
| CPU time | 3.84 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:48:50 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305791 392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.3305791392 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3363060080 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 39897664721 ps |
| CPU time | 103.9 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:50:30 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3363060 080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.3363060080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3806339430 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4058448045 ps |
| CPU time | 5.44 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:48:51 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3806339 430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.3806339430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1476710538 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2090114914 ps |
| CPU time | 2.75 seconds |
| Started | Aug 21 08:48:45 AM UTC 24 |
| Finished | Aug 21 08:48:49 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=1476710538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1476710538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.878050958 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2132916745 ps |
| CPU time | 2.87 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:48:48 AM UTC 24 |
| Peak memory | 211088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=878050958 -as sert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysr st_ctrl_csr_rw.878050958 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.123976651 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 2024748099 ps |
| CPU time | 2.76 seconds |
| Started | Aug 21 08:48:44 AM UTC 24 |
| Finished | Aug 21 08:48:48 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=123976651 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ ctrl_intr_test.123976651 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.467388489 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3164240218 ps |
| CPU time | 6.4 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:54 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4673884 89 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.467388489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.4121630125 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 38116611639 ps |
| CPU time | 50.47 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:49:38 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4121630 125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.4121630125 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2307981536 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4069244987 ps |
| CPU time | 2.12 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:49 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2307981 536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.2307981536 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4118872899 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2082334343 ps |
| CPU time | 8.76 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:56 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=4118872899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.4118872899 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1816982684 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 2018161833 ps |
| CPU time | 10.6 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:58 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1816982684 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst _ctrl_intr_test.1816982684 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4044235176 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 5394727409 ps |
| CPU time | 36.96 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:49:25 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=4044235176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.sysrst_ctrl_same_csr_outstanding.4044235176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1530480944 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2030320360 ps |
| CPU time | 10.36 seconds |
| Started | Aug 21 08:48:45 AM UTC 24 |
| Finished | Aug 21 08:48:56 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530480944 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst _ctrl_tl_errors.1530480944 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3022631257 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 22188192918 ps |
| CPU time | 60.27 seconds |
| Started | Aug 21 08:48:45 AM UTC 24 |
| Finished | Aug 21 08:49:47 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3022 631257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.sysrst_ctrl_tl_intg_err.3022631257 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3446952491 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2298272587 ps |
| CPU time | 2.66 seconds |
| Started | Aug 21 08:49:25 AM UTC 24 |
| Finished | Aug 21 08:49:29 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3446952491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3446952491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1965749038 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2063637868 ps |
| CPU time | 2.51 seconds |
| Started | Aug 21 08:49:25 AM UTC 24 |
| Finished | Aug 21 08:49:29 AM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965749038 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sy srst_ctrl_csr_rw.1965749038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3621867500 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2029409901 ps |
| CPU time | 4.23 seconds |
| Started | Aug 21 08:49:25 AM UTC 24 |
| Finished | Aug 21 08:49:30 AM UTC 24 |
| Peak memory | 210548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3621867500 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrs t_ctrl_intr_test.3621867500 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1529677702 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 7723869010 ps |
| CPU time | 9.32 seconds |
| Started | Aug 21 08:49:25 AM UTC 24 |
| Finished | Aug 21 08:49:36 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=1529677702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.sysrst_ctrl_same_csr_outstanding.1529677702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4006682038 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 2065656071 ps |
| CPU time | 4.38 seconds |
| Started | Aug 21 08:49:29 AM UTC 24 |
| Finished | Aug 21 08:49:34 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=4006682038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4006682038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1169348538 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2074364650 ps |
| CPU time | 3.8 seconds |
| Started | Aug 21 08:49:28 AM UTC 24 |
| Finished | Aug 21 08:49:32 AM UTC 24 |
| Peak memory | 211144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1169348538 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sy srst_ctrl_csr_rw.1169348538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3828312259 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2016770373 ps |
| CPU time | 4.7 seconds |
| Started | Aug 21 08:49:26 AM UTC 24 |
| Finished | Aug 21 08:49:32 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3828312259 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrs t_ctrl_intr_test.3828312259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4183041022 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 5319670977 ps |
| CPU time | 26.52 seconds |
| Started | Aug 21 08:49:29 AM UTC 24 |
| Finished | Aug 21 08:49:57 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=4183041022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.sysrst_ctrl_same_csr_outstanding.4183041022 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3467619572 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 2111883008 ps |
| CPU time | 14.38 seconds |
| Started | Aug 21 08:49:25 AM UTC 24 |
| Finished | Aug 21 08:49:41 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3467619572 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrs t_ctrl_tl_errors.3467619572 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2569550901 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 22243048977 ps |
| CPU time | 59.85 seconds |
| Started | Aug 21 08:49:26 AM UTC 24 |
| Finished | Aug 21 08:50:28 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2569 550901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.sysrst_ctrl_tl_intg_err.2569550901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.904279214 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2056966184 ps |
| CPU time | 11.12 seconds |
| Started | Aug 21 08:49:31 AM UTC 24 |
| Finished | Aug 21 08:49:43 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=904279214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.904279214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1784972495 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2051148590 ps |
| CPU time | 7.11 seconds |
| Started | Aug 21 08:49:30 AM UTC 24 |
| Finished | Aug 21 08:49:38 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1784972495 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sy srst_ctrl_csr_rw.1784972495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4204001918 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2015719630 ps |
| CPU time | 5.32 seconds |
| Started | Aug 21 08:49:30 AM UTC 24 |
| Finished | Aug 21 08:49:36 AM UTC 24 |
| Peak memory | 210884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4204001918 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrs t_ctrl_intr_test.4204001918 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.885068561 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 10292986533 ps |
| CPU time | 12.57 seconds |
| Started | Aug 21 08:49:31 AM UTC 24 |
| Finished | Aug 21 08:49:45 AM UTC 24 |
| Peak memory | 211324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=885068561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.sysrst_ctrl_same_csr_outstanding.885068561 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1733502683 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2123499457 ps |
| CPU time | 3.15 seconds |
| Started | Aug 21 08:49:29 AM UTC 24 |
| Finished | Aug 21 08:49:33 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1733502683 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrs t_ctrl_tl_errors.1733502683 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1989948523 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 22323843824 ps |
| CPU time | 39.58 seconds |
| Started | Aug 21 08:49:30 AM UTC 24 |
| Finished | Aug 21 08:50:11 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1989 948523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 12.sysrst_ctrl_tl_intg_err.1989948523 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2559398840 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 2098894855 ps |
| CPU time | 3.58 seconds |
| Started | Aug 21 08:49:36 AM UTC 24 |
| Finished | Aug 21 08:49:40 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=2559398840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2559398840 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3122175270 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2030806873 ps |
| CPU time | 5.92 seconds |
| Started | Aug 21 08:49:36 AM UTC 24 |
| Finished | Aug 21 08:49:43 AM UTC 24 |
| Peak memory | 210936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3122175270 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sy srst_ctrl_csr_rw.3122175270 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3978826916 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2008526107 ps |
| CPU time | 9.23 seconds |
| Started | Aug 21 08:49:34 AM UTC 24 |
| Finished | Aug 21 08:49:44 AM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3978826916 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrs t_ctrl_intr_test.3978826916 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3016382137 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4113467294 ps |
| CPU time | 23.36 seconds |
| Started | Aug 21 08:49:36 AM UTC 24 |
| Finished | Aug 21 08:50:00 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3016382137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.sysrst_ctrl_same_csr_outstanding.3016382137 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1120590788 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 2085016894 ps |
| CPU time | 9.71 seconds |
| Started | Aug 21 08:49:34 AM UTC 24 |
| Finished | Aug 21 08:49:44 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1120590788 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrs t_ctrl_tl_errors.1120590788 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1403258335 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 22266791975 ps |
| CPU time | 22.26 seconds |
| Started | Aug 21 08:49:34 AM UTC 24 |
| Finished | Aug 21 08:49:57 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1403 258335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.sysrst_ctrl_tl_intg_err.1403258335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3728487347 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2061590044 ps |
| CPU time | 8.83 seconds |
| Started | Aug 21 08:49:41 AM UTC 24 |
| Finished | Aug 21 08:49:51 AM UTC 24 |
| Peak memory | 211076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3728487347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3728487347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4165475391 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2037764198 ps |
| CPU time | 4.51 seconds |
| Started | Aug 21 08:49:39 AM UTC 24 |
| Finished | Aug 21 08:49:45 AM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165475391 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sy srst_ctrl_csr_rw.4165475391 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.231243259 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 2014404518 ps |
| CPU time | 8.4 seconds |
| Started | Aug 21 08:49:37 AM UTC 24 |
| Finished | Aug 21 08:49:47 AM UTC 24 |
| Peak memory | 210684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231243259 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst _ctrl_intr_test.231243259 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.92121176 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 5331691712 ps |
| CPU time | 22.56 seconds |
| Started | Aug 21 08:49:39 AM UTC 24 |
| Finished | Aug 21 08:50:03 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=92121176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 14.sysrst_ctrl_same_csr_outstanding.92121176 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2403057235 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 2154463085 ps |
| CPU time | 3.88 seconds |
| Started | Aug 21 08:49:37 AM UTC 24 |
| Finished | Aug 21 08:49:42 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2403057235 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrs t_ctrl_tl_errors.2403057235 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1988248978 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 42631148645 ps |
| CPU time | 49.02 seconds |
| Started | Aug 21 08:49:37 AM UTC 24 |
| Finished | Aug 21 08:50:27 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1988 248978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 14.sysrst_ctrl_tl_intg_err.1988248978 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3353569831 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2185991751 ps |
| CPU time | 3.18 seconds |
| Started | Aug 21 08:49:45 AM UTC 24 |
| Finished | Aug 21 08:49:49 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3353569831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3353569831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.448976266 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2032188993 ps |
| CPU time | 9.02 seconds |
| Started | Aug 21 08:49:44 AM UTC 24 |
| Finished | Aug 21 08:49:54 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448976266 -as sert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sys rst_ctrl_csr_rw.448976266 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2385672973 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2012504337 ps |
| CPU time | 6.85 seconds |
| Started | Aug 21 08:49:44 AM UTC 24 |
| Finished | Aug 21 08:49:52 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385672973 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrs t_ctrl_intr_test.2385672973 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2855771897 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4697340286 ps |
| CPU time | 9.37 seconds |
| Started | Aug 21 08:49:44 AM UTC 24 |
| Finished | Aug 21 08:49:54 AM UTC 24 |
| Peak memory | 211224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=2855771897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.sysrst_ctrl_same_csr_outstanding.2855771897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1028058719 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 2547285257 ps |
| CPU time | 4.75 seconds |
| Started | Aug 21 08:49:42 AM UTC 24 |
| Finished | Aug 21 08:49:48 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1028058719 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrs t_ctrl_tl_errors.1028058719 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1950083201 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 22833951910 ps |
| CPU time | 8.18 seconds |
| Started | Aug 21 08:49:43 AM UTC 24 |
| Finished | Aug 21 08:49:52 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1950 083201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.sysrst_ctrl_tl_intg_err.1950083201 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.694559891 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2115714614 ps |
| CPU time | 3.77 seconds |
| Started | Aug 21 08:49:48 AM UTC 24 |
| Finished | Aug 21 08:49:52 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=694559891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.694559891 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3289770798 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2040384919 ps |
| CPU time | 5.69 seconds |
| Started | Aug 21 08:49:46 AM UTC 24 |
| Finished | Aug 21 08:49:53 AM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3289770798 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sy srst_ctrl_csr_rw.3289770798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3394611130 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2020470868 ps |
| CPU time | 3.89 seconds |
| Started | Aug 21 08:49:45 AM UTC 24 |
| Finished | Aug 21 08:49:50 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394611130 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrs t_ctrl_intr_test.3394611130 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3318959868 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 4702937704 ps |
| CPU time | 21.29 seconds |
| Started | Aug 21 08:49:48 AM UTC 24 |
| Finished | Aug 21 08:50:10 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3318959868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 16.sysrst_ctrl_same_csr_outstanding.3318959868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.261432688 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2082624545 ps |
| CPU time | 8.6 seconds |
| Started | Aug 21 08:49:45 AM UTC 24 |
| Finished | Aug 21 08:49:55 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=261432688 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst _ctrl_tl_errors.261432688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1470006399 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 23159896871 ps |
| CPU time | 7.32 seconds |
| Started | Aug 21 08:49:45 AM UTC 24 |
| Finished | Aug 21 08:49:54 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470 006399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 16.sysrst_ctrl_tl_intg_err.1470006399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.964746538 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2279733646 ps |
| CPU time | 1.46 seconds |
| Started | Aug 21 08:49:52 AM UTC 24 |
| Finished | Aug 21 08:49:55 AM UTC 24 |
| Peak memory | 221160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=964746538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.964746538 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.850717082 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2052706136 ps |
| CPU time | 8.85 seconds |
| Started | Aug 21 08:49:52 AM UTC 24 |
| Finished | Aug 21 08:50:02 AM UTC 24 |
| Peak memory | 211024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=850717082 -as sert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sys rst_ctrl_csr_rw.850717082 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.477154109 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2011617368 ps |
| CPU time | 10.32 seconds |
| Started | Aug 21 08:49:51 AM UTC 24 |
| Finished | Aug 21 08:50:02 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=477154109 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst _ctrl_intr_test.477154109 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.4022892982 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4710344778 ps |
| CPU time | 17.46 seconds |
| Started | Aug 21 08:49:52 AM UTC 24 |
| Finished | Aug 21 08:50:11 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=4022892982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.sysrst_ctrl_same_csr_outstanding.4022892982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.211279231 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 2086924416 ps |
| CPU time | 5.24 seconds |
| Started | Aug 21 08:49:49 AM UTC 24 |
| Finished | Aug 21 08:49:55 AM UTC 24 |
| Peak memory | 211252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211279231 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst _ctrl_tl_errors.211279231 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2021827455 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 22210838294 ps |
| CPU time | 66 seconds |
| Started | Aug 21 08:49:50 AM UTC 24 |
| Finished | Aug 21 08:50:57 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2021 827455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sysrst_ctrl_tl_intg_err.2021827455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3175207924 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2090033382 ps |
| CPU time | 5.51 seconds |
| Started | Aug 21 08:49:56 AM UTC 24 |
| Finished | Aug 21 08:50:03 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3175207924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3175207924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2706023104 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2045205139 ps |
| CPU time | 11.5 seconds |
| Started | Aug 21 08:49:55 AM UTC 24 |
| Finished | Aug 21 08:50:08 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706023104 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sy srst_ctrl_csr_rw.2706023104 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1142339324 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2036522705 ps |
| CPU time | 3.48 seconds |
| Started | Aug 21 08:49:55 AM UTC 24 |
| Finished | Aug 21 08:50:00 AM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1142339324 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrs t_ctrl_intr_test.1142339324 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2776342859 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 7401854415 ps |
| CPU time | 31.96 seconds |
| Started | Aug 21 08:49:55 AM UTC 24 |
| Finished | Aug 21 08:50:29 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=2776342859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.sysrst_ctrl_same_csr_outstanding.2776342859 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2197602173 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2279947273 ps |
| CPU time | 4.39 seconds |
| Started | Aug 21 08:49:53 AM UTC 24 |
| Finished | Aug 21 08:49:59 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197602173 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrs t_ctrl_tl_errors.2197602173 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3005903230 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 42485767230 ps |
| CPU time | 132.13 seconds |
| Started | Aug 21 08:49:53 AM UTC 24 |
| Finished | Aug 21 08:52:08 AM UTC 24 |
| Peak memory | 211220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3005 903230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sysrst_ctrl_tl_intg_err.3005903230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.865638982 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 2148617281 ps |
| CPU time | 2.98 seconds |
| Started | Aug 21 08:50:00 AM UTC 24 |
| Finished | Aug 21 08:50:05 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=865638982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverag e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.865638982 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1562491911 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2558575473 ps |
| CPU time | 1.81 seconds |
| Started | Aug 21 08:49:57 AM UTC 24 |
| Finished | Aug 21 08:50:00 AM UTC 24 |
| Peak memory | 209676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1562491911 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sy srst_ctrl_csr_rw.1562491911 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2091786382 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2014391342 ps |
| CPU time | 9.16 seconds |
| Started | Aug 21 08:49:56 AM UTC 24 |
| Finished | Aug 21 08:50:06 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2091786382 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrs t_ctrl_intr_test.2091786382 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3761792225 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 4866209447 ps |
| CPU time | 4.98 seconds |
| Started | Aug 21 08:49:57 AM UTC 24 |
| Finished | Aug 21 08:50:03 AM UTC 24 |
| Peak memory | 211328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3761792225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 19.sysrst_ctrl_same_csr_outstanding.3761792225 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3197047827 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 2092269479 ps |
| CPU time | 12.42 seconds |
| Started | Aug 21 08:49:56 AM UTC 24 |
| Finished | Aug 21 08:50:10 AM UTC 24 |
| Peak memory | 211160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3197047827 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrs t_ctrl_tl_errors.3197047827 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.493618581 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 42492402190 ps |
| CPU time | 33.32 seconds |
| Started | Aug 21 08:49:56 AM UTC 24 |
| Finished | Aug 21 08:50:31 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4936 18581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 19.sysrst_ctrl_tl_intg_err.493618581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.413861511 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2581857705 ps |
| CPU time | 3.93 seconds |
| Started | Aug 21 08:48:50 AM UTC 24 |
| Finished | Aug 21 08:48:55 AM UTC 24 |
| Peak memory | 211388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4138615 11 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.413861511 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2269241694 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6021347051 ps |
| CPU time | 17.68 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:49:05 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2269241 694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.2269241694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.92103531 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2093760064 ps |
| CPU time | 3.51 seconds |
| Started | Aug 21 08:48:50 AM UTC 24 |
| Finished | Aug 21 08:48:55 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=92103531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage /cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.92103531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.279603214 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2036782142 ps |
| CPU time | 10.81 seconds |
| Started | Aug 21 08:48:48 AM UTC 24 |
| Finished | Aug 21 08:48:59 AM UTC 24 |
| Peak memory | 210948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279603214 -as sert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysr st_ctrl_csr_rw.279603214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3460651062 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2031739721 ps |
| CPU time | 1.63 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:49 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3460651062 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst _ctrl_intr_test.3460651062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3673448972 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5142400936 ps |
| CPU time | 17.08 seconds |
| Started | Aug 21 08:48:50 AM UTC 24 |
| Finished | Aug 21 08:49:08 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3673448972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.sysrst_ctrl_same_csr_outstanding.3673448972 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3574317922 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2268711274 ps |
| CPU time | 6.1 seconds |
| Started | Aug 21 08:48:46 AM UTC 24 |
| Finished | Aug 21 08:48:53 AM UTC 24 |
| Peak memory | 211472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574317922 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst _ctrl_tl_errors.3574317922 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1568688000 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2014676993 ps |
| CPU time | 6.09 seconds |
| Started | Aug 21 08:50:01 AM UTC 24 |
| Finished | Aug 21 08:50:09 AM UTC 24 |
| Peak memory | 210764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1568688000 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrs t_ctrl_intr_test.1568688000 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1407851730 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2013242562 ps |
| CPU time | 7.88 seconds |
| Started | Aug 21 08:50:01 AM UTC 24 |
| Finished | Aug 21 08:50:10 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1407851730 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrs t_ctrl_intr_test.1407851730 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.978946359 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2015875358 ps |
| CPU time | 8 seconds |
| Started | Aug 21 08:50:02 AM UTC 24 |
| Finished | Aug 21 08:50:11 AM UTC 24 |
| Peak memory | 210880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=978946359 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst _ctrl_intr_test.978946359 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3023280223 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2017436392 ps |
| CPU time | 5.88 seconds |
| Started | Aug 21 08:50:03 AM UTC 24 |
| Finished | Aug 21 08:50:10 AM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023280223 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrs t_ctrl_intr_test.3023280223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.365806085 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2025325422 ps |
| CPU time | 5.21 seconds |
| Started | Aug 21 08:50:03 AM UTC 24 |
| Finished | Aug 21 08:50:10 AM UTC 24 |
| Peak memory | 210772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=365806085 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst _ctrl_intr_test.365806085 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.153807898 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2031900592 ps |
| CPU time | 3.29 seconds |
| Started | Aug 21 08:50:03 AM UTC 24 |
| Finished | Aug 21 08:50:08 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=153807898 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst _ctrl_intr_test.153807898 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.998085509 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2037818248 ps |
| CPU time | 3.04 seconds |
| Started | Aug 21 08:50:04 AM UTC 24 |
| Finished | Aug 21 08:50:08 AM UTC 24 |
| Peak memory | 210604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998085509 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst _ctrl_intr_test.998085509 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.500032837 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2036347818 ps |
| CPU time | 3.34 seconds |
| Started | Aug 21 08:50:04 AM UTC 24 |
| Finished | Aug 21 08:50:09 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=500032837 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst _ctrl_intr_test.500032837 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3082293906 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2093492079 ps |
| CPU time | 2.01 seconds |
| Started | Aug 21 08:50:04 AM UTC 24 |
| Finished | Aug 21 08:50:08 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082293906 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrs t_ctrl_intr_test.3082293906 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.861815924 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2055311005 ps |
| CPU time | 2.14 seconds |
| Started | Aug 21 08:50:06 AM UTC 24 |
| Finished | Aug 21 08:50:09 AM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=861815924 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst _ctrl_intr_test.861815924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3364271618 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3233265160 ps |
| CPU time | 13.96 seconds |
| Started | Aug 21 08:48:55 AM UTC 24 |
| Finished | Aug 21 08:49:10 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3364271 618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.3364271618 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2574515531 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 39999863563 ps |
| CPU time | 40.19 seconds |
| Started | Aug 21 08:48:55 AM UTC 24 |
| Finished | Aug 21 08:49:36 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2574515 531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.2574515531 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3473117411 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4026841268 ps |
| CPU time | 6.13 seconds |
| Started | Aug 21 08:48:51 AM UTC 24 |
| Finished | Aug 21 08:48:58 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3473117 411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.3473117411 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3481489427 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2139727735 ps |
| CPU time | 3.4 seconds |
| Started | Aug 21 08:48:56 AM UTC 24 |
| Finished | Aug 21 08:49:00 AM UTC 24 |
| Peak memory | 221280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3481489427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3481489427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.128912845 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 2031372721 ps |
| CPU time | 5.08 seconds |
| Started | Aug 21 08:48:52 AM UTC 24 |
| Finished | Aug 21 08:48:59 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=128912845 -as sert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysr st_ctrl_csr_rw.128912845 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1299491055 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2011802607 ps |
| CPU time | 6.84 seconds |
| Started | Aug 21 08:48:51 AM UTC 24 |
| Finished | Aug 21 08:48:59 AM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1299491055 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst _ctrl_intr_test.1299491055 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2876967028 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 8772945136 ps |
| CPU time | 7.5 seconds |
| Started | Aug 21 08:48:56 AM UTC 24 |
| Finished | Aug 21 08:49:05 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=2876967028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.sysrst_ctrl_same_csr_outstanding.2876967028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1277540171 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2423488386 ps |
| CPU time | 4.51 seconds |
| Started | Aug 21 08:48:50 AM UTC 24 |
| Finished | Aug 21 08:48:56 AM UTC 24 |
| Peak memory | 227720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1277540171 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst _ctrl_tl_errors.1277540171 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1391056928 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 22219527270 ps |
| CPU time | 84.35 seconds |
| Started | Aug 21 08:48:50 AM UTC 24 |
| Finished | Aug 21 08:50:16 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1391 056928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.sysrst_ctrl_tl_intg_err.1391056928 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3428361698 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2012643550 ps |
| CPU time | 5.98 seconds |
| Started | Aug 21 08:50:07 AM UTC 24 |
| Finished | Aug 21 08:50:14 AM UTC 24 |
| Peak memory | 210620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3428361698 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrs t_ctrl_intr_test.3428361698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.257715098 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2037723392 ps |
| CPU time | 2.19 seconds |
| Started | Aug 21 08:50:08 AM UTC 24 |
| Finished | Aug 21 08:50:11 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=257715098 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst _ctrl_intr_test.257715098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1278121308 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2024271400 ps |
| CPU time | 3.9 seconds |
| Started | Aug 21 08:50:08 AM UTC 24 |
| Finished | Aug 21 08:50:13 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1278121308 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrs t_ctrl_intr_test.1278121308 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.431763506 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2065981203 ps |
| CPU time | 2.15 seconds |
| Started | Aug 21 08:50:09 AM UTC 24 |
| Finished | Aug 21 08:50:12 AM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=431763506 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst _ctrl_intr_test.431763506 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1442265944 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2013488022 ps |
| CPU time | 6.77 seconds |
| Started | Aug 21 08:50:09 AM UTC 24 |
| Finished | Aug 21 08:50:17 AM UTC 24 |
| Peak memory | 210692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1442265944 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrs t_ctrl_intr_test.1442265944 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.971336811 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2038262564 ps |
| CPU time | 2.35 seconds |
| Started | Aug 21 08:50:09 AM UTC 24 |
| Finished | Aug 21 08:50:13 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971336811 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst _ctrl_intr_test.971336811 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3580889515 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2047009430 ps |
| CPU time | 2.71 seconds |
| Started | Aug 21 08:50:09 AM UTC 24 |
| Finished | Aug 21 08:50:13 AM UTC 24 |
| Peak memory | 210956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3580889515 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrs t_ctrl_intr_test.3580889515 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.831852349 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2011725414 ps |
| CPU time | 7.46 seconds |
| Started | Aug 21 08:50:09 AM UTC 24 |
| Finished | Aug 21 08:50:18 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=831852349 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst _ctrl_intr_test.831852349 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.4212418660 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2023662157 ps |
| CPU time | 3.91 seconds |
| Started | Aug 21 08:50:09 AM UTC 24 |
| Finished | Aug 21 08:50:14 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4212418660 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrs t_ctrl_intr_test.4212418660 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.29866510 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2039621618 ps |
| CPU time | 2.02 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:14 AM UTC 24 |
| Peak memory | 211020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29866510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ ctrl_intr_test.29866510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3457689468 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 2505882140 ps |
| CPU time | 9.48 seconds |
| Started | Aug 21 08:49:00 AM UTC 24 |
| Finished | Aug 21 08:49:10 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3457689 468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.3457689468 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.446285609 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 39440850785 ps |
| CPU time | 24.17 seconds |
| Started | Aug 21 08:49:00 AM UTC 24 |
| Finished | Aug 21 08:49:25 AM UTC 24 |
| Peak memory | 211260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4462856 09 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.446285609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1272036262 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6110379253 ps |
| CPU time | 4.12 seconds |
| Started | Aug 21 08:48:57 AM UTC 24 |
| Finished | Aug 21 08:49:03 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1272036 262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.1272036262 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2821803491 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2037200266 ps |
| CPU time | 10.05 seconds |
| Started | Aug 21 08:49:01 AM UTC 24 |
| Finished | Aug 21 08:49:12 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=2821803491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2821803491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2927637857 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 2050626120 ps |
| CPU time | 3.32 seconds |
| Started | Aug 21 08:48:58 AM UTC 24 |
| Finished | Aug 21 08:49:03 AM UTC 24 |
| Peak memory | 211016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927637857 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sys rst_ctrl_csr_rw.2927637857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3401348994 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2021638513 ps |
| CPU time | 5.85 seconds |
| Started | Aug 21 08:48:57 AM UTC 24 |
| Finished | Aug 21 08:49:04 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401348994 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst _ctrl_intr_test.3401348994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.327163667 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4575631840 ps |
| CPU time | 6.66 seconds |
| Started | Aug 21 08:49:00 AM UTC 24 |
| Finished | Aug 21 08:49:08 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=327163667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.sysrst_ctrl_same_csr_outstanding.327163667 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1275998626 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2160928419 ps |
| CPU time | 4.96 seconds |
| Started | Aug 21 08:48:56 AM UTC 24 |
| Finished | Aug 21 08:49:02 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1275998626 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst _ctrl_tl_errors.1275998626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1199266263 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 42527099723 ps |
| CPU time | 45.31 seconds |
| Started | Aug 21 08:48:56 AM UTC 24 |
| Finished | Aug 21 08:49:43 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1199 266263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.sysrst_ctrl_tl_intg_err.1199266263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3949838420 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2026380368 ps |
| CPU time | 2.24 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:14 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3949838420 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrs t_ctrl_intr_test.3949838420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2231623555 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2020214284 ps |
| CPU time | 6.98 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:19 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231623555 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrs t_ctrl_intr_test.2231623555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2789749702 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2101357837 ps |
| CPU time | 1.31 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:13 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789749702 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrs t_ctrl_intr_test.2789749702 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3981526361 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2069154336 ps |
| CPU time | 1.84 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:14 AM UTC 24 |
| Peak memory | 210156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3981526361 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrs t_ctrl_intr_test.3981526361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2856756007 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2020698969 ps |
| CPU time | 4.85 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:17 AM UTC 24 |
| Peak memory | 210812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2856756007 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrs t_ctrl_intr_test.2856756007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1402264285 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2032650225 ps |
| CPU time | 2.53 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:14 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1402264285 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrs t_ctrl_intr_test.1402264285 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4278226804 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2056343962 ps |
| CPU time | 2.71 seconds |
| Started | Aug 21 08:50:11 AM UTC 24 |
| Finished | Aug 21 08:50:15 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4278226804 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrs t_ctrl_intr_test.4278226804 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1743682178 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2023750418 ps |
| CPU time | 3.4 seconds |
| Started | Aug 21 08:50:12 AM UTC 24 |
| Finished | Aug 21 08:50:17 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743682178 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrs t_ctrl_intr_test.1743682178 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3035755227 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2035688343 ps |
| CPU time | 2.1 seconds |
| Started | Aug 21 08:50:12 AM UTC 24 |
| Finished | Aug 21 08:50:16 AM UTC 24 |
| Peak memory | 210952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3035755227 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrs t_ctrl_intr_test.3035755227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.971680009 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2039197630 ps |
| CPU time | 3.06 seconds |
| Started | Aug 21 08:50:12 AM UTC 24 |
| Finished | Aug 21 08:50:17 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971680009 -asser t nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst _ctrl_intr_test.971680009 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3453383036 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2181990651 ps |
| CPU time | 3.03 seconds |
| Started | Aug 21 08:49:05 AM UTC 24 |
| Finished | Aug 21 08:49:10 AM UTC 24 |
| Peak memory | 211136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3453383036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3453383036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3262678446 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2062422547 ps |
| CPU time | 4.61 seconds |
| Started | Aug 21 08:49:04 AM UTC 24 |
| Finished | Aug 21 08:49:10 AM UTC 24 |
| Peak memory | 211012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3262678446 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sys rst_ctrl_csr_rw.3262678446 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2166305687 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2016241469 ps |
| CPU time | 9.18 seconds |
| Started | Aug 21 08:49:03 AM UTC 24 |
| Finished | Aug 21 08:49:13 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2166305687 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst _ctrl_intr_test.2166305687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.4250508698 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 7799449359 ps |
| CPU time | 8.97 seconds |
| Started | Aug 21 08:49:05 AM UTC 24 |
| Finished | Aug 21 08:49:15 AM UTC 24 |
| Peak memory | 211264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=4250508698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sysrst_ctrl_same_csr_outstanding.4250508698 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1849699588 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2166048453 ps |
| CPU time | 10.26 seconds |
| Started | Aug 21 08:49:01 AM UTC 24 |
| Finished | Aug 21 08:49:12 AM UTC 24 |
| Peak memory | 221464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1849699588 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst _ctrl_tl_errors.1849699588 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3646510626 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 22227762175 ps |
| CPU time | 60.65 seconds |
| Started | Aug 21 08:49:03 AM UTC 24 |
| Finished | Aug 21 08:50:05 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3646 510626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sysrst_ctrl_tl_intg_err.3646510626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1631793577 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2134370797 ps |
| CPU time | 3.51 seconds |
| Started | Aug 21 08:49:09 AM UTC 24 |
| Finished | Aug 21 08:49:14 AM UTC 24 |
| Peak memory | 210756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=1631793577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1631793577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1774170075 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 2052120509 ps |
| CPU time | 6.21 seconds |
| Started | Aug 21 08:49:08 AM UTC 24 |
| Finished | Aug 21 08:49:15 AM UTC 24 |
| Peak memory | 210944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1774170075 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sys rst_ctrl_csr_rw.1774170075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2030072290 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 2013061910 ps |
| CPU time | 8.25 seconds |
| Started | Aug 21 08:49:08 AM UTC 24 |
| Finished | Aug 21 08:49:17 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2030072290 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst _ctrl_intr_test.2030072290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2088357807 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 4755399602 ps |
| CPU time | 8.86 seconds |
| Started | Aug 21 08:49:09 AM UTC 24 |
| Finished | Aug 21 08:49:19 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=2088357807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.sysrst_ctrl_same_csr_outstanding.2088357807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1849140696 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2558095616 ps |
| CPU time | 4.73 seconds |
| Started | Aug 21 08:49:07 AM UTC 24 |
| Finished | Aug 21 08:49:12 AM UTC 24 |
| Peak memory | 221408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1849140696 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst _ctrl_tl_errors.1849140696 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.4224470001 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 22204093303 ps |
| CPU time | 60.34 seconds |
| Started | Aug 21 08:49:08 AM UTC 24 |
| Finished | Aug 21 08:50:10 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224 470001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 6.sysrst_ctrl_tl_intg_err.4224470001 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3433787278 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2063885739 ps |
| CPU time | 11.02 seconds |
| Started | Aug 21 08:49:14 AM UTC 24 |
| Finished | Aug 21 08:49:26 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=3433787278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3433787278 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.801804203 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2056566057 ps |
| CPU time | 10.6 seconds |
| Started | Aug 21 08:49:11 AM UTC 24 |
| Finished | Aug 21 08:49:23 AM UTC 24 |
| Peak memory | 211028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=801804203 -as sert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysr st_ctrl_csr_rw.801804203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1415071930 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2018611308 ps |
| CPU time | 6.91 seconds |
| Started | Aug 21 08:49:11 AM UTC 24 |
| Finished | Aug 21 08:49:19 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1415071930 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst _ctrl_intr_test.1415071930 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1958606047 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4981032476 ps |
| CPU time | 13.8 seconds |
| Started | Aug 21 08:49:13 AM UTC 24 |
| Finished | Aug 21 08:49:27 AM UTC 24 |
| Peak memory | 211240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=1958606047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.sysrst_ctrl_same_csr_outstanding.1958606047 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2052470219 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 2043916247 ps |
| CPU time | 11.34 seconds |
| Started | Aug 21 08:49:10 AM UTC 24 |
| Finished | Aug 21 08:49:23 AM UTC 24 |
| Peak memory | 211200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2052470219 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst _ctrl_tl_errors.2052470219 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3876256440 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 42417985760 ps |
| CPU time | 126.11 seconds |
| Started | Aug 21 08:49:11 AM UTC 24 |
| Finished | Aug 21 08:51:20 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876 256440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sysrst_ctrl_tl_intg_err.3876256440 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1196147220 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2068871777 ps |
| CPU time | 6.76 seconds |
| Started | Aug 21 08:49:16 AM UTC 24 |
| Finished | Aug 21 08:49:24 AM UTC 24 |
| Peak memory | 211084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=1196147220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1196147220 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2217761490 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2033839686 ps |
| CPU time | 7.87 seconds |
| Started | Aug 21 08:49:15 AM UTC 24 |
| Finished | Aug 21 08:49:24 AM UTC 24 |
| Peak memory | 210940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2217761490 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sys rst_ctrl_csr_rw.2217761490 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3483447798 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2036895260 ps |
| CPU time | 3.57 seconds |
| Started | Aug 21 08:49:14 AM UTC 24 |
| Finished | Aug 21 08:49:19 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3483447798 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst _ctrl_intr_test.3483447798 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3572087244 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4723761756 ps |
| CPU time | 9.15 seconds |
| Started | Aug 21 08:49:16 AM UTC 24 |
| Finished | Aug 21 08:49:26 AM UTC 24 |
| Peak memory | 211072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=3572087244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.sysrst_ctrl_same_csr_outstanding.3572087244 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1868902688 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2210424366 ps |
| CPU time | 2.85 seconds |
| Started | Aug 21 08:49:14 AM UTC 24 |
| Finished | Aug 21 08:49:18 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1868902688 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst _ctrl_tl_errors.1868902688 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.89371676 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 42391571227 ps |
| CPU time | 113.76 seconds |
| Started | Aug 21 08:49:14 AM UTC 24 |
| Finished | Aug 21 08:51:10 AM UTC 24 |
| Peak memory | 211464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8937 1676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sysrst_ctrl_tl_intg_err.89371676 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2856833663 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2085878879 ps |
| CPU time | 5.77 seconds |
| Started | Aug 21 08:49:24 AM UTC 24 |
| Finished | Aug 21 08:49:31 AM UTC 24 |
| Peak memory | 211008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeo ut_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentit an/hw/dv/tools/sim.tcl +ntb_random_seed=2856833663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/covera ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2856833663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2045104070 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 2040302489 ps |
| CPU time | 4.1 seconds |
| Started | Aug 21 08:49:20 AM UTC 24 |
| Finished | Aug 21 08:49:25 AM UTC 24 |
| Peak memory | 211080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045104070 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sys rst_ctrl_csr_rw.2045104070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3250777120 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2050406841 ps |
| CPU time | 2.14 seconds |
| Started | Aug 21 08:49:20 AM UTC 24 |
| Finished | Aug 21 08:49:23 AM UTC 24 |
| Peak memory | 210624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250777120 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst _ctrl_intr_test.3250777120 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1414862413 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 9175793466 ps |
| CPU time | 12.73 seconds |
| Started | Aug 21 08:49:21 AM UTC 24 |
| Finished | Aug 21 08:49:35 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_ seed=1414862413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 9.sysrst_ctrl_same_csr_outstanding.1414862413 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3214585407 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2226662635 ps |
| CPU time | 8.4 seconds |
| Started | Aug 21 08:49:18 AM UTC 24 |
| Finished | Aug 21 08:49:28 AM UTC 24 |
| Peak memory | 221436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214585407 -asse rt nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst _ctrl_tl_errors.3214585407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3757056045 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 42463526661 ps |
| CPU time | 146.1 seconds |
| Started | Aug 21 08:49:18 AM UTC 24 |
| Finished | Aug 21 08:51:47 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3757 056045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 9.sysrst_ctrl_tl_intg_err.3757056045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.290039230 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2181149671 ps |
| CPU time | 3.82 seconds |
| Started | Aug 21 07:26:30 AM UTC 24 |
| Finished | Aug 21 07:26:34 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290039230 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det ect_ec_rst.290039230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1754809669 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2551283002 ps |
| CPU time | 3.68 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:36 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1754809669 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst _ctrl_combo_detect_ec_rst_with_pre_cond.1754809669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3514800778 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3071626817 ps |
| CPU time | 9.81 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:43 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35148 00778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.sysrst_ctrl_ec_pwr_on_rst.3514800778 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2014513825 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2640703693 ps |
| CPU time | 2.76 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:35 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2014513825 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_ out.2014513825 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3302396436 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2461863221 ps |
| CPU time | 9.88 seconds |
| Started | Aug 21 07:26:29 AM UTC 24 |
| Finished | Aug 21 07:26:40 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3302396436 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inver ted.3302396436 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4101022049 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2153873890 ps |
| CPU time | 3.25 seconds |
| Started | Aug 21 07:26:32 AM UTC 24 |
| Finished | Aug 21 07:26:36 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101022049 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.4101022049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.412759539 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2126433256 ps |
| CPU time | 3.35 seconds |
| Started | Aug 21 07:26:29 AM UTC 24 |
| Finished | Aug 21 07:26:34 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=412759539 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.412759539 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1071949606 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 8872411007 ps |
| CPU time | 34.08 seconds |
| Started | Aug 21 07:26:36 AM UTC 24 |
| Finished | Aug 21 07:27:12 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10719496 06 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0. sysrst_ctrl_stress_all.1071949606 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2054253693 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3736404463 ps |
| CPU time | 18.73 seconds |
| Started | Aug 21 07:26:36 AM UTC 24 |
| Finished | Aug 21 07:26:56 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054253693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2054253693 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3828248566 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2014771755 ps |
| CPU time | 7.56 seconds |
| Started | Aug 21 07:27:07 AM UTC 24 |
| Finished | Aug 21 07:27:16 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3828248566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ ctrl_alert_test.3828248566 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3801855417 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3231301621 ps |
| CPU time | 15.77 seconds |
| Started | Aug 21 07:26:49 AM UTC 24 |
| Finished | Aug 21 07:27:06 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3801855417 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk _key_output.3801855417 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2023232301 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 189955645768 ps |
| CPU time | 152.01 seconds |
| Started | Aug 21 07:26:50 AM UTC 24 |
| Finished | Aug 21 07:29:25 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20232 32301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 1.sysrst_ctrl_combo_detect.2023232301 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.811325819 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2227407459 ps |
| CPU time | 5.96 seconds |
| Started | Aug 21 07:26:42 AM UTC 24 |
| Finished | Aug 21 07:26:49 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=811325819 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_det ect_ec_rst.811325819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1688096946 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 2531377481 ps |
| CPU time | 7.36 seconds |
| Started | Aug 21 07:26:43 AM UTC 24 |
| Finished | Aug 21 07:26:51 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1688096946 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst _ctrl_combo_detect_ec_rst_with_pre_cond.1688096946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1817001977 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3973857438 ps |
| CPU time | 5.21 seconds |
| Started | Aug 21 07:26:48 AM UTC 24 |
| Finished | Aug 21 07:26:54 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18170 01977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.sysrst_ctrl_ec_pwr_on_rst.1817001977 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.351408543 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2619437288 ps |
| CPU time | 8.57 seconds |
| Started | Aug 21 07:26:47 AM UTC 24 |
| Finished | Aug 21 07:26:57 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351408543 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.351408543 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3255379388 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2484299109 ps |
| CPU time | 3.35 seconds |
| Started | Aug 21 07:26:40 AM UTC 24 |
| Finished | Aug 21 07:26:45 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255379388 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inver ted.3255379388 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.1597538704 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2244249847 ps |
| CPU time | 3.83 seconds |
| Started | Aug 21 07:26:44 AM UTC 24 |
| Finished | Aug 21 07:26:49 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597538704 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1597538704 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.4209493860 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 22213636557 ps |
| CPU time | 10.42 seconds |
| Started | Aug 21 07:27:02 AM UTC 24 |
| Finished | Aug 21 07:27:13 AM UTC 24 |
| Peak memory | 240216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4209493860 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c trl_sec_cm.4209493860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.4118420403 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2113702184 ps |
| CPU time | 6.61 seconds |
| Started | Aug 21 07:26:38 AM UTC 24 |
| Finished | Aug 21 07:26:46 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4118420403 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.4118420403 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3826444938 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5461972845 ps |
| CPU time | 31.39 seconds |
| Started | Aug 21 07:26:57 AM UTC 24 |
| Finished | Aug 21 07:27:29 AM UTC 24 |
| Peak memory | 220416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3826444938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3826444938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2592149599 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 13321728613 ps |
| CPU time | 4.85 seconds |
| Started | Aug 21 07:26:49 AM UTC 24 |
| Finished | Aug 21 07:26:55 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25921 49599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.sysrst_ctrl_ultra_low_pwr.2592149599 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.262928378 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2032516464 ps |
| CPU time | 3.08 seconds |
| Started | Aug 21 07:30:42 AM UTC 24 |
| Finished | Aug 21 07:30:47 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=262928378 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ ctrl_alert_test.262928378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.477747663 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3477361824 ps |
| CPU time | 10.9 seconds |
| Started | Aug 21 07:30:29 AM UTC 24 |
| Finished | Aug 21 07:30:41 AM UTC 24 |
| Peak memory | 209676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=477747663 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk _key_output.477747663 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3656972592 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 26594454337 ps |
| CPU time | 29.23 seconds |
| Started | Aug 21 07:30:37 AM UTC 24 |
| Finished | Aug 21 07:31:08 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3656972592 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ combo_detect_with_pre_cond.3656972592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3649162844 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 3360619847 ps |
| CPU time | 16.17 seconds |
| Started | Aug 21 07:30:29 AM UTC 24 |
| Finished | Aug 21 07:30:46 AM UTC 24 |
| Peak memory | 209500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36491 62844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 10.sysrst_ctrl_ec_pwr_on_rst.3649162844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.4244880177 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2609124201 ps |
| CPU time | 13.41 seconds |
| Started | Aug 21 07:30:27 AM UTC 24 |
| Finished | Aug 21 07:30:41 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4244880177 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot _out.4244880177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.2030609024 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2468365156 ps |
| CPU time | 6.63 seconds |
| Started | Aug 21 07:30:23 AM UTC 24 |
| Finished | Aug 21 07:30:31 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2030609024 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inve rted.2030609024 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.3326946401 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2148854479 ps |
| CPU time | 5.9 seconds |
| Started | Aug 21 07:30:25 AM UTC 24 |
| Finished | Aug 21 07:30:32 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3326946401 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3326946401 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.261661480 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2522734900 ps |
| CPU time | 2.42 seconds |
| Started | Aug 21 07:30:25 AM UTC 24 |
| Finished | Aug 21 07:30:28 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=261661480 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.261661480 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.622723713 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2114693884 ps |
| CPU time | 5.98 seconds |
| Started | Aug 21 07:30:18 AM UTC 24 |
| Finished | Aug 21 07:30:25 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=622723713 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.622723713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2786881650 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 7121000112 ps |
| CPU time | 33.02 seconds |
| Started | Aug 21 07:30:37 AM UTC 24 |
| Finished | Aug 21 07:31:11 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27868816 50 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sysrst_ctrl_stress_all.2786881650 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.4171979860 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 19116045130 ps |
| CPU time | 23.74 seconds |
| Started | Aug 21 07:30:37 AM UTC 24 |
| Finished | Aug 21 07:31:02 AM UTC 24 |
| Peak memory | 220552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4171979860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.4171979860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1316851708 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2010596785 ps |
| CPU time | 5.71 seconds |
| Started | Aug 21 07:31:00 AM UTC 24 |
| Finished | Aug 21 07:31:07 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1316851708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst _ctrl_alert_test.1316851708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3424335541 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2895358363 ps |
| CPU time | 12.36 seconds |
| Started | Aug 21 07:30:51 AM UTC 24 |
| Finished | Aug 21 07:31:04 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3424335541 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_bl k_key_output.3424335541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3045604764 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 26460877053 ps |
| CPU time | 47.42 seconds |
| Started | Aug 21 07:30:54 AM UTC 24 |
| Finished | Aug 21 07:31:43 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30456 04764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 11.sysrst_ctrl_combo_detect.3045604764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.107641239 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 24132645739 ps |
| CPU time | 10.88 seconds |
| Started | Aug 21 07:30:55 AM UTC 24 |
| Finished | Aug 21 07:31:07 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=107641239 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_c ombo_detect_with_pre_cond.107641239 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3465310990 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3445128555 ps |
| CPU time | 4.8 seconds |
| Started | Aug 21 07:30:47 AM UTC 24 |
| Finished | Aug 21 07:30:53 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34653 10990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.sysrst_ctrl_ec_pwr_on_rst.3465310990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.2001694163 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 3123475238 ps |
| CPU time | 9.56 seconds |
| Started | Aug 21 07:30:54 AM UTC 24 |
| Finished | Aug 21 07:31:05 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20016 94163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.sysrst_ctrl_edge_detect.2001694163 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1151296336 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2612530725 ps |
| CPU time | 9.17 seconds |
| Started | Aug 21 07:30:47 AM UTC 24 |
| Finished | Aug 21 07:30:58 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1151296336 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot _out.1151296336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3691578439 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2514105832 ps |
| CPU time | 3.74 seconds |
| Started | Aug 21 07:30:45 AM UTC 24 |
| Finished | Aug 21 07:30:50 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3691578439 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inve rted.3691578439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.4004318705 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2120344303 ps |
| CPU time | 8.04 seconds |
| Started | Aug 21 07:30:46 AM UTC 24 |
| Finished | Aug 21 07:30:56 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4004318705 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.4004318705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2351809476 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2532919571 ps |
| CPU time | 4.15 seconds |
| Started | Aug 21 07:30:47 AM UTC 24 |
| Finished | Aug 21 07:30:53 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2351809476 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_t est.2351809476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.1188842405 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2135080164 ps |
| CPU time | 2.47 seconds |
| Started | Aug 21 07:30:42 AM UTC 24 |
| Finished | Aug 21 07:30:46 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1188842405 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.1188842405 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3604626390 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 9059426524 ps |
| CPU time | 7.64 seconds |
| Started | Aug 21 07:31:00 AM UTC 24 |
| Finished | Aug 21 07:31:09 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36046263 90 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11 .sysrst_ctrl_stress_all.3604626390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3812500342 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 19580177584 ps |
| CPU time | 30.86 seconds |
| Started | Aug 21 07:30:56 AM UTC 24 |
| Finished | Aug 21 07:31:29 AM UTC 24 |
| Peak memory | 220472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3812500342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.3812500342 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3092291007 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 6145019514 ps |
| CPU time | 15.23 seconds |
| Started | Aug 21 07:30:52 AM UTC 24 |
| Finished | Aug 21 07:31:08 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30922 91007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 11.sysrst_ctrl_ultra_low_pwr.3092291007 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2913101399 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2093990708 ps |
| CPU time | 1.95 seconds |
| Started | Aug 21 07:31:11 AM UTC 24 |
| Finished | Aug 21 07:31:14 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2913101399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst _ctrl_alert_test.2913101399 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.290001557 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3206964595 ps |
| CPU time | 4.72 seconds |
| Started | Aug 21 07:31:07 AM UTC 24 |
| Finished | Aug 21 07:31:13 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290001557 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk _key_output.290001557 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3368193320 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 39520667399 ps |
| CPU time | 19.6 seconds |
| Started | Aug 21 07:31:09 AM UTC 24 |
| Finished | Aug 21 07:31:29 AM UTC 24 |
| Peak memory | 210096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33681 93320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 12.sysrst_ctrl_combo_detect.3368193320 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3219159666 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2859371631 ps |
| CPU time | 5.35 seconds |
| Started | Aug 21 07:31:05 AM UTC 24 |
| Finished | Aug 21 07:31:12 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32191 59666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 12.sysrst_ctrl_ec_pwr_on_rst.3219159666 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1771188455 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2827079158 ps |
| CPU time | 6.59 seconds |
| Started | Aug 21 07:31:09 AM UTC 24 |
| Finished | Aug 21 07:31:16 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17711 88455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.sysrst_ctrl_edge_detect.1771188455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3863237335 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2611156006 ps |
| CPU time | 11.85 seconds |
| Started | Aug 21 07:31:05 AM UTC 24 |
| Finished | Aug 21 07:31:18 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3863237335 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot _out.3863237335 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2673148284 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2438374303 ps |
| CPU time | 4.32 seconds |
| Started | Aug 21 07:31:04 AM UTC 24 |
| Finished | Aug 21 07:31:09 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2673148284 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inve rted.2673148284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.1673694653 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2094928073 ps |
| CPU time | 5.73 seconds |
| Started | Aug 21 07:31:04 AM UTC 24 |
| Finished | Aug 21 07:31:11 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1673694653 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.1673694653 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2658504924 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2543013571 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:31:05 AM UTC 24 |
| Finished | Aug 21 07:31:09 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2658504924 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_t est.2658504924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2544760042 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2112498724 ps |
| CPU time | 8.43 seconds |
| Started | Aug 21 07:31:00 AM UTC 24 |
| Finished | Aug 21 07:31:10 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2544760042 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2544760042 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.4277409510 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 15083382451 ps |
| CPU time | 11.96 seconds |
| Started | Aug 21 07:31:10 AM UTC 24 |
| Finished | Aug 21 07:31:23 AM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42774095 10 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12 .sysrst_ctrl_stress_all.4277409510 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.2856278541 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2010358480 ps |
| CPU time | 8.58 seconds |
| Started | Aug 21 07:31:24 AM UTC 24 |
| Finished | Aug 21 07:31:34 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2856278541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst _ctrl_alert_test.2856278541 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.456156920 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3459055494 ps |
| CPU time | 5.05 seconds |
| Started | Aug 21 07:31:18 AM UTC 24 |
| Finished | Aug 21 07:31:24 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456156920 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk _key_output.456156920 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1198581724 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 68697624398 ps |
| CPU time | 62.11 seconds |
| Started | Aug 21 07:31:20 AM UTC 24 |
| Finished | Aug 21 07:32:24 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11985 81724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 13.sysrst_ctrl_combo_detect.1198581724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.513725366 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2716033752 ps |
| CPU time | 2.38 seconds |
| Started | Aug 21 07:31:18 AM UTC 24 |
| Finished | Aug 21 07:31:21 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51372 5366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 13.sysrst_ctrl_ec_pwr_on_rst.513725366 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1201221789 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3274037354 ps |
| CPU time | 2.39 seconds |
| Started | Aug 21 07:31:20 AM UTC 24 |
| Finished | Aug 21 07:31:23 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12012 21789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.sysrst_ctrl_edge_detect.1201221789 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3324196772 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2609382777 ps |
| CPU time | 12.89 seconds |
| Started | Aug 21 07:31:14 AM UTC 24 |
| Finished | Aug 21 07:31:28 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324196772 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot _out.3324196772 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.2748884247 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2474975935 ps |
| CPU time | 8.61 seconds |
| Started | Aug 21 07:31:12 AM UTC 24 |
| Finished | Aug 21 07:31:22 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748884247 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inve rted.2748884247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.4030074822 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2066661219 ps |
| CPU time | 3.15 seconds |
| Started | Aug 21 07:31:12 AM UTC 24 |
| Finished | Aug 21 07:31:16 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4030074822 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.4030074822 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2509086513 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2508787706 ps |
| CPU time | 10.3 seconds |
| Started | Aug 21 07:31:14 AM UTC 24 |
| Finished | Aug 21 07:31:26 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2509086513 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_t est.2509086513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3964610396 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2113369041 ps |
| CPU time | 5.99 seconds |
| Started | Aug 21 07:31:12 AM UTC 24 |
| Finished | Aug 21 07:31:19 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3964610396 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3964610396 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.4209609884 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 8824434407 ps |
| CPU time | 10.17 seconds |
| Started | Aug 21 07:31:24 AM UTC 24 |
| Finished | Aug 21 07:31:36 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42096098 84 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13 .sysrst_ctrl_stress_all.4209609884 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1897528812 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 7746672907 ps |
| CPU time | 7.68 seconds |
| Started | Aug 21 07:31:23 AM UTC 24 |
| Finished | Aug 21 07:31:32 AM UTC 24 |
| Peak memory | 210300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1897528812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1897528812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3526502984 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4985773378927 ps |
| CPU time | 223.77 seconds |
| Started | Aug 21 07:31:19 AM UTC 24 |
| Finished | Aug 21 07:35:05 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35265 02984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 13.sysrst_ctrl_ultra_low_pwr.3526502984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.4098826826 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2014897205 ps |
| CPU time | 10.42 seconds |
| Started | Aug 21 07:31:35 AM UTC 24 |
| Finished | Aug 21 07:31:47 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4098826826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst _ctrl_alert_test.4098826826 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1740963586 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3403809347 ps |
| CPU time | 3.41 seconds |
| Started | Aug 21 07:31:30 AM UTC 24 |
| Finished | Aug 21 07:31:34 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1740963586 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_bl k_key_output.1740963586 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.2746461686 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 46745523491 ps |
| CPU time | 28.08 seconds |
| Started | Aug 21 07:31:33 AM UTC 24 |
| Finished | Aug 21 07:32:02 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27464 61686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 14.sysrst_ctrl_combo_detect.2746461686 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.698310185 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4123620006 ps |
| CPU time | 5.39 seconds |
| Started | Aug 21 07:31:30 AM UTC 24 |
| Finished | Aug 21 07:31:36 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=69831 0185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 14.sysrst_ctrl_ec_pwr_on_rst.698310185 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.10590450 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4664865553 ps |
| CPU time | 4.2 seconds |
| Started | Aug 21 07:31:33 AM UTC 24 |
| Finished | Aug 21 07:31:38 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10590 450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.10590450 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1329981577 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2690005810 ps |
| CPU time | 2.29 seconds |
| Started | Aug 21 07:31:29 AM UTC 24 |
| Finished | Aug 21 07:31:32 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1329981577 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot _out.1329981577 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.54534447 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2502851886 ps |
| CPU time | 2.46 seconds |
| Started | Aug 21 07:31:24 AM UTC 24 |
| Finished | Aug 21 07:31:28 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=54534447 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.54534447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.2999880408 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2065795127 ps |
| CPU time | 5.8 seconds |
| Started | Aug 21 07:31:26 AM UTC 24 |
| Finished | Aug 21 07:31:33 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2999880408 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2999880408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.3371939077 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2512718462 ps |
| CPU time | 11.3 seconds |
| Started | Aug 21 07:31:27 AM UTC 24 |
| Finished | Aug 21 07:31:40 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3371939077 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_t est.3371939077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1047735199 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2111843663 ps |
| CPU time | 8.17 seconds |
| Started | Aug 21 07:31:24 AM UTC 24 |
| Finished | Aug 21 07:31:34 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1047735199 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.1047735199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3575974984 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 16599291776 ps |
| CPU time | 4.39 seconds |
| Started | Aug 21 07:31:35 AM UTC 24 |
| Finished | Aug 21 07:31:41 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35759749 84 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14 .sysrst_ctrl_stress_all.3575974984 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2795582994 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3744375453 ps |
| CPU time | 6.46 seconds |
| Started | Aug 21 07:31:34 AM UTC 24 |
| Finished | Aug 21 07:31:42 AM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795582994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.2795582994 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.67571710 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4709543597 ps |
| CPU time | 3.78 seconds |
| Started | Aug 21 07:31:30 AM UTC 24 |
| Finished | Aug 21 07:31:35 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=67571 710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.sysrst_ctrl_ultra_low_pwr.67571710 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3415669737 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2032935663 ps |
| CPU time | 3.28 seconds |
| Started | Aug 21 07:31:47 AM UTC 24 |
| Finished | Aug 21 07:31:52 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415669737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst _ctrl_alert_test.3415669737 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2632339070 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 4682764943 ps |
| CPU time | 6.73 seconds |
| Started | Aug 21 07:31:41 AM UTC 24 |
| Finished | Aug 21 07:31:49 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26323 39070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sysrst_ctrl_ec_pwr_on_rst.2632339070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1465875890 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3247231007 ps |
| CPU time | 13.09 seconds |
| Started | Aug 21 07:31:43 AM UTC 24 |
| Finished | Aug 21 07:31:57 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14658 75890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.sysrst_ctrl_edge_detect.1465875890 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.393677893 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2658882594 ps |
| CPU time | 2.11 seconds |
| Started | Aug 21 07:31:40 AM UTC 24 |
| Finished | Aug 21 07:31:43 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=393677893 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_ out.393677893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.2363499131 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2497184003 ps |
| CPU time | 3.39 seconds |
| Started | Aug 21 07:31:36 AM UTC 24 |
| Finished | Aug 21 07:31:41 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2363499131 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inve rted.2363499131 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3876556617 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2108647812 ps |
| CPU time | 2.92 seconds |
| Started | Aug 21 07:31:38 AM UTC 24 |
| Finished | Aug 21 07:31:41 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3876556617 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3876556617 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.3496556549 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2529650948 ps |
| CPU time | 3.94 seconds |
| Started | Aug 21 07:31:40 AM UTC 24 |
| Finished | Aug 21 07:31:45 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496556549 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_t est.3496556549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3778266968 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2142480623 ps |
| CPU time | 2.44 seconds |
| Started | Aug 21 07:31:35 AM UTC 24 |
| Finished | Aug 21 07:31:39 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778266968 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3778266968 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1181723813 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5043956613 ps |
| CPU time | 24.34 seconds |
| Started | Aug 21 07:31:44 AM UTC 24 |
| Finished | Aug 21 07:32:10 AM UTC 24 |
| Peak memory | 227044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1181723813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1181723813 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2069851289 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3055812997 ps |
| CPU time | 3.5 seconds |
| Started | Aug 21 07:31:42 AM UTC 24 |
| Finished | Aug 21 07:31:46 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20698 51289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 15.sysrst_ctrl_ultra_low_pwr.2069851289 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.1336553865 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2023089234 ps |
| CPU time | 3.33 seconds |
| Started | Aug 21 07:32:06 AM UTC 24 |
| Finished | Aug 21 07:32:10 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1336553865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst _ctrl_alert_test.1336553865 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.186585081 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3483994717 ps |
| CPU time | 5.65 seconds |
| Started | Aug 21 07:31:58 AM UTC 24 |
| Finished | Aug 21 07:32:05 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186585081 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk _key_output.186585081 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1130799127 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 104457400093 ps |
| CPU time | 76.74 seconds |
| Started | Aug 21 07:32:00 AM UTC 24 |
| Finished | Aug 21 07:33:19 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11307 99127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 16.sysrst_ctrl_combo_detect.1130799127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.714587451 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 4845789405 ps |
| CPU time | 5.22 seconds |
| Started | Aug 21 07:31:56 AM UTC 24 |
| Finished | Aug 21 07:32:02 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=71458 7451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 16.sysrst_ctrl_ec_pwr_on_rst.714587451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1575806077 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4420138285 ps |
| CPU time | 8.44 seconds |
| Started | Aug 21 07:32:01 AM UTC 24 |
| Finished | Aug 21 07:32:11 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15758 06077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.sysrst_ctrl_edge_detect.1575806077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.4249198709 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2621132440 ps |
| CPU time | 4.38 seconds |
| Started | Aug 21 07:31:56 AM UTC 24 |
| Finished | Aug 21 07:32:01 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4249198709 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot _out.4249198709 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.1551387542 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2489536328 ps |
| CPU time | 4.4 seconds |
| Started | Aug 21 07:31:50 AM UTC 24 |
| Finished | Aug 21 07:31:55 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1551387542 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inve rted.1551387542 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2844478430 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2209644764 ps |
| CPU time | 11.36 seconds |
| Started | Aug 21 07:31:53 AM UTC 24 |
| Finished | Aug 21 07:32:05 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2844478430 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2844478430 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3737286875 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2547888870 ps |
| CPU time | 2.92 seconds |
| Started | Aug 21 07:31:56 AM UTC 24 |
| Finished | Aug 21 07:32:00 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737286875 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_t est.3737286875 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1315712070 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2110608974 ps |
| CPU time | 12.11 seconds |
| Started | Aug 21 07:31:47 AM UTC 24 |
| Finished | Aug 21 07:32:01 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1315712070 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1315712070 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1769775533 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 9182518915 ps |
| CPU time | 3.75 seconds |
| Started | Aug 21 07:32:03 AM UTC 24 |
| Finished | Aug 21 07:32:08 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17697755 33 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sysrst_ctrl_stress_all.1769775533 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.420174145 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4119087778 ps |
| CPU time | 16.19 seconds |
| Started | Aug 21 07:32:03 AM UTC 24 |
| Finished | Aug 21 07:32:21 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=420174145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.420174145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.4201773390 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2028601032 ps |
| CPU time | 2.44 seconds |
| Started | Aug 21 07:32:17 AM UTC 24 |
| Finished | Aug 21 07:32:20 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4201773390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst _ctrl_alert_test.4201773390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.424669750 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 3613327036 ps |
| CPU time | 7.33 seconds |
| Started | Aug 21 07:32:12 AM UTC 24 |
| Finished | Aug 21 07:32:21 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=424669750 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk _key_output.424669750 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2305216431 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 160824597866 ps |
| CPU time | 231.95 seconds |
| Started | Aug 21 07:32:12 AM UTC 24 |
| Finished | Aug 21 07:36:07 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23052 16431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 17.sysrst_ctrl_combo_detect.2305216431 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1428020036 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 38511323032 ps |
| CPU time | 32.99 seconds |
| Started | Aug 21 07:32:15 AM UTC 24 |
| Finished | Aug 21 07:32:49 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1428020036 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ combo_detect_with_pre_cond.1428020036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3240595014 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 4463326099 ps |
| CPU time | 8.46 seconds |
| Started | Aug 21 07:32:11 AM UTC 24 |
| Finished | Aug 21 07:32:21 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32405 95014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sysrst_ctrl_ec_pwr_on_rst.3240595014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.2940819637 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2778933210 ps |
| CPU time | 6.63 seconds |
| Started | Aug 21 07:32:14 AM UTC 24 |
| Finished | Aug 21 07:32:21 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29408 19637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.sysrst_ctrl_edge_detect.2940819637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2026112996 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2617664309 ps |
| CPU time | 4.46 seconds |
| Started | Aug 21 07:32:11 AM UTC 24 |
| Finished | Aug 21 07:32:17 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026112996 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot _out.2026112996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3854128457 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2477565262 ps |
| CPU time | 4.05 seconds |
| Started | Aug 21 07:32:09 AM UTC 24 |
| Finished | Aug 21 07:32:14 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3854128457 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inve rted.3854128457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1249974987 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2151421219 ps |
| CPU time | 3.45 seconds |
| Started | Aug 21 07:32:10 AM UTC 24 |
| Finished | Aug 21 07:32:14 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1249974987 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1249974987 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.2301600138 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2514741670 ps |
| CPU time | 12.06 seconds |
| Started | Aug 21 07:32:11 AM UTC 24 |
| Finished | Aug 21 07:32:24 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2301600138 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_t est.2301600138 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.4072917025 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2142985319 ps |
| CPU time | 2.52 seconds |
| Started | Aug 21 07:32:06 AM UTC 24 |
| Finished | Aug 21 07:32:09 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4072917025 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.4072917025 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1184099841 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 9474469309 ps |
| CPU time | 12.72 seconds |
| Started | Aug 21 07:32:16 AM UTC 24 |
| Finished | Aug 21 07:32:30 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11840998 41 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17 .sysrst_ctrl_stress_all.1184099841 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2624310152 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 6794158651 ps |
| CPU time | 8.7 seconds |
| Started | Aug 21 07:32:16 AM UTC 24 |
| Finished | Aug 21 07:32:25 AM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2624310152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2624310152 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1801459612 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 5299704961 ps |
| CPU time | 2.18 seconds |
| Started | Aug 21 07:32:12 AM UTC 24 |
| Finished | Aug 21 07:32:16 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18014 59612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 17.sysrst_ctrl_ultra_low_pwr.1801459612 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.556411527 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2030595289 ps |
| CPU time | 3.1 seconds |
| Started | Aug 21 07:32:28 AM UTC 24 |
| Finished | Aug 21 07:32:32 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556411527 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ ctrl_alert_test.556411527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.593405636 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 275358708721 ps |
| CPU time | 182 seconds |
| Started | Aug 21 07:32:22 AM UTC 24 |
| Finished | Aug 21 07:35:27 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=593405636 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk _key_output.593405636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.2574464868 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 115872895449 ps |
| CPU time | 178.14 seconds |
| Started | Aug 21 07:32:25 AM UTC 24 |
| Finished | Aug 21 07:35:26 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25744 64868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 18.sysrst_ctrl_combo_detect.2574464868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3676794026 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 49453915132 ps |
| CPU time | 36.92 seconds |
| Started | Aug 21 07:32:27 AM UTC 24 |
| Finished | Aug 21 07:33:05 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3676794026 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ combo_detect_with_pre_cond.3676794026 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.511665160 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 4604385452 ps |
| CPU time | 21.69 seconds |
| Started | Aug 21 07:32:22 AM UTC 24 |
| Finished | Aug 21 07:32:45 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51166 5160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 18.sysrst_ctrl_ec_pwr_on_rst.511665160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2245812208 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 5793903939 ps |
| CPU time | 18.39 seconds |
| Started | Aug 21 07:32:26 AM UTC 24 |
| Finished | Aug 21 07:32:45 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22458 12208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.sysrst_ctrl_edge_detect.2245812208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3840450089 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2635498114 ps |
| CPU time | 2.86 seconds |
| Started | Aug 21 07:32:22 AM UTC 24 |
| Finished | Aug 21 07:32:26 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3840450089 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot _out.3840450089 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.4139849455 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2492562800 ps |
| CPU time | 2.36 seconds |
| Started | Aug 21 07:32:21 AM UTC 24 |
| Finished | Aug 21 07:32:24 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4139849455 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inve rted.4139849455 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.344816985 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2195899524 ps |
| CPU time | 6.07 seconds |
| Started | Aug 21 07:32:21 AM UTC 24 |
| Finished | Aug 21 07:32:28 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344816985 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.344816985 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.830560422 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2540099892 ps |
| CPU time | 3.54 seconds |
| Started | Aug 21 07:32:22 AM UTC 24 |
| Finished | Aug 21 07:32:27 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830560422 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.830560422 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3705412834 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2110861136 ps |
| CPU time | 8.17 seconds |
| Started | Aug 21 07:32:18 AM UTC 24 |
| Finished | Aug 21 07:32:27 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3705412834 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3705412834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.799723222 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 4404402067 ps |
| CPU time | 27.73 seconds |
| Started | Aug 21 07:32:27 AM UTC 24 |
| Finished | Aug 21 07:32:56 AM UTC 24 |
| Peak memory | 220804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=799723222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.799723222 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2643299554 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4089154228 ps |
| CPU time | 2.46 seconds |
| Started | Aug 21 07:32:24 AM UTC 24 |
| Finished | Aug 21 07:32:28 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26432 99554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 18.sysrst_ctrl_ultra_low_pwr.2643299554 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2392824523 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2035565265 ps |
| CPU time | 3.48 seconds |
| Started | Aug 21 07:32:43 AM UTC 24 |
| Finished | Aug 21 07:32:48 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392824523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst _ctrl_alert_test.2392824523 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3525339818 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 4092415763 ps |
| CPU time | 2.13 seconds |
| Started | Aug 21 07:32:35 AM UTC 24 |
| Finished | Aug 21 07:32:39 AM UTC 24 |
| Peak memory | 210212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525339818 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_bl k_key_output.3525339818 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.1399949311 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 63394678998 ps |
| CPU time | 182.6 seconds |
| Started | Aug 21 07:32:40 AM UTC 24 |
| Finished | Aug 21 07:35:45 AM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13999 49311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 19.sysrst_ctrl_combo_detect.1399949311 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.14334938 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3410424301 ps |
| CPU time | 3.81 seconds |
| Started | Aug 21 07:32:33 AM UTC 24 |
| Finished | Aug 21 07:32:38 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14334 938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.sysrst_ctrl_ec_pwr_on_rst.14334938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.3283793619 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2581532241 ps |
| CPU time | 3.79 seconds |
| Started | Aug 21 07:32:40 AM UTC 24 |
| Finished | Aug 21 07:32:45 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32837 93619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.sysrst_ctrl_edge_detect.3283793619 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3961721209 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2619689217 ps |
| CPU time | 3.7 seconds |
| Started | Aug 21 07:32:32 AM UTC 24 |
| Finished | Aug 21 07:32:37 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961721209 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot _out.3961721209 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2562472966 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2508751719 ps |
| CPU time | 2.17 seconds |
| Started | Aug 21 07:32:29 AM UTC 24 |
| Finished | Aug 21 07:32:32 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2562472966 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inve rted.2562472966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3836841668 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2051712799 ps |
| CPU time | 9.98 seconds |
| Started | Aug 21 07:32:29 AM UTC 24 |
| Finished | Aug 21 07:32:40 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836841668 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3836841668 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2214900356 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2537846375 ps |
| CPU time | 2.65 seconds |
| Started | Aug 21 07:32:30 AM UTC 24 |
| Finished | Aug 21 07:32:34 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2214900356 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_t est.2214900356 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.1823871472 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2109772260 ps |
| CPU time | 9.86 seconds |
| Started | Aug 21 07:32:28 AM UTC 24 |
| Finished | Aug 21 07:32:39 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1823871472 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1823871472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2023891015 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 214002042171 ps |
| CPU time | 597.43 seconds |
| Started | Aug 21 07:32:41 AM UTC 24 |
| Finished | Aug 21 07:42:45 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20238910 15 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19 .sysrst_ctrl_stress_all.2023891015 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1667713532 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 758783924776 ps |
| CPU time | 19.74 seconds |
| Started | Aug 21 07:32:40 AM UTC 24 |
| Finished | Aug 21 07:33:01 AM UTC 24 |
| Peak memory | 220484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667713532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.1667713532 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2038083112 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 4904505723 ps |
| CPU time | 3.61 seconds |
| Started | Aug 21 07:32:37 AM UTC 24 |
| Finished | Aug 21 07:32:42 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20380 83112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 19.sysrst_ctrl_ultra_low_pwr.2038083112 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.104176559 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2014038186 ps |
| CPU time | 5.13 seconds |
| Started | Aug 21 07:27:28 AM UTC 24 |
| Finished | Aug 21 07:27:35 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=104176559 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c trl_alert_test.104176559 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3268795654 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3197553384 ps |
| CPU time | 3.95 seconds |
| Started | Aug 21 07:27:21 AM UTC 24 |
| Finished | Aug 21 07:27:26 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3268795654 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk _key_output.3268795654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1651125296 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2391857688 ps |
| CPU time | 4.56 seconds |
| Started | Aug 21 07:27:15 AM UTC 24 |
| Finished | Aug 21 07:27:21 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1651125296 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de tect_ec_rst.1651125296 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1718763669 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2315422294 ps |
| CPU time | 3.68 seconds |
| Started | Aug 21 07:27:15 AM UTC 24 |
| Finished | Aug 21 07:27:20 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1718763669 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst _ctrl_combo_detect_ec_rst_with_pre_cond.1718763669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3456414872 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 26365374975 ps |
| CPU time | 26.83 seconds |
| Started | Aug 21 07:27:28 AM UTC 24 |
| Finished | Aug 21 07:27:57 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3456414872 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_c ombo_detect_with_pre_cond.3456414872 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1845933514 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4161765995 ps |
| CPU time | 20.84 seconds |
| Started | Aug 21 07:27:21 AM UTC 24 |
| Finished | Aug 21 07:27:43 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18459 33514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.sysrst_ctrl_ec_pwr_on_rst.1845933514 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2700824379 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2640399766 ps |
| CPU time | 5.17 seconds |
| Started | Aug 21 07:27:24 AM UTC 24 |
| Finished | Aug 21 07:27:30 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27008 24379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.sysrst_ctrl_edge_detect.2700824379 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3435110959 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2623814779 ps |
| CPU time | 3.99 seconds |
| Started | Aug 21 07:27:18 AM UTC 24 |
| Finished | Aug 21 07:27:23 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435110959 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_ out.3435110959 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.1597063713 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2479957134 ps |
| CPU time | 11.98 seconds |
| Started | Aug 21 07:27:12 AM UTC 24 |
| Finished | Aug 21 07:27:25 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597063713 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inver ted.1597063713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.1670044114 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2237501356 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 07:27:15 AM UTC 24 |
| Finished | Aug 21 07:27:20 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1670044114 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.1670044114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2537070758 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 42556598688 ps |
| CPU time | 53.02 seconds |
| Started | Aug 21 07:27:28 AM UTC 24 |
| Finished | Aug 21 07:28:23 AM UTC 24 |
| Peak memory | 238240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2537070758 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c trl_sec_cm.2537070758 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3992219947 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2135383726 ps |
| CPU time | 3.82 seconds |
| Started | Aug 21 07:27:08 AM UTC 24 |
| Finished | Aug 21 07:27:13 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3992219947 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3992219947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3509216127 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5225640610 ps |
| CPU time | 16.56 seconds |
| Started | Aug 21 07:27:28 AM UTC 24 |
| Finished | Aug 21 07:27:46 AM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3509216127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.3509216127 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.3789969062 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2017995339 ps |
| CPU time | 5.56 seconds |
| Started | Aug 21 07:33:00 AM UTC 24 |
| Finished | Aug 21 07:33:07 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3789969062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst _ctrl_alert_test.3789969062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1792331983 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3455725561 ps |
| CPU time | 4.88 seconds |
| Started | Aug 21 07:32:54 AM UTC 24 |
| Finished | Aug 21 07:33:00 AM UTC 24 |
| Peak memory | 209956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1792331983 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_bl k_key_output.1792331983 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1765751528 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 82249051135 ps |
| CPU time | 47.02 seconds |
| Started | Aug 21 07:32:56 AM UTC 24 |
| Finished | Aug 21 07:33:44 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17657 51528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 20.sysrst_ctrl_combo_detect.1765751528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1091286768 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 61800846493 ps |
| CPU time | 184.33 seconds |
| Started | Aug 21 07:32:57 AM UTC 24 |
| Finished | Aug 21 07:36:04 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1091286768 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ combo_detect_with_pre_cond.1091286768 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3827572591 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3973034855 ps |
| CPU time | 6.49 seconds |
| Started | Aug 21 07:32:50 AM UTC 24 |
| Finished | Aug 21 07:32:57 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38275 72591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 20.sysrst_ctrl_ec_pwr_on_rst.3827572591 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.967214 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4303170634 ps |
| CPU time | 16.71 seconds |
| Started | Aug 21 07:32:57 AM UTC 24 |
| Finished | Aug 21 07:33:15 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=96721 4 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sysrst_ctrl_edge_detect.967214 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.186795092 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2614256323 ps |
| CPU time | 10.38 seconds |
| Started | Aug 21 07:32:49 AM UTC 24 |
| Finished | Aug 21 07:33:00 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186795092 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_ out.186795092 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2039814870 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2462664081 ps |
| CPU time | 7.15 seconds |
| Started | Aug 21 07:32:46 AM UTC 24 |
| Finished | Aug 21 07:32:55 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2039814870 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inve rted.2039814870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.4218415116 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2246137157 ps |
| CPU time | 5.57 seconds |
| Started | Aug 21 07:32:46 AM UTC 24 |
| Finished | Aug 21 07:32:53 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4218415116 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.4218415116 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3982175764 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2514704613 ps |
| CPU time | 6.41 seconds |
| Started | Aug 21 07:32:49 AM UTC 24 |
| Finished | Aug 21 07:32:56 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982175764 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_t est.3982175764 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.3012420347 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2107798100 ps |
| CPU time | 6.13 seconds |
| Started | Aug 21 07:32:45 AM UTC 24 |
| Finished | Aug 21 07:32:52 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012420347 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.3012420347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2413952936 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 84327706564 ps |
| CPU time | 66.74 seconds |
| Started | Aug 21 07:33:00 AM UTC 24 |
| Finished | Aug 21 07:34:09 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24139529 36 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20 .sysrst_ctrl_stress_all.2413952936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.2540949276 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 13628032691 ps |
| CPU time | 11.9 seconds |
| Started | Aug 21 07:32:58 AM UTC 24 |
| Finished | Aug 21 07:33:11 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540949276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.2540949276 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.617299552 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 9558146918 ps |
| CPU time | 4.95 seconds |
| Started | Aug 21 07:32:54 AM UTC 24 |
| Finished | Aug 21 07:33:00 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=61729 9552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 20.sysrst_ctrl_ultra_low_pwr.617299552 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.2748720200 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2017243591 ps |
| CPU time | 5.71 seconds |
| Started | Aug 21 07:33:30 AM UTC 24 |
| Finished | Aug 21 07:33:36 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2748720200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst _ctrl_alert_test.2748720200 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1069795098 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2973884946 ps |
| CPU time | 5.41 seconds |
| Started | Aug 21 07:33:24 AM UTC 24 |
| Finished | Aug 21 07:33:30 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1069795098 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_bl k_key_output.1069795098 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2356812390 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 119360342961 ps |
| CPU time | 142.23 seconds |
| Started | Aug 21 07:33:24 AM UTC 24 |
| Finished | Aug 21 07:35:49 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23568 12390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 21.sysrst_ctrl_combo_detect.2356812390 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1003248376 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 59267086309 ps |
| CPU time | 120.84 seconds |
| Started | Aug 21 07:33:25 AM UTC 24 |
| Finished | Aug 21 07:35:28 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1003248376 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ combo_detect_with_pre_cond.1003248376 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3130168870 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2900964539 ps |
| CPU time | 7.4 seconds |
| Started | Aug 21 07:33:24 AM UTC 24 |
| Finished | Aug 21 07:33:32 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31301 68870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sysrst_ctrl_ec_pwr_on_rst.3130168870 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2183142881 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3277128221 ps |
| CPU time | 6.58 seconds |
| Started | Aug 21 07:33:25 AM UTC 24 |
| Finished | Aug 21 07:33:33 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21831 42881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.sysrst_ctrl_edge_detect.2183142881 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3447083404 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2627311539 ps |
| CPU time | 3.72 seconds |
| Started | Aug 21 07:33:24 AM UTC 24 |
| Finished | Aug 21 07:33:29 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447083404 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot _out.3447083404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1903628179 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2457803294 ps |
| CPU time | 7.52 seconds |
| Started | Aug 21 07:33:01 AM UTC 24 |
| Finished | Aug 21 07:33:10 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1903628179 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inve rted.1903628179 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1620077145 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2018445363 ps |
| CPU time | 10.34 seconds |
| Started | Aug 21 07:33:13 AM UTC 24 |
| Finished | Aug 21 07:33:24 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1620077145 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1620077145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1293665873 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2512663726 ps |
| CPU time | 11.63 seconds |
| Started | Aug 21 07:33:24 AM UTC 24 |
| Finished | Aug 21 07:33:36 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1293665873 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_t est.1293665873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.472625975 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2111647757 ps |
| CPU time | 9.91 seconds |
| Started | Aug 21 07:33:01 AM UTC 24 |
| Finished | Aug 21 07:33:12 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=472625975 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.472625975 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.2322161907 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 10197271543 ps |
| CPU time | 16.23 seconds |
| Started | Aug 21 07:33:25 AM UTC 24 |
| Finished | Aug 21 07:33:43 AM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23221619 07 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21 .sysrst_ctrl_stress_all.2322161907 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1585042619 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 14015696499 ps |
| CPU time | 16.29 seconds |
| Started | Aug 21 07:33:25 AM UTC 24 |
| Finished | Aug 21 07:33:43 AM UTC 24 |
| Peak memory | 220552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1585042619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.1585042619 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.485904912 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 6846851747 ps |
| CPU time | 3.88 seconds |
| Started | Aug 21 07:33:24 AM UTC 24 |
| Finished | Aug 21 07:33:29 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48590 4912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 21.sysrst_ctrl_ultra_low_pwr.485904912 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.2595160581 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2018274261 ps |
| CPU time | 6.55 seconds |
| Started | Aug 21 07:33:46 AM UTC 24 |
| Finished | Aug 21 07:33:53 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595160581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst _ctrl_alert_test.2595160581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.4277821966 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3411275880 ps |
| CPU time | 4.27 seconds |
| Started | Aug 21 07:33:39 AM UTC 24 |
| Finished | Aug 21 07:33:44 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4277821966 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_bl k_key_output.4277821966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.100577807 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 155626261966 ps |
| CPU time | 429.87 seconds |
| Started | Aug 21 07:33:43 AM UTC 24 |
| Finished | Aug 21 07:40:58 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10057 7807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.sysrst_ctrl_combo_detect.100577807 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2670172204 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 67307178865 ps |
| CPU time | 228.18 seconds |
| Started | Aug 21 07:33:46 AM UTC 24 |
| Finished | Aug 21 07:37:37 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2670172204 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ combo_detect_with_pre_cond.2670172204 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1187664168 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 4357643181 ps |
| CPU time | 22.06 seconds |
| Started | Aug 21 07:33:37 AM UTC 24 |
| Finished | Aug 21 07:34:00 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11876 64168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sysrst_ctrl_ec_pwr_on_rst.1187664168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3157092694 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3135441053 ps |
| CPU time | 5.18 seconds |
| Started | Aug 21 07:33:43 AM UTC 24 |
| Finished | Aug 21 07:33:50 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31570 92694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.sysrst_ctrl_edge_detect.3157092694 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.850469804 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2610490804 ps |
| CPU time | 10.39 seconds |
| Started | Aug 21 07:33:37 AM UTC 24 |
| Finished | Aug 21 07:33:49 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=850469804 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_ out.850469804 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3954514623 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2469953044 ps |
| CPU time | 6.76 seconds |
| Started | Aug 21 07:33:31 AM UTC 24 |
| Finished | Aug 21 07:33:39 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3954514623 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inve rted.3954514623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2885419386 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2094269028 ps |
| CPU time | 10.86 seconds |
| Started | Aug 21 07:33:33 AM UTC 24 |
| Finished | Aug 21 07:33:45 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2885419386 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2885419386 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.835148050 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2508438147 ps |
| CPU time | 13.38 seconds |
| Started | Aug 21 07:33:34 AM UTC 24 |
| Finished | Aug 21 07:33:48 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=835148050 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.835148050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1853426836 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2112904034 ps |
| CPU time | 10.33 seconds |
| Started | Aug 21 07:33:30 AM UTC 24 |
| Finished | Aug 21 07:33:41 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1853426836 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1853426836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.212873193 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 8804989956 ps |
| CPU time | 12.9 seconds |
| Started | Aug 21 07:33:46 AM UTC 24 |
| Finished | Aug 21 07:34:00 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21287319 3 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22. sysrst_ctrl_stress_all.212873193 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1176201861 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 6158441355 ps |
| CPU time | 27.29 seconds |
| Started | Aug 21 07:33:46 AM UTC 24 |
| Finished | Aug 21 07:34:14 AM UTC 24 |
| Peak memory | 220468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1176201861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.1176201861 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2556659762 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 7266805374 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:33:42 AM UTC 24 |
| Finished | Aug 21 07:33:45 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25566 59762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 22.sysrst_ctrl_ultra_low_pwr.2556659762 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.4042510972 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2033037054 ps |
| CPU time | 2.89 seconds |
| Started | Aug 21 07:34:05 AM UTC 24 |
| Finished | Aug 21 07:34:09 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4042510972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst _ctrl_alert_test.4042510972 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3594838266 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3571832634 ps |
| CPU time | 21.87 seconds |
| Started | Aug 21 07:33:57 AM UTC 24 |
| Finished | Aug 21 07:34:20 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594838266 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_bl k_key_output.3594838266 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2778327570 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 121144738810 ps |
| CPU time | 401.14 seconds |
| Started | Aug 21 07:34:01 AM UTC 24 |
| Finished | Aug 21 07:40:47 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27783 27570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 23.sysrst_ctrl_combo_detect.2778327570 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2010227445 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 56861227971 ps |
| CPU time | 148.84 seconds |
| Started | Aug 21 07:34:04 AM UTC 24 |
| Finished | Aug 21 07:36:35 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2010227445 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ combo_detect_with_pre_cond.2010227445 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.161215415 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 4140378229 ps |
| CPU time | 5.68 seconds |
| Started | Aug 21 07:33:56 AM UTC 24 |
| Finished | Aug 21 07:34:03 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16121 5415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 23.sysrst_ctrl_ec_pwr_on_rst.161215415 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.3481513197 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4954317959 ps |
| CPU time | 9.18 seconds |
| Started | Aug 21 07:34:02 AM UTC 24 |
| Finished | Aug 21 07:34:12 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34815 13197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.sysrst_ctrl_edge_detect.3481513197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.360173783 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2610902773 ps |
| CPU time | 8.76 seconds |
| Started | Aug 21 07:33:54 AM UTC 24 |
| Finished | Aug 21 07:34:04 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360173783 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_ out.360173783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3656604010 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2468313525 ps |
| CPU time | 7.26 seconds |
| Started | Aug 21 07:33:49 AM UTC 24 |
| Finished | Aug 21 07:33:57 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3656604010 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inve rted.3656604010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.3447704880 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2277124416 ps |
| CPU time | 4.56 seconds |
| Started | Aug 21 07:33:50 AM UTC 24 |
| Finished | Aug 21 07:33:56 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447704880 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3447704880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3528886831 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2539736199 ps |
| CPU time | 3.46 seconds |
| Started | Aug 21 07:33:52 AM UTC 24 |
| Finished | Aug 21 07:33:57 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3528886831 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_t est.3528886831 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.578458895 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2261991201 ps |
| CPU time | 1.27 seconds |
| Started | Aug 21 07:33:49 AM UTC 24 |
| Finished | Aug 21 07:33:51 AM UTC 24 |
| Peak memory | 207832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=578458895 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.578458895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1221197316 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 6663757837 ps |
| CPU time | 6.75 seconds |
| Started | Aug 21 07:34:04 AM UTC 24 |
| Finished | Aug 21 07:34:12 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12211973 16 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23 .sysrst_ctrl_stress_all.1221197316 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2902248656 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3728374454 ps |
| CPU time | 21.23 seconds |
| Started | Aug 21 07:34:04 AM UTC 24 |
| Finished | Aug 21 07:34:26 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2902248656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2902248656 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.842444931 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3264348199 ps |
| CPU time | 3.6 seconds |
| Started | Aug 21 07:33:58 AM UTC 24 |
| Finished | Aug 21 07:34:03 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=84244 4931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 23.sysrst_ctrl_ultra_low_pwr.842444931 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2600288551 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2023273296 ps |
| CPU time | 5.96 seconds |
| Started | Aug 21 07:34:29 AM UTC 24 |
| Finished | Aug 21 07:34:36 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2600288551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst _ctrl_alert_test.2600288551 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2539956295 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3717323937 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 07:34:15 AM UTC 24 |
| Finished | Aug 21 07:34:19 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2539956295 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_bl k_key_output.2539956295 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.2878608230 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 135313387623 ps |
| CPU time | 121.06 seconds |
| Started | Aug 21 07:34:17 AM UTC 24 |
| Finished | Aug 21 07:36:21 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28786 08230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 24.sysrst_ctrl_combo_detect.2878608230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4015407290 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3115757317 ps |
| CPU time | 5.09 seconds |
| Started | Aug 21 07:34:14 AM UTC 24 |
| Finished | Aug 21 07:34:20 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40154 07290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.sysrst_ctrl_ec_pwr_on_rst.4015407290 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3851362102 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1368611000986 ps |
| CPU time | 913.43 seconds |
| Started | Aug 21 07:34:19 AM UTC 24 |
| Finished | Aug 21 07:49:42 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38513 62102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.sysrst_ctrl_edge_detect.3851362102 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2803773284 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2614153555 ps |
| CPU time | 9.86 seconds |
| Started | Aug 21 07:34:13 AM UTC 24 |
| Finished | Aug 21 07:34:24 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2803773284 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot _out.2803773284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.3495425952 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2459658210 ps |
| CPU time | 14.3 seconds |
| Started | Aug 21 07:34:10 AM UTC 24 |
| Finished | Aug 21 07:34:25 AM UTC 24 |
| Peak memory | 209756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3495425952 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inve rted.3495425952 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3416574880 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2061359116 ps |
| CPU time | 3.84 seconds |
| Started | Aug 21 07:34:10 AM UTC 24 |
| Finished | Aug 21 07:34:15 AM UTC 24 |
| Peak memory | 209148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416574880 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3416574880 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.404448991 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2556434262 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:34:13 AM UTC 24 |
| Finished | Aug 21 07:34:16 AM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=404448991 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.404448991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1021940005 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2131185570 ps |
| CPU time | 3.38 seconds |
| Started | Aug 21 07:34:09 AM UTC 24 |
| Finished | Aug 21 07:34:13 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1021940005 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1021940005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.226529251 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 44905798187 ps |
| CPU time | 157.94 seconds |
| Started | Aug 21 07:34:29 AM UTC 24 |
| Finished | Aug 21 07:37:09 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22652925 1 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24. sysrst_ctrl_stress_all.226529251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1718074254 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 13830890577 ps |
| CPU time | 9.77 seconds |
| Started | Aug 21 07:34:29 AM UTC 24 |
| Finished | Aug 21 07:34:40 AM UTC 24 |
| Peak memory | 220484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1718074254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1718074254 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1965010919 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 7338100922 ps |
| CPU time | 14.05 seconds |
| Started | Aug 21 07:34:15 AM UTC 24 |
| Finished | Aug 21 07:34:31 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19650 10919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 24.sysrst_ctrl_ultra_low_pwr.1965010919 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2809851302 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2017008245 ps |
| CPU time | 8.08 seconds |
| Started | Aug 21 07:34:50 AM UTC 24 |
| Finished | Aug 21 07:34:59 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809851302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst _ctrl_alert_test.2809851302 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4264518585 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 329901092827 ps |
| CPU time | 914.6 seconds |
| Started | Aug 21 07:34:41 AM UTC 24 |
| Finished | Aug 21 07:50:05 AM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4264518585 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_bl k_key_output.4264518585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.4129487717 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 214762265922 ps |
| CPU time | 121.04 seconds |
| Started | Aug 21 07:34:41 AM UTC 24 |
| Finished | Aug 21 07:36:45 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41294 87717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 25.sysrst_ctrl_combo_detect.4129487717 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.14888834 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 60056117591 ps |
| CPU time | 177.35 seconds |
| Started | Aug 21 07:34:42 AM UTC 24 |
| Finished | Aug 21 07:37:42 AM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14888834 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_co mbo_detect_with_pre_cond.14888834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.183287597 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 5145293398 ps |
| CPU time | 21.72 seconds |
| Started | Aug 21 07:34:41 AM UTC 24 |
| Finished | Aug 21 07:35:04 AM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18328 7597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 25.sysrst_ctrl_ec_pwr_on_rst.183287597 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.204681672 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3944206331 ps |
| CPU time | 6.3 seconds |
| Started | Aug 21 07:34:42 AM UTC 24 |
| Finished | Aug 21 07:34:49 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20468 1672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.204681672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3056500571 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2627504867 ps |
| CPU time | 4.82 seconds |
| Started | Aug 21 07:34:34 AM UTC 24 |
| Finished | Aug 21 07:34:41 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3056500571 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot _out.3056500571 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3244117555 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2478583840 ps |
| CPU time | 12.74 seconds |
| Started | Aug 21 07:34:29 AM UTC 24 |
| Finished | Aug 21 07:34:43 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3244117555 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inve rted.3244117555 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3793485169 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 2286191575 ps |
| CPU time | 3.71 seconds |
| Started | Aug 21 07:34:31 AM UTC 24 |
| Finished | Aug 21 07:34:36 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3793485169 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3793485169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.302382902 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2531803864 ps |
| CPU time | 3.99 seconds |
| Started | Aug 21 07:34:31 AM UTC 24 |
| Finished | Aug 21 07:34:36 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=302382902 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.302382902 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.242583351 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2122282670 ps |
| CPU time | 3.24 seconds |
| Started | Aug 21 07:34:29 AM UTC 24 |
| Finished | Aug 21 07:34:33 AM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242583351 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.242583351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3726809895 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 12799426516 ps |
| CPU time | 10.69 seconds |
| Started | Aug 21 07:34:50 AM UTC 24 |
| Finished | Aug 21 07:35:02 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37268098 95 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25 .sysrst_ctrl_stress_all.3726809895 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2564182478 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5447934750 ps |
| CPU time | 11.13 seconds |
| Started | Aug 21 07:34:50 AM UTC 24 |
| Finished | Aug 21 07:35:03 AM UTC 24 |
| Peak memory | 220412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2564182478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2564182478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4138048461 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3188902916 ps |
| CPU time | 3.32 seconds |
| Started | Aug 21 07:34:41 AM UTC 24 |
| Finished | Aug 21 07:34:46 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41380 48461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 25.sysrst_ctrl_ultra_low_pwr.4138048461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.825312580 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2010149077 ps |
| CPU time | 7.15 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:31 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=825312580 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ ctrl_alert_test.825312580 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3443057238 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3654419333 ps |
| CPU time | 19.3 seconds |
| Started | Aug 21 07:35:01 AM UTC 24 |
| Finished | Aug 21 07:35:21 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443057238 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_bl k_key_output.3443057238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.1605556296 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 52950512143 ps |
| CPU time | 156.97 seconds |
| Started | Aug 21 07:35:03 AM UTC 24 |
| Finished | Aug 21 07:37:42 AM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16055 56296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 26.sysrst_ctrl_combo_detect.1605556296 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.392634284 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 24336425525 ps |
| CPU time | 53.65 seconds |
| Started | Aug 21 07:35:05 AM UTC 24 |
| Finished | Aug 21 07:36:00 AM UTC 24 |
| Peak memory | 210636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=392634284 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_c ombo_detect_with_pre_cond.392634284 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1746240477 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2506865545 ps |
| CPU time | 3.81 seconds |
| Started | Aug 21 07:35:01 AM UTC 24 |
| Finished | Aug 21 07:35:06 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17462 40477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 26.sysrst_ctrl_ec_pwr_on_rst.1746240477 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.823987765 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3589173578 ps |
| CPU time | 4.27 seconds |
| Started | Aug 21 07:35:03 AM UTC 24 |
| Finished | Aug 21 07:35:08 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=82398 7765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.823987765 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3878693901 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2610609910 ps |
| CPU time | 12.28 seconds |
| Started | Aug 21 07:34:58 AM UTC 24 |
| Finished | Aug 21 07:35:11 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3878693901 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot _out.3878693901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1575677815 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2485379634 ps |
| CPU time | 3.99 seconds |
| Started | Aug 21 07:34:50 AM UTC 24 |
| Finished | Aug 21 07:34:55 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1575677815 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inve rted.1575677815 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.665150045 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2135726842 ps |
| CPU time | 3.12 seconds |
| Started | Aug 21 07:34:53 AM UTC 24 |
| Finished | Aug 21 07:34:57 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=665150045 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.665150045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.4148019174 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2552795172 ps |
| CPU time | 2.42 seconds |
| Started | Aug 21 07:34:57 AM UTC 24 |
| Finished | Aug 21 07:35:00 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4148019174 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_t est.4148019174 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.4039585887 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2113779229 ps |
| CPU time | 9.94 seconds |
| Started | Aug 21 07:34:50 AM UTC 24 |
| Finished | Aug 21 07:35:01 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4039585887 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.4039585887 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1999892965 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 9318716124 ps |
| CPU time | 12.51 seconds |
| Started | Aug 21 07:35:06 AM UTC 24 |
| Finished | Aug 21 07:35:20 AM UTC 24 |
| Peak memory | 222588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1999892965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1999892965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.730411878 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 5546670256 ps |
| CPU time | 3.19 seconds |
| Started | Aug 21 07:35:02 AM UTC 24 |
| Finished | Aug 21 07:35:06 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73041 1878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 26.sysrst_ctrl_ultra_low_pwr.730411878 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1146253105 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2068879560 ps |
| CPU time | 2.68 seconds |
| Started | Aug 21 07:35:30 AM UTC 24 |
| Finished | Aug 21 07:35:34 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1146253105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst _ctrl_alert_test.1146253105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.3045303344 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 89596418762 ps |
| CPU time | 28.96 seconds |
| Started | Aug 21 07:35:27 AM UTC 24 |
| Finished | Aug 21 07:35:57 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30453 03344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 27.sysrst_ctrl_combo_detect.3045303344 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3486798145 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 35685684172 ps |
| CPU time | 25.62 seconds |
| Started | Aug 21 07:35:30 AM UTC 24 |
| Finished | Aug 21 07:35:57 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3486798145 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ combo_detect_with_pre_cond.3486798145 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.575421491 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4357517016 ps |
| CPU time | 4.92 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:29 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=57542 1491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 27.sysrst_ctrl_ec_pwr_on_rst.575421491 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1480163440 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2613622017 ps |
| CPU time | 8.44 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:32 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480163440 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot _out.1480163440 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2537435667 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2465649934 ps |
| CPU time | 12.38 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:36 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2537435667 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inve rted.2537435667 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.1294445996 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2095313949 ps |
| CPU time | 3.35 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:27 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1294445996 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1294445996 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1073375191 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2581023648 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:26 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073375191 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_t est.1073375191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3551615783 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2138049028 ps |
| CPU time | 3.14 seconds |
| Started | Aug 21 07:35:23 AM UTC 24 |
| Finished | Aug 21 07:35:27 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3551615783 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3551615783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.1628936014 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 15677897944 ps |
| CPU time | 14.45 seconds |
| Started | Aug 21 07:35:30 AM UTC 24 |
| Finished | Aug 21 07:35:46 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16289360 14 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sysrst_ctrl_stress_all.1628936014 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.819617191 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 5651410764 ps |
| CPU time | 15.84 seconds |
| Started | Aug 21 07:35:30 AM UTC 24 |
| Finished | Aug 21 07:35:47 AM UTC 24 |
| Peak memory | 220796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=819617191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.819617191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2122325323 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 3354246839 ps |
| CPU time | 7.01 seconds |
| Started | Aug 21 07:35:27 AM UTC 24 |
| Finished | Aug 21 07:35:35 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21223 25323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 27.sysrst_ctrl_ultra_low_pwr.2122325323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.540400045 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2015095090 ps |
| CPU time | 11.02 seconds |
| Started | Aug 21 07:35:47 AM UTC 24 |
| Finished | Aug 21 07:36:00 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=540400045 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ ctrl_alert_test.540400045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.688470623 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 3475376491 ps |
| CPU time | 2.04 seconds |
| Started | Aug 21 07:35:37 AM UTC 24 |
| Finished | Aug 21 07:35:40 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=688470623 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk _key_output.688470623 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.4012549261 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 129739854812 ps |
| CPU time | 340.32 seconds |
| Started | Aug 21 07:35:42 AM UTC 24 |
| Finished | Aug 21 07:41:26 AM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40125 49261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 28.sysrst_ctrl_combo_detect.4012549261 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2553714310 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2586577075 ps |
| CPU time | 6.58 seconds |
| Started | Aug 21 07:35:37 AM UTC 24 |
| Finished | Aug 21 07:35:44 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25537 14310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sysrst_ctrl_ec_pwr_on_rst.2553714310 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3220403041 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2925406812 ps |
| CPU time | 14.03 seconds |
| Started | Aug 21 07:35:43 AM UTC 24 |
| Finished | Aug 21 07:35:58 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32204 03041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.sysrst_ctrl_edge_detect.3220403041 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3851062461 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2634388518 ps |
| CPU time | 3.94 seconds |
| Started | Aug 21 07:35:36 AM UTC 24 |
| Finished | Aug 21 07:35:41 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3851062461 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot _out.3851062461 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.3076633642 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2471642648 ps |
| CPU time | 7.31 seconds |
| Started | Aug 21 07:35:33 AM UTC 24 |
| Finished | Aug 21 07:35:42 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076633642 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inve rted.3076633642 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.4219523898 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2218906268 ps |
| CPU time | 11.11 seconds |
| Started | Aug 21 07:35:34 AM UTC 24 |
| Finished | Aug 21 07:35:47 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219523898 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.4219523898 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3790904886 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2514155981 ps |
| CPU time | 10.28 seconds |
| Started | Aug 21 07:35:36 AM UTC 24 |
| Finished | Aug 21 07:35:47 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3790904886 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_t est.3790904886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3380439713 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2122734842 ps |
| CPU time | 3.25 seconds |
| Started | Aug 21 07:35:31 AM UTC 24 |
| Finished | Aug 21 07:35:36 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380439713 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3380439713 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.4251333715 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 10357620384 ps |
| CPU time | 13.83 seconds |
| Started | Aug 21 07:35:46 AM UTC 24 |
| Finished | Aug 21 07:36:01 AM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42513337 15 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sysrst_ctrl_stress_all.4251333715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.418152105 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 7499374577 ps |
| CPU time | 17.09 seconds |
| Started | Aug 21 07:35:46 AM UTC 24 |
| Finished | Aug 21 07:36:05 AM UTC 24 |
| Peak memory | 220708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=418152105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.418152105 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3466440039 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4763515586 ps |
| CPU time | 8.98 seconds |
| Started | Aug 21 07:35:41 AM UTC 24 |
| Finished | Aug 21 07:35:51 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34664 40039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sysrst_ctrl_ultra_low_pwr.3466440039 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3053389581 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 2023281432 ps |
| CPU time | 2.37 seconds |
| Started | Aug 21 07:36:06 AM UTC 24 |
| Finished | Aug 21 07:36:10 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3053389581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst _ctrl_alert_test.3053389581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.458155197 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 3174023678 ps |
| CPU time | 7.68 seconds |
| Started | Aug 21 07:35:54 AM UTC 24 |
| Finished | Aug 21 07:36:03 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=458155197 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk _key_output.458155197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2867173429 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 149243623117 ps |
| CPU time | 402.45 seconds |
| Started | Aug 21 07:36:06 AM UTC 24 |
| Finished | Aug 21 07:42:53 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2867173429 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ combo_detect_with_pre_cond.2867173429 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3475374447 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3494494583 ps |
| CPU time | 8.36 seconds |
| Started | Aug 21 07:35:52 AM UTC 24 |
| Finished | Aug 21 07:36:01 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34753 74447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 29.sysrst_ctrl_ec_pwr_on_rst.3475374447 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2278071563 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6409765475 ps |
| CPU time | 26.66 seconds |
| Started | Aug 21 07:36:06 AM UTC 24 |
| Finished | Aug 21 07:36:34 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22780 71563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.sysrst_ctrl_edge_detect.2278071563 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3401624224 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2610635022 ps |
| CPU time | 10.55 seconds |
| Started | Aug 21 07:35:52 AM UTC 24 |
| Finished | Aug 21 07:36:03 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401624224 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot _out.3401624224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.1225966384 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2509363509 ps |
| CPU time | 4.15 seconds |
| Started | Aug 21 07:35:49 AM UTC 24 |
| Finished | Aug 21 07:35:54 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225966384 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inve rted.1225966384 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1225801681 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2045969381 ps |
| CPU time | 3.39 seconds |
| Started | Aug 21 07:35:49 AM UTC 24 |
| Finished | Aug 21 07:35:53 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1225801681 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1225801681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3845817080 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2519658593 ps |
| CPU time | 6.53 seconds |
| Started | Aug 21 07:35:50 AM UTC 24 |
| Finished | Aug 21 07:35:57 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3845817080 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_t est.3845817080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2538584336 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2143662529 ps |
| CPU time | 2.05 seconds |
| Started | Aug 21 07:35:47 AM UTC 24 |
| Finished | Aug 21 07:35:51 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538584336 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2538584336 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1481428314 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 4707498419 ps |
| CPU time | 3.43 seconds |
| Started | Aug 21 07:36:05 AM UTC 24 |
| Finished | Aug 21 07:36:09 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14814 28314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 29.sysrst_ctrl_ultra_low_pwr.1481428314 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.4016634265 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2022533270 ps |
| CPU time | 3.61 seconds |
| Started | Aug 21 07:27:50 AM UTC 24 |
| Finished | Aug 21 07:27:55 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4016634265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ ctrl_alert_test.4016634265 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.727551901 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3313122965 ps |
| CPU time | 9.05 seconds |
| Started | Aug 21 07:27:42 AM UTC 24 |
| Finished | Aug 21 07:27:53 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=727551901 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_ key_output.727551901 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1428066658 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 41040394680 ps |
| CPU time | 34.43 seconds |
| Started | Aug 21 07:27:44 AM UTC 24 |
| Finished | Aug 21 07:28:19 AM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14280 66658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 3.sysrst_ctrl_combo_detect.1428066658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1271254168 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2255588441 ps |
| CPU time | 11.03 seconds |
| Started | Aug 21 07:27:32 AM UTC 24 |
| Finished | Aug 21 07:27:44 AM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271254168 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de tect_ec_rst.1271254168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2828174030 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2527276603 ps |
| CPU time | 6.73 seconds |
| Started | Aug 21 07:27:35 AM UTC 24 |
| Finished | Aug 21 07:27:43 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2828174030 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst _ctrl_combo_detect_ec_rst_with_pre_cond.2828174030 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2549996080 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 58908032445 ps |
| CPU time | 210.68 seconds |
| Started | Aug 21 07:27:45 AM UTC 24 |
| Finished | Aug 21 07:31:18 AM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2549996080 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_c ombo_detect_with_pre_cond.2549996080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.357738340 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3762220808 ps |
| CPU time | 7.3 seconds |
| Started | Aug 21 07:27:40 AM UTC 24 |
| Finished | Aug 21 07:27:49 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35773 8340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 3.sysrst_ctrl_ec_pwr_on_rst.357738340 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3346714585 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2925310169 ps |
| CPU time | 14.37 seconds |
| Started | Aug 21 07:27:44 AM UTC 24 |
| Finished | Aug 21 07:27:59 AM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33467 14585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.sysrst_ctrl_edge_detect.3346714585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3703348247 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2640354342 ps |
| CPU time | 3.03 seconds |
| Started | Aug 21 07:27:40 AM UTC 24 |
| Finished | Aug 21 07:27:45 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703348247 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_ out.3703348247 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1192311947 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2477944160 ps |
| CPU time | 2.14 seconds |
| Started | Aug 21 07:27:31 AM UTC 24 |
| Finished | Aug 21 07:27:34 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1192311947 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inver ted.1192311947 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2937285032 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2036412486 ps |
| CPU time | 5.47 seconds |
| Started | Aug 21 07:27:35 AM UTC 24 |
| Finished | Aug 21 07:27:42 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2937285032 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.2937285032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3093941253 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2577408464 ps |
| CPU time | 2.07 seconds |
| Started | Aug 21 07:27:36 AM UTC 24 |
| Finished | Aug 21 07:27:39 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093941253 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_te st.3093941253 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3440907037 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 42011029620 ps |
| CPU time | 115.05 seconds |
| Started | Aug 21 07:27:48 AM UTC 24 |
| Finished | Aug 21 07:29:45 AM UTC 24 |
| Peak memory | 240288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3440907037 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c trl_sec_cm.3440907037 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.1906734087 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2125825302 ps |
| CPU time | 3.52 seconds |
| Started | Aug 21 07:27:30 AM UTC 24 |
| Finished | Aug 21 07:27:34 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1906734087 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.1906734087 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.345194955 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3636553570 ps |
| CPU time | 18.41 seconds |
| Started | Aug 21 07:27:46 AM UTC 24 |
| Finished | Aug 21 07:28:05 AM UTC 24 |
| Peak memory | 220248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345194955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.345194955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.121284790 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5365015841 ps |
| CPU time | 12.43 seconds |
| Started | Aug 21 07:27:43 AM UTC 24 |
| Finished | Aug 21 07:27:57 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12128 4790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 3.sysrst_ctrl_ultra_low_pwr.121284790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3879228988 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2027916697 ps |
| CPU time | 3.06 seconds |
| Started | Aug 21 07:36:12 AM UTC 24 |
| Finished | Aug 21 07:36:16 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3879228988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst _ctrl_alert_test.3879228988 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.4143989207 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 3062270016 ps |
| CPU time | 3.03 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:11 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4143989207 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_bl k_key_output.4143989207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.3044719246 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 134144208142 ps |
| CPU time | 105.51 seconds |
| Started | Aug 21 07:36:08 AM UTC 24 |
| Finished | Aug 21 07:37:55 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30447 19246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 30.sysrst_ctrl_combo_detect.3044719246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2488109458 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 4382094135 ps |
| CPU time | 3.39 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:11 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24881 09458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sysrst_ctrl_ec_pwr_on_rst.2488109458 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2984658063 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3383241975 ps |
| CPU time | 6.28 seconds |
| Started | Aug 21 07:36:10 AM UTC 24 |
| Finished | Aug 21 07:36:17 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29846 58063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.sysrst_ctrl_edge_detect.2984658063 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.330909875 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2626067870 ps |
| CPU time | 5.2 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:13 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=330909875 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_ out.330909875 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.3748482670 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2462355002 ps |
| CPU time | 4 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:12 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748482670 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inve rted.3748482670 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.1085848511 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2208961900 ps |
| CPU time | 5.71 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:13 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1085848511 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1085848511 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.2722624774 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2512957648 ps |
| CPU time | 6.81 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:15 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2722624774 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_t est.2722624774 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.2873209365 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2108627904 ps |
| CPU time | 12.95 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:21 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2873209365 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2873209365 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2795546521 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 8166670457 ps |
| CPU time | 10.75 seconds |
| Started | Aug 21 07:36:11 AM UTC 24 |
| Finished | Aug 21 07:36:23 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2795546521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2795546521 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2787639946 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3644251837 ps |
| CPU time | 8.04 seconds |
| Started | Aug 21 07:36:07 AM UTC 24 |
| Finished | Aug 21 07:36:16 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27876 39946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 30.sysrst_ctrl_ultra_low_pwr.2787639946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3685111465 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2012849584 ps |
| CPU time | 7 seconds |
| Started | Aug 21 07:36:34 AM UTC 24 |
| Finished | Aug 21 07:36:42 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3685111465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst _ctrl_alert_test.3685111465 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.4247274474 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 323066099522 ps |
| CPU time | 235.22 seconds |
| Started | Aug 21 07:36:18 AM UTC 24 |
| Finished | Aug 21 07:40:16 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4247274474 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_bl k_key_output.4247274474 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.2904847899 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 79058495222 ps |
| CPU time | 60.71 seconds |
| Started | Aug 21 07:36:20 AM UTC 24 |
| Finished | Aug 21 07:37:22 AM UTC 24 |
| Peak memory | 210228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29048 47899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 31.sysrst_ctrl_combo_detect.2904847899 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1302249966 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3431472317 ps |
| CPU time | 16.4 seconds |
| Started | Aug 21 07:36:18 AM UTC 24 |
| Finished | Aug 21 07:36:36 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13022 49966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 31.sysrst_ctrl_ec_pwr_on_rst.1302249966 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2975695955 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4286865149 ps |
| CPU time | 3.28 seconds |
| Started | Aug 21 07:36:32 AM UTC 24 |
| Finished | Aug 21 07:36:37 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29756 95955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.sysrst_ctrl_edge_detect.2975695955 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3957111420 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2631984516 ps |
| CPU time | 3.72 seconds |
| Started | Aug 21 07:36:17 AM UTC 24 |
| Finished | Aug 21 07:36:22 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3957111420 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot _out.3957111420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1213232031 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2474388112 ps |
| CPU time | 3.95 seconds |
| Started | Aug 21 07:36:13 AM UTC 24 |
| Finished | Aug 21 07:36:19 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1213232031 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inve rted.1213232031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3804932763 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2084450778 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 07:36:14 AM UTC 24 |
| Finished | Aug 21 07:36:19 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3804932763 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3804932763 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.4222130728 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2516346570 ps |
| CPU time | 7.29 seconds |
| Started | Aug 21 07:36:16 AM UTC 24 |
| Finished | Aug 21 07:36:24 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4222130728 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_t est.4222130728 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2949681573 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2110643886 ps |
| CPU time | 9.89 seconds |
| Started | Aug 21 07:36:12 AM UTC 24 |
| Finished | Aug 21 07:36:23 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2949681573 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2949681573 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.985220654 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 6809643791 ps |
| CPU time | 17.67 seconds |
| Started | Aug 21 07:36:33 AM UTC 24 |
| Finished | Aug 21 07:36:53 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=98522065 4 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31. sysrst_ctrl_stress_all.985220654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3882353354 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 8570018564 ps |
| CPU time | 7.91 seconds |
| Started | Aug 21 07:36:20 AM UTC 24 |
| Finished | Aug 21 07:36:29 AM UTC 24 |
| Peak memory | 209692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38823 53354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 31.sysrst_ctrl_ultra_low_pwr.3882353354 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1601576294 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2008751974 ps |
| CPU time | 8.72 seconds |
| Started | Aug 21 07:36:43 AM UTC 24 |
| Finished | Aug 21 07:36:52 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1601576294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst _ctrl_alert_test.1601576294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2861660187 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 241236507074 ps |
| CPU time | 157.4 seconds |
| Started | Aug 21 07:36:36 AM UTC 24 |
| Finished | Aug 21 07:39:16 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2861660187 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_bl k_key_output.2861660187 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.3907550417 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 57566800454 ps |
| CPU time | 86.19 seconds |
| Started | Aug 21 07:36:37 AM UTC 24 |
| Finished | Aug 21 07:38:05 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39075 50417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 32.sysrst_ctrl_combo_detect.3907550417 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2447865420 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3992806686 ps |
| CPU time | 5.39 seconds |
| Started | Aug 21 07:36:36 AM UTC 24 |
| Finished | Aug 21 07:36:42 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24478 65420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sysrst_ctrl_ec_pwr_on_rst.2447865420 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.2279098700 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4453005738 ps |
| CPU time | 6.13 seconds |
| Started | Aug 21 07:36:38 AM UTC 24 |
| Finished | Aug 21 07:36:45 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22790 98700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.sysrst_ctrl_edge_detect.2279098700 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1046039873 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2611249862 ps |
| CPU time | 7.3 seconds |
| Started | Aug 21 07:36:35 AM UTC 24 |
| Finished | Aug 21 07:36:43 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1046039873 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot _out.1046039873 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.1570313177 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2464954079 ps |
| CPU time | 8.46 seconds |
| Started | Aug 21 07:36:34 AM UTC 24 |
| Finished | Aug 21 07:36:43 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1570313177 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inve rted.1570313177 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.882559417 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2054900225 ps |
| CPU time | 3.3 seconds |
| Started | Aug 21 07:36:34 AM UTC 24 |
| Finished | Aug 21 07:36:38 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=882559417 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.882559417 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.3403560343 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2541216607 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 07:36:34 AM UTC 24 |
| Finished | Aug 21 07:36:37 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403560343 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_t est.3403560343 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3255064097 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2116896674 ps |
| CPU time | 5.13 seconds |
| Started | Aug 21 07:36:34 AM UTC 24 |
| Finished | Aug 21 07:36:40 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3255064097 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3255064097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.3874403752 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 9477604736 ps |
| CPU time | 3.81 seconds |
| Started | Aug 21 07:36:40 AM UTC 24 |
| Finished | Aug 21 07:36:45 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38744037 52 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32 .sysrst_ctrl_stress_all.3874403752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2652605936 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 9413860351 ps |
| CPU time | 12.86 seconds |
| Started | Aug 21 07:36:39 AM UTC 24 |
| Finished | Aug 21 07:36:53 AM UTC 24 |
| Peak memory | 220552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2652605936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.2652605936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2814393781 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 6762401501 ps |
| CPU time | 10.58 seconds |
| Started | Aug 21 07:36:37 AM UTC 24 |
| Finished | Aug 21 07:36:49 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28143 93781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sysrst_ctrl_ultra_low_pwr.2814393781 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.200326934 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2020594899 ps |
| CPU time | 5.55 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:37:16 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=200326934 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ ctrl_alert_test.200326934 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.710945897 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 90535260941 ps |
| CPU time | 74.99 seconds |
| Started | Aug 21 07:36:53 AM UTC 24 |
| Finished | Aug 21 07:38:10 AM UTC 24 |
| Peak memory | 209908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=710945897 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk _key_output.710945897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.2183319578 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 179279805133 ps |
| CPU time | 110.62 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:39:02 AM UTC 24 |
| Peak memory | 210116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21833 19578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 33.sysrst_ctrl_combo_detect.2183319578 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.975393077 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 3874689767 ps |
| CPU time | 11.02 seconds |
| Started | Aug 21 07:36:53 AM UTC 24 |
| Finished | Aug 21 07:37:05 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97539 3077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 33.sysrst_ctrl_ec_pwr_on_rst.975393077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.96645428 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2608039217 ps |
| CPU time | 12.42 seconds |
| Started | Aug 21 07:36:53 AM UTC 24 |
| Finished | Aug 21 07:37:07 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=96645428 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.96645428 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1353980495 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2446039564 ps |
| CPU time | 7.5 seconds |
| Started | Aug 21 07:36:44 AM UTC 24 |
| Finished | Aug 21 07:36:52 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1353980495 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inve rted.1353980495 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.1445379212 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2110532320 ps |
| CPU time | 3.21 seconds |
| Started | Aug 21 07:36:45 AM UTC 24 |
| Finished | Aug 21 07:36:49 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1445379212 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.1445379212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.4258831808 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2507315681 ps |
| CPU time | 7.02 seconds |
| Started | Aug 21 07:36:53 AM UTC 24 |
| Finished | Aug 21 07:37:01 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4258831808 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_t est.4258831808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1722820038 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2112694130 ps |
| CPU time | 7.07 seconds |
| Started | Aug 21 07:36:44 AM UTC 24 |
| Finished | Aug 21 07:36:52 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1722820038 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1722820038 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3495300307 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 92136158278 ps |
| CPU time | 271.35 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:41:44 AM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34953003 07 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33 .sysrst_ctrl_stress_all.3495300307 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1026019198 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 6445099606 ps |
| CPU time | 2.36 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:37:13 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10260 19198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 33.sysrst_ctrl_ultra_low_pwr.1026019198 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.1643905914 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2015751260 ps |
| CPU time | 8.23 seconds |
| Started | Aug 21 07:37:16 AM UTC 24 |
| Finished | Aug 21 07:37:26 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1643905914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst _ctrl_alert_test.1643905914 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.179063902 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 244563114799 ps |
| CPU time | 685.41 seconds |
| Started | Aug 21 07:37:11 AM UTC 24 |
| Finished | Aug 21 07:48:44 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=179063902 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk _key_output.179063902 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.153947882 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 110781638319 ps |
| CPU time | 208.69 seconds |
| Started | Aug 21 07:37:13 AM UTC 24 |
| Finished | Aug 21 07:40:45 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=15394 7882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.sysrst_ctrl_combo_detect.153947882 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2623186464 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 27599228868 ps |
| CPU time | 33.2 seconds |
| Started | Aug 21 07:37:13 AM UTC 24 |
| Finished | Aug 21 07:37:48 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2623186464 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ combo_detect_with_pre_cond.2623186464 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2529581207 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 4994035504 ps |
| CPU time | 24.76 seconds |
| Started | Aug 21 07:37:11 AM UTC 24 |
| Finished | Aug 21 07:37:37 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25295 81207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.sysrst_ctrl_ec_pwr_on_rst.2529581207 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.1915485527 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 556973177236 ps |
| CPU time | 1161.05 seconds |
| Started | Aug 21 07:37:13 AM UTC 24 |
| Finished | Aug 21 07:56:46 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19154 85527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.sysrst_ctrl_edge_detect.1915485527 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1819676079 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2623163343 ps |
| CPU time | 4.24 seconds |
| Started | Aug 21 07:37:11 AM UTC 24 |
| Finished | Aug 21 07:37:16 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1819676079 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot _out.1819676079 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.553015033 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2509140904 ps |
| CPU time | 1.29 seconds |
| Started | Aug 21 07:37:10 AM UTC 24 |
| Finished | Aug 21 07:37:12 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=553015033 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inver ted.553015033 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2890357946 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2259853063 ps |
| CPU time | 3.9 seconds |
| Started | Aug 21 07:37:10 AM UTC 24 |
| Finished | Aug 21 07:37:15 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2890357946 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2890357946 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.1369384406 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2531092726 ps |
| CPU time | 3.61 seconds |
| Started | Aug 21 07:37:11 AM UTC 24 |
| Finished | Aug 21 07:37:15 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1369384406 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_t est.1369384406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.323236331 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2225725338 ps |
| CPU time | 1.38 seconds |
| Started | Aug 21 07:37:09 AM UTC 24 |
| Finished | Aug 21 07:37:12 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=323236331 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.323236331 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.964011616 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 7103656090 ps |
| CPU time | 22.39 seconds |
| Started | Aug 21 07:37:13 AM UTC 24 |
| Finished | Aug 21 07:37:37 AM UTC 24 |
| Peak memory | 220536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=964011616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.964011616 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2710354785 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 360135360536 ps |
| CPU time | 146.44 seconds |
| Started | Aug 21 07:37:13 AM UTC 24 |
| Finished | Aug 21 07:39:42 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27103 54785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 34.sysrst_ctrl_ultra_low_pwr.2710354785 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.1976051208 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2027629247 ps |
| CPU time | 4.01 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:37:41 AM UTC 24 |
| Peak memory | 209844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1976051208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst _ctrl_alert_test.1976051208 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.189556267 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3617049509 ps |
| CPU time | 11.89 seconds |
| Started | Aug 21 07:37:25 AM UTC 24 |
| Finished | Aug 21 07:37:38 AM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=189556267 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk _key_output.189556267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2408751106 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 42561056581 ps |
| CPU time | 95.19 seconds |
| Started | Aug 21 07:37:28 AM UTC 24 |
| Finished | Aug 21 07:39:05 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24087 51106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 35.sysrst_ctrl_combo_detect.2408751106 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1808525639 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 32337540190 ps |
| CPU time | 50.37 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:38:28 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1808525639 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ combo_detect_with_pre_cond.1808525639 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4067184836 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 3195497927 ps |
| CPU time | 4.59 seconds |
| Started | Aug 21 07:37:24 AM UTC 24 |
| Finished | Aug 21 07:37:30 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40671 84836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sysrst_ctrl_ec_pwr_on_rst.4067184836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.801730537 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2767908962 ps |
| CPU time | 1.92 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:37:39 AM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=80173 0537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.801730537 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2047307823 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2611265795 ps |
| CPU time | 8.64 seconds |
| Started | Aug 21 07:37:23 AM UTC 24 |
| Finished | Aug 21 07:37:33 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2047307823 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot _out.2047307823 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.971809844 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2463086320 ps |
| CPU time | 5.93 seconds |
| Started | Aug 21 07:37:18 AM UTC 24 |
| Finished | Aug 21 07:37:25 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971809844 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inver ted.971809844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1655553949 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2240587848 ps |
| CPU time | 11.03 seconds |
| Started | Aug 21 07:37:21 AM UTC 24 |
| Finished | Aug 21 07:37:33 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1655553949 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1655553949 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.3496065034 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2534233315 ps |
| CPU time | 4.12 seconds |
| Started | Aug 21 07:37:22 AM UTC 24 |
| Finished | Aug 21 07:37:27 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496065034 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_t est.3496065034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.867267783 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2128792208 ps |
| CPU time | 3.19 seconds |
| Started | Aug 21 07:37:16 AM UTC 24 |
| Finished | Aug 21 07:37:21 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867267783 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.867267783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.1057102159 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 14545825728 ps |
| CPU time | 44.83 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:38:23 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10571021 59 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sysrst_ctrl_stress_all.1057102159 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1347713133 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 5124966213 ps |
| CPU time | 9.1 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:37:47 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1347713133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1347713133 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1203578160 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2897020604766 ps |
| CPU time | 79.36 seconds |
| Started | Aug 21 07:37:27 AM UTC 24 |
| Finished | Aug 21 07:38:48 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12035 78160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 35.sysrst_ctrl_ultra_low_pwr.1203578160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3513856036 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2025949921 ps |
| CPU time | 5.1 seconds |
| Started | Aug 21 07:37:47 AM UTC 24 |
| Finished | Aug 21 07:37:53 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3513856036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst _ctrl_alert_test.3513856036 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.492106769 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 3468317301 ps |
| CPU time | 4.56 seconds |
| Started | Aug 21 07:37:40 AM UTC 24 |
| Finished | Aug 21 07:37:46 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=492106769 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk _key_output.492106769 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.363858051 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 130978086551 ps |
| CPU time | 28.07 seconds |
| Started | Aug 21 07:37:43 AM UTC 24 |
| Finished | Aug 21 07:38:12 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36385 8051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.sysrst_ctrl_combo_detect.363858051 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2526346344 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 52318062793 ps |
| CPU time | 121.09 seconds |
| Started | Aug 21 07:37:44 AM UTC 24 |
| Finished | Aug 21 07:39:47 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526346344 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ combo_detect_with_pre_cond.2526346344 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2338614049 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2878119783 ps |
| CPU time | 3.5 seconds |
| Started | Aug 21 07:37:39 AM UTC 24 |
| Finished | Aug 21 07:37:44 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23386 14049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 36.sysrst_ctrl_ec_pwr_on_rst.2338614049 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.2245019805 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3814093721 ps |
| CPU time | 4.53 seconds |
| Started | Aug 21 07:37:43 AM UTC 24 |
| Finished | Aug 21 07:37:48 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22450 19805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.sysrst_ctrl_edge_detect.2245019805 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2553603777 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2672431890 ps |
| CPU time | 1.86 seconds |
| Started | Aug 21 07:37:38 AM UTC 24 |
| Finished | Aug 21 07:37:42 AM UTC 24 |
| Peak memory | 208116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2553603777 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot _out.2553603777 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1363523924 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2457638741 ps |
| CPU time | 12.17 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:37:50 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1363523924 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inve rted.1363523924 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2408622011 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2068740433 ps |
| CPU time | 2.77 seconds |
| Started | Aug 21 07:37:38 AM UTC 24 |
| Finished | Aug 21 07:37:43 AM UTC 24 |
| Peak memory | 209732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2408622011 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2408622011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2267624661 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2514085177 ps |
| CPU time | 9.26 seconds |
| Started | Aug 21 07:37:38 AM UTC 24 |
| Finished | Aug 21 07:37:49 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2267624661 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_t est.2267624661 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.3161249676 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2114016189 ps |
| CPU time | 8.9 seconds |
| Started | Aug 21 07:37:36 AM UTC 24 |
| Finished | Aug 21 07:37:46 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3161249676 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.3161249676 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.1818556675 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 13711350054 ps |
| CPU time | 36.56 seconds |
| Started | Aug 21 07:37:45 AM UTC 24 |
| Finished | Aug 21 07:38:23 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18185566 75 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36 .sysrst_ctrl_stress_all.1818556675 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2856191011 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 6473443198 ps |
| CPU time | 11.16 seconds |
| Started | Aug 21 07:37:44 AM UTC 24 |
| Finished | Aug 21 07:37:56 AM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2856191011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2856191011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.1059958118 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2012890463 ps |
| CPU time | 6.5 seconds |
| Started | Aug 21 07:38:00 AM UTC 24 |
| Finished | Aug 21 07:38:08 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1059958118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst _ctrl_alert_test.1059958118 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2587932172 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 3023275836 ps |
| CPU time | 9.18 seconds |
| Started | Aug 21 07:37:52 AM UTC 24 |
| Finished | Aug 21 07:38:02 AM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2587932172 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_bl k_key_output.2587932172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.2076907005 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 76705978693 ps |
| CPU time | 29.53 seconds |
| Started | Aug 21 07:37:56 AM UTC 24 |
| Finished | Aug 21 07:38:27 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20769 07005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 37.sysrst_ctrl_combo_detect.2076907005 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.436588600 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 77739900939 ps |
| CPU time | 218.7 seconds |
| Started | Aug 21 07:37:57 AM UTC 24 |
| Finished | Aug 21 07:41:39 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=436588600 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_c ombo_detect_with_pre_cond.436588600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.368445124 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3292695871 ps |
| CPU time | 4.48 seconds |
| Started | Aug 21 07:37:51 AM UTC 24 |
| Finished | Aug 21 07:37:56 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36844 5124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 37.sysrst_ctrl_ec_pwr_on_rst.368445124 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.3004091404 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2556625517 ps |
| CPU time | 12.61 seconds |
| Started | Aug 21 07:37:57 AM UTC 24 |
| Finished | Aug 21 07:38:11 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30040 91404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.sysrst_ctrl_edge_detect.3004091404 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2462774376 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2615138102 ps |
| CPU time | 9.91 seconds |
| Started | Aug 21 07:37:49 AM UTC 24 |
| Finished | Aug 21 07:38:01 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2462774376 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot _out.2462774376 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2977520638 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2480509829 ps |
| CPU time | 11.54 seconds |
| Started | Aug 21 07:37:47 AM UTC 24 |
| Finished | Aug 21 07:38:00 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2977520638 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inve rted.2977520638 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.382747787 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2191408856 ps |
| CPU time | 10.39 seconds |
| Started | Aug 21 07:37:48 AM UTC 24 |
| Finished | Aug 21 07:38:00 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=382747787 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.382747787 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2776513031 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2510673951 ps |
| CPU time | 10.29 seconds |
| Started | Aug 21 07:37:48 AM UTC 24 |
| Finished | Aug 21 07:38:00 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2776513031 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_t est.2776513031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.3821458035 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2110875564 ps |
| CPU time | 9.78 seconds |
| Started | Aug 21 07:37:47 AM UTC 24 |
| Finished | Aug 21 07:37:58 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3821458035 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.3821458035 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.3131756011 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 12329811613 ps |
| CPU time | 3.8 seconds |
| Started | Aug 21 07:37:59 AM UTC 24 |
| Finished | Aug 21 07:38:04 AM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31317560 11 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sysrst_ctrl_stress_all.3131756011 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2576602868 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4888871617 ps |
| CPU time | 22.69 seconds |
| Started | Aug 21 07:37:58 AM UTC 24 |
| Finished | Aug 21 07:38:22 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2576602868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2576602868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3655544191 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 5469918596 ps |
| CPU time | 8.36 seconds |
| Started | Aug 21 07:37:54 AM UTC 24 |
| Finished | Aug 21 07:38:03 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36555 44191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 37.sysrst_ctrl_ultra_low_pwr.3655544191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3270219246 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2083578605 ps |
| CPU time | 1.71 seconds |
| Started | Aug 21 07:38:13 AM UTC 24 |
| Finished | Aug 21 07:38:16 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3270219246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst _ctrl_alert_test.3270219246 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.4188850654 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3235126250 ps |
| CPU time | 7.93 seconds |
| Started | Aug 21 07:38:11 AM UTC 24 |
| Finished | Aug 21 07:38:20 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4188850654 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_bl k_key_output.4188850654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3087773317 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 157384506639 ps |
| CPU time | 356.23 seconds |
| Started | Aug 21 07:38:11 AM UTC 24 |
| Finished | Aug 21 07:44:11 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30877 73317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 38.sysrst_ctrl_combo_detect.3087773317 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1030704121 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 137219137905 ps |
| CPU time | 125.58 seconds |
| Started | Aug 21 07:38:11 AM UTC 24 |
| Finished | Aug 21 07:40:19 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1030704121 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ combo_detect_with_pre_cond.1030704121 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.383452199 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 3843216692 ps |
| CPU time | 2.06 seconds |
| Started | Aug 21 07:38:11 AM UTC 24 |
| Finished | Aug 21 07:38:14 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38345 2199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 38.sysrst_ctrl_ec_pwr_on_rst.383452199 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.677082528 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4939919001 ps |
| CPU time | 7.49 seconds |
| Started | Aug 21 07:38:11 AM UTC 24 |
| Finished | Aug 21 07:38:19 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=67708 2528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.677082528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1536794953 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2631121408 ps |
| CPU time | 3.9 seconds |
| Started | Aug 21 07:38:09 AM UTC 24 |
| Finished | Aug 21 07:38:14 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1536794953 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot _out.1536794953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.615565203 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2468384528 ps |
| CPU time | 10.6 seconds |
| Started | Aug 21 07:38:00 AM UTC 24 |
| Finished | Aug 21 07:38:12 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=615565203 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inver ted.615565203 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3431885687 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2013098465 ps |
| CPU time | 9.85 seconds |
| Started | Aug 21 07:38:01 AM UTC 24 |
| Finished | Aug 21 07:38:12 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3431885687 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3431885687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1157150705 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2508423396 ps |
| CPU time | 8.02 seconds |
| Started | Aug 21 07:38:09 AM UTC 24 |
| Finished | Aug 21 07:38:18 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1157150705 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_t est.1157150705 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2265573350 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2137148836 ps |
| CPU time | 3.42 seconds |
| Started | Aug 21 07:38:00 AM UTC 24 |
| Finished | Aug 21 07:38:05 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2265573350 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2265573350 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.73298406 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 13197731006 ps |
| CPU time | 32.94 seconds |
| Started | Aug 21 07:38:13 AM UTC 24 |
| Finished | Aug 21 07:38:47 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=73298406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.s ysrst_ctrl_stress_all.73298406 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4154560868 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 5605972585 ps |
| CPU time | 6.89 seconds |
| Started | Aug 21 07:38:11 AM UTC 24 |
| Finished | Aug 21 07:38:19 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=41545 60868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 38.sysrst_ctrl_ultra_low_pwr.4154560868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2321866581 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2045759181 ps |
| CPU time | 2.31 seconds |
| Started | Aug 21 07:38:24 AM UTC 24 |
| Finished | Aug 21 07:38:27 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2321866581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst _ctrl_alert_test.2321866581 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1086741864 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3088831310 ps |
| CPU time | 3.24 seconds |
| Started | Aug 21 07:38:20 AM UTC 24 |
| Finished | Aug 21 07:38:24 AM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1086741864 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_bl k_key_output.1086741864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.897243472 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 101417278124 ps |
| CPU time | 313.91 seconds |
| Started | Aug 21 07:38:21 AM UTC 24 |
| Finished | Aug 21 07:43:39 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89724 3472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.sysrst_ctrl_combo_detect.897243472 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1329348489 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 53216248861 ps |
| CPU time | 175.6 seconds |
| Started | Aug 21 07:38:23 AM UTC 24 |
| Finished | Aug 21 07:41:21 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1329348489 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ combo_detect_with_pre_cond.1329348489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2617910441 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3951787681 ps |
| CPU time | 6.89 seconds |
| Started | Aug 21 07:38:20 AM UTC 24 |
| Finished | Aug 21 07:38:28 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=26179 10441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sysrst_ctrl_ec_pwr_on_rst.2617910441 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.3336687658 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3167979001 ps |
| CPU time | 11.48 seconds |
| Started | Aug 21 07:38:21 AM UTC 24 |
| Finished | Aug 21 07:38:33 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33366 87658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.sysrst_ctrl_edge_detect.3336687658 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2661668493 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2630874979 ps |
| CPU time | 3.89 seconds |
| Started | Aug 21 07:38:17 AM UTC 24 |
| Finished | Aug 21 07:38:22 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2661668493 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot _out.2661668493 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.4266516869 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2470332606 ps |
| CPU time | 11.1 seconds |
| Started | Aug 21 07:38:14 AM UTC 24 |
| Finished | Aug 21 07:38:26 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4266516869 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inve rted.4266516869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2267199400 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2037179539 ps |
| CPU time | 3.22 seconds |
| Started | Aug 21 07:38:15 AM UTC 24 |
| Finished | Aug 21 07:38:20 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2267199400 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2267199400 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1999429636 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2511592820 ps |
| CPU time | 9.83 seconds |
| Started | Aug 21 07:38:16 AM UTC 24 |
| Finished | Aug 21 07:38:27 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1999429636 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_t est.1999429636 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.623150501 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2144150351 ps |
| CPU time | 2.28 seconds |
| Started | Aug 21 07:38:13 AM UTC 24 |
| Finished | Aug 21 07:38:16 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=623150501 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.623150501 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3074615754 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1027888914714 ps |
| CPU time | 39.47 seconds |
| Started | Aug 21 07:38:23 AM UTC 24 |
| Finished | Aug 21 07:39:04 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074615754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3074615754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2505907294 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4949608035 ps |
| CPU time | 10.82 seconds |
| Started | Aug 21 07:38:20 AM UTC 24 |
| Finished | Aug 21 07:38:32 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25059 07294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 39.sysrst_ctrl_ultra_low_pwr.2505907294 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.4068444771 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2014777540 ps |
| CPU time | 10.81 seconds |
| Started | Aug 21 07:28:24 AM UTC 24 |
| Finished | Aug 21 07:28:36 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4068444771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ ctrl_alert_test.4068444771 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4088516834 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3184178893 ps |
| CPU time | 2.34 seconds |
| Started | Aug 21 07:28:09 AM UTC 24 |
| Finished | Aug 21 07:28:13 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4088516834 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk _key_output.4088516834 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.764877793 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 148883651247 ps |
| CPU time | 171.12 seconds |
| Started | Aug 21 07:28:10 AM UTC 24 |
| Finished | Aug 21 07:31:04 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=76487 7793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.sysrst_ctrl_combo_detect.764877793 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2536706451 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2392376317 ps |
| CPU time | 10.48 seconds |
| Started | Aug 21 07:27:57 AM UTC 24 |
| Finished | Aug 21 07:28:09 AM UTC 24 |
| Peak memory | 209956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2536706451 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de tect_ec_rst.2536706451 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3000921869 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2517661882 ps |
| CPU time | 9.61 seconds |
| Started | Aug 21 07:27:58 AM UTC 24 |
| Finished | Aug 21 07:28:09 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3000921869 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst _ctrl_combo_detect_ec_rst_with_pre_cond.3000921869 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1040364221 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1284481142659 ps |
| CPU time | 3365.86 seconds |
| Started | Aug 21 07:28:09 AM UTC 24 |
| Finished | Aug 21 08:24:48 AM UTC 24 |
| Peak memory | 212528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10403 64221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sysrst_ctrl_ec_pwr_on_rst.1040364221 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1406453126 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2618017693 ps |
| CPU time | 7.86 seconds |
| Started | Aug 21 07:28:09 AM UTC 24 |
| Finished | Aug 21 07:28:18 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1406453126 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_ out.1406453126 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.244722896 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2459583513 ps |
| CPU time | 12.31 seconds |
| Started | Aug 21 07:27:55 AM UTC 24 |
| Finished | Aug 21 07:28:09 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244722896 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.244722896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3871834868 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2174779914 ps |
| CPU time | 9.5 seconds |
| Started | Aug 21 07:27:59 AM UTC 24 |
| Finished | Aug 21 07:28:10 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3871834868 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3871834868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2279801989 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2509862739 ps |
| CPU time | 12.17 seconds |
| Started | Aug 21 07:28:09 AM UTC 24 |
| Finished | Aug 21 07:28:22 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2279801989 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_te st.2279801989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.2830110528 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 22011479924 ps |
| CPU time | 91.44 seconds |
| Started | Aug 21 07:28:23 AM UTC 24 |
| Finished | Aug 21 07:29:56 AM UTC 24 |
| Peak memory | 240216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2830110528 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c trl_sec_cm.2830110528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.4235205753 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2112374982 ps |
| CPU time | 12.1 seconds |
| Started | Aug 21 07:27:53 AM UTC 24 |
| Finished | Aug 21 07:28:06 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4235205753 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.4235205753 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3877482738 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 13567696176 ps |
| CPU time | 13.47 seconds |
| Started | Aug 21 07:28:19 AM UTC 24 |
| Finished | Aug 21 07:28:33 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3877482738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.3877482738 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3521293053 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 5422931280 ps |
| CPU time | 13.85 seconds |
| Started | Aug 21 07:28:10 AM UTC 24 |
| Finished | Aug 21 07:28:25 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35212 93053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.sysrst_ctrl_ultra_low_pwr.3521293053 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.550875857 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2022202336 ps |
| CPU time | 4.82 seconds |
| Started | Aug 21 07:38:34 AM UTC 24 |
| Finished | Aug 21 07:38:40 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=550875857 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ ctrl_alert_test.550875857 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1569492056 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3463951425 ps |
| CPU time | 2.94 seconds |
| Started | Aug 21 07:38:29 AM UTC 24 |
| Finished | Aug 21 07:38:33 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1569492056 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_bl k_key_output.1569492056 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.1680478847 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 100589180322 ps |
| CPU time | 129.9 seconds |
| Started | Aug 21 07:38:33 AM UTC 24 |
| Finished | Aug 21 07:40:45 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16804 78847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 40.sysrst_ctrl_combo_detect.1680478847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3008976130 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4608700625 ps |
| CPU time | 5.7 seconds |
| Started | Aug 21 07:38:29 AM UTC 24 |
| Finished | Aug 21 07:38:35 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30089 76130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.sysrst_ctrl_ec_pwr_on_rst.3008976130 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.3186933609 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2916861971 ps |
| CPU time | 4.48 seconds |
| Started | Aug 21 07:38:33 AM UTC 24 |
| Finished | Aug 21 07:38:38 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31869 33609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.sysrst_ctrl_edge_detect.3186933609 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.744682687 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 2636981749 ps |
| CPU time | 4.27 seconds |
| Started | Aug 21 07:38:29 AM UTC 24 |
| Finished | Aug 21 07:38:34 AM UTC 24 |
| Peak memory | 209612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=744682687 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_ out.744682687 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.2334052804 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2444273593 ps |
| CPU time | 11.98 seconds |
| Started | Aug 21 07:38:27 AM UTC 24 |
| Finished | Aug 21 07:38:40 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2334052804 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inve rted.2334052804 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2531681879 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2228982392 ps |
| CPU time | 3.53 seconds |
| Started | Aug 21 07:38:27 AM UTC 24 |
| Finished | Aug 21 07:38:32 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2531681879 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.2531681879 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.1166304851 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2542398036 ps |
| CPU time | 2.51 seconds |
| Started | Aug 21 07:38:29 AM UTC 24 |
| Finished | Aug 21 07:38:32 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1166304851 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_t est.1166304851 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.3957224790 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2129891615 ps |
| CPU time | 3.61 seconds |
| Started | Aug 21 07:38:25 AM UTC 24 |
| Finished | Aug 21 07:38:30 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3957224790 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3957224790 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2241177263 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 18355052375 ps |
| CPU time | 3.16 seconds |
| Started | Aug 21 07:38:34 AM UTC 24 |
| Finished | Aug 21 07:38:38 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22411772 63 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sysrst_ctrl_stress_all.2241177263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2940752140 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 10380627747 ps |
| CPU time | 8.78 seconds |
| Started | Aug 21 07:38:33 AM UTC 24 |
| Finished | Aug 21 07:38:43 AM UTC 24 |
| Peak memory | 220784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2940752140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2940752140 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2208714123 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2029797268 ps |
| CPU time | 3.33 seconds |
| Started | Aug 21 07:38:48 AM UTC 24 |
| Finished | Aug 21 07:38:53 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2208714123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst _ctrl_alert_test.2208714123 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.421458897 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3627505464 ps |
| CPU time | 8.21 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:38:55 AM UTC 24 |
| Peak memory | 209744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=421458897 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk _key_output.421458897 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.2861873622 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 113349975709 ps |
| CPU time | 37.31 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:39:25 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=28618 73622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 41.sysrst_ctrl_combo_detect.2861873622 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1705852111 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2797347794 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:38:49 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17058 52111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.sysrst_ctrl_ec_pwr_on_rst.1705852111 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2091469408 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3401209344 ps |
| CPU time | 9.01 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:38:56 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20914 69408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.sysrst_ctrl_edge_detect.2091469408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1234599197 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2633271174 ps |
| CPU time | 4.87 seconds |
| Started | Aug 21 07:38:40 AM UTC 24 |
| Finished | Aug 21 07:38:46 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1234599197 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot _out.1234599197 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2608757894 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2468865316 ps |
| CPU time | 4.19 seconds |
| Started | Aug 21 07:38:36 AM UTC 24 |
| Finished | Aug 21 07:38:42 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608757894 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inve rted.2608757894 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1964971172 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2162654951 ps |
| CPU time | 9.55 seconds |
| Started | Aug 21 07:38:36 AM UTC 24 |
| Finished | Aug 21 07:38:47 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1964971172 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1964971172 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.4019554034 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2517846393 ps |
| CPU time | 5.65 seconds |
| Started | Aug 21 07:38:40 AM UTC 24 |
| Finished | Aug 21 07:38:46 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4019554034 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_t est.4019554034 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.1436595736 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2111458021 ps |
| CPU time | 9.79 seconds |
| Started | Aug 21 07:38:34 AM UTC 24 |
| Finished | Aug 21 07:38:45 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1436595736 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1436595736 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.1140623963 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 13664900855 ps |
| CPU time | 30.29 seconds |
| Started | Aug 21 07:38:47 AM UTC 24 |
| Finished | Aug 21 07:39:19 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=11406239 63 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sysrst_ctrl_stress_all.1140623963 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.556843122 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 8273261707 ps |
| CPU time | 10.99 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:38:58 AM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556843122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.556843122 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3038989714 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1915598404176 ps |
| CPU time | 51.6 seconds |
| Started | Aug 21 07:38:46 AM UTC 24 |
| Finished | Aug 21 07:39:39 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30389 89714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 41.sysrst_ctrl_ultra_low_pwr.3038989714 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2809888953 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2022002692 ps |
| CPU time | 5.08 seconds |
| Started | Aug 21 07:38:59 AM UTC 24 |
| Finished | Aug 21 07:39:06 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809888953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst _ctrl_alert_test.2809888953 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1500699492 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3638237143 ps |
| CPU time | 4.52 seconds |
| Started | Aug 21 07:38:54 AM UTC 24 |
| Finished | Aug 21 07:38:59 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1500699492 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_bl k_key_output.1500699492 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3887050031 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 81342759790 ps |
| CPU time | 30.37 seconds |
| Started | Aug 21 07:38:57 AM UTC 24 |
| Finished | Aug 21 07:39:29 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3887050031 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ combo_detect_with_pre_cond.3887050031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2910256674 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2681591332 ps |
| CPU time | 4.15 seconds |
| Started | Aug 21 07:38:53 AM UTC 24 |
| Finished | Aug 21 07:38:58 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29102 56674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sysrst_ctrl_ec_pwr_on_rst.2910256674 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.2596846074 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2425133641 ps |
| CPU time | 10.95 seconds |
| Started | Aug 21 07:38:56 AM UTC 24 |
| Finished | Aug 21 07:39:08 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25968 46074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.sysrst_ctrl_edge_detect.2596846074 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3420543740 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 2689121848 ps |
| CPU time | 1.9 seconds |
| Started | Aug 21 07:38:53 AM UTC 24 |
| Finished | Aug 21 07:38:56 AM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3420543740 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot _out.3420543740 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1468038372 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2458257378 ps |
| CPU time | 2.96 seconds |
| Started | Aug 21 07:38:49 AM UTC 24 |
| Finished | Aug 21 07:38:52 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1468038372 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inve rted.1468038372 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.3962681360 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2134598669 ps |
| CPU time | 6.41 seconds |
| Started | Aug 21 07:38:50 AM UTC 24 |
| Finished | Aug 21 07:38:57 AM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962681360 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3962681360 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.1523693114 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2524980677 ps |
| CPU time | 4.67 seconds |
| Started | Aug 21 07:38:50 AM UTC 24 |
| Finished | Aug 21 07:38:55 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1523693114 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_t est.1523693114 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.713360665 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2154998452 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 07:38:48 AM UTC 24 |
| Finished | Aug 21 07:38:52 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=713360665 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.713360665 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3391179957 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 8169038250 ps |
| CPU time | 9.05 seconds |
| Started | Aug 21 07:38:58 AM UTC 24 |
| Finished | Aug 21 07:39:09 AM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=33911799 57 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42 .sysrst_ctrl_stress_all.3391179957 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2481851633 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4257342735 ps |
| CPU time | 18.47 seconds |
| Started | Aug 21 07:38:58 AM UTC 24 |
| Finished | Aug 21 07:39:18 AM UTC 24 |
| Peak memory | 220252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2481851633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2481851633 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2439061550 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2729204012 ps |
| CPU time | 10.6 seconds |
| Started | Aug 21 07:38:56 AM UTC 24 |
| Finished | Aug 21 07:39:08 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24390 61550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sysrst_ctrl_ultra_low_pwr.2439061550 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.1140321341 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 2042116104 ps |
| CPU time | 3.16 seconds |
| Started | Aug 21 07:39:18 AM UTC 24 |
| Finished | Aug 21 07:39:22 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1140321341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst _ctrl_alert_test.1140321341 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.716837462 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3128730123 ps |
| CPU time | 15.57 seconds |
| Started | Aug 21 07:39:09 AM UTC 24 |
| Finished | Aug 21 07:39:26 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=716837462 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk _key_output.716837462 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.3140517808 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 139413221168 ps |
| CPU time | 151.36 seconds |
| Started | Aug 21 07:39:11 AM UTC 24 |
| Finished | Aug 21 07:41:45 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31405 17808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 43.sysrst_ctrl_combo_detect.3140517808 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3240033516 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 100746980053 ps |
| CPU time | 71.13 seconds |
| Started | Aug 21 07:39:14 AM UTC 24 |
| Finished | Aug 21 07:40:27 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3240033516 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ combo_detect_with_pre_cond.3240033516 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.452610045 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4553764856 ps |
| CPU time | 25.29 seconds |
| Started | Aug 21 07:39:09 AM UTC 24 |
| Finished | Aug 21 07:39:36 AM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45261 0045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 43.sysrst_ctrl_ec_pwr_on_rst.452610045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.889029407 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2610263824 ps |
| CPU time | 7.11 seconds |
| Started | Aug 21 07:39:07 AM UTC 24 |
| Finished | Aug 21 07:39:15 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=889029407 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_ out.889029407 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1947389810 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2435389893 ps |
| CPU time | 6.27 seconds |
| Started | Aug 21 07:39:03 AM UTC 24 |
| Finished | Aug 21 07:39:10 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1947389810 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inve rted.1947389810 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.1115538478 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2123643606 ps |
| CPU time | 10.87 seconds |
| Started | Aug 21 07:39:05 AM UTC 24 |
| Finished | Aug 21 07:39:17 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1115538478 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1115538478 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3023457926 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2521283556 ps |
| CPU time | 6.89 seconds |
| Started | Aug 21 07:39:06 AM UTC 24 |
| Finished | Aug 21 07:39:14 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3023457926 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_t est.3023457926 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.3088321351 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 2112859134 ps |
| CPU time | 11.46 seconds |
| Started | Aug 21 07:39:01 AM UTC 24 |
| Finished | Aug 21 07:39:13 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088321351 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.3088321351 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2503724800 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 8822507405 ps |
| CPU time | 16.22 seconds |
| Started | Aug 21 07:39:17 AM UTC 24 |
| Finished | Aug 21 07:39:34 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25037248 00 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43 .sysrst_ctrl_stress_all.2503724800 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3792530457 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 6117443087 ps |
| CPU time | 8.83 seconds |
| Started | Aug 21 07:39:15 AM UTC 24 |
| Finished | Aug 21 07:39:26 AM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3792530457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3792530457 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2297396375 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 7402315104 ps |
| CPU time | 9.38 seconds |
| Started | Aug 21 07:39:09 AM UTC 24 |
| Finished | Aug 21 07:39:20 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22973 96375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 43.sysrst_ctrl_ultra_low_pwr.2297396375 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.841749408 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2044184272 ps |
| CPU time | 3.24 seconds |
| Started | Aug 21 07:39:30 AM UTC 24 |
| Finished | Aug 21 07:39:34 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=841749408 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ ctrl_alert_test.841749408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1515204077 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 3571940482 ps |
| CPU time | 5.39 seconds |
| Started | Aug 21 07:39:23 AM UTC 24 |
| Finished | Aug 21 07:39:30 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1515204077 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_bl k_key_output.1515204077 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1396231525 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 150384146687 ps |
| CPU time | 225.6 seconds |
| Started | Aug 21 07:39:25 AM UTC 24 |
| Finished | Aug 21 07:43:14 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13962 31525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 44.sysrst_ctrl_combo_detect.1396231525 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2196491860 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 76227578505 ps |
| CPU time | 293.19 seconds |
| Started | Aug 21 07:39:26 AM UTC 24 |
| Finished | Aug 21 07:44:24 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2196491860 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ combo_detect_with_pre_cond.2196491860 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.3569652896 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3087616382 ps |
| CPU time | 13.03 seconds |
| Started | Aug 21 07:39:25 AM UTC 24 |
| Finished | Aug 21 07:39:40 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35696 52896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.sysrst_ctrl_edge_detect.3569652896 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3996313643 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2616983939 ps |
| CPU time | 4.26 seconds |
| Started | Aug 21 07:39:20 AM UTC 24 |
| Finished | Aug 21 07:39:26 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3996313643 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot _out.3996313643 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.3395001679 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2467874435 ps |
| CPU time | 4.11 seconds |
| Started | Aug 21 07:39:18 AM UTC 24 |
| Finished | Aug 21 07:39:23 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3395001679 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inve rted.3395001679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.113645969 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2263338602 ps |
| CPU time | 2.05 seconds |
| Started | Aug 21 07:39:19 AM UTC 24 |
| Finished | Aug 21 07:39:22 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=113645969 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.113645969 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3037909893 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2510956349 ps |
| CPU time | 9.77 seconds |
| Started | Aug 21 07:39:20 AM UTC 24 |
| Finished | Aug 21 07:39:31 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037909893 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_t est.3037909893 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.2526485191 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2116778142 ps |
| CPU time | 5.6 seconds |
| Started | Aug 21 07:39:18 AM UTC 24 |
| Finished | Aug 21 07:39:24 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526485191 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.2526485191 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.62970313 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 120732928898 ps |
| CPU time | 381.94 seconds |
| Started | Aug 21 07:39:27 AM UTC 24 |
| Finished | Aug 21 07:45:53 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=62970313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.s ysrst_ctrl_stress_all.62970313 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3521385754 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 10188321904 ps |
| CPU time | 12.58 seconds |
| Started | Aug 21 07:39:27 AM UTC 24 |
| Finished | Aug 21 07:39:40 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3521385754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.3521385754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.39157868 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2843334284 ps |
| CPU time | 6.21 seconds |
| Started | Aug 21 07:39:24 AM UTC 24 |
| Finished | Aug 21 07:39:32 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39157 868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.sysrst_ctrl_ultra_low_pwr.39157868 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2317694303 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2014416246 ps |
| CPU time | 9.98 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:39:56 AM UTC 24 |
| Peak memory | 209660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2317694303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst _ctrl_alert_test.2317694303 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2768260879 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3653430811 ps |
| CPU time | 3.56 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:39:49 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2768260879 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_bl k_key_output.2768260879 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3702025528 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 46073508246 ps |
| CPU time | 135.3 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:42:02 AM UTC 24 |
| Peak memory | 210424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37020 25528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 45.sysrst_ctrl_combo_detect.3702025528 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1018661374 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 69936302567 ps |
| CPU time | 217.14 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:43:25 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018661374 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ combo_detect_with_pre_cond.1018661374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2950045212 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2725602898 ps |
| CPU time | 13.45 seconds |
| Started | Aug 21 07:39:44 AM UTC 24 |
| Finished | Aug 21 07:39:59 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29500 45212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 45.sysrst_ctrl_ec_pwr_on_rst.2950045212 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.1739104241 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2577499817 ps |
| CPU time | 2.2 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:39:48 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17391 04241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.sysrst_ctrl_edge_detect.1739104241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.502261304 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2610916853 ps |
| CPU time | 8.87 seconds |
| Started | Aug 21 07:39:44 AM UTC 24 |
| Finished | Aug 21 07:39:54 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=502261304 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_ out.502261304 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.2516411680 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 2470213409 ps |
| CPU time | 6.14 seconds |
| Started | Aug 21 07:39:32 AM UTC 24 |
| Finished | Aug 21 07:39:39 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2516411680 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inve rted.2516411680 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3338418942 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2120286993 ps |
| CPU time | 7.9 seconds |
| Started | Aug 21 07:39:33 AM UTC 24 |
| Finished | Aug 21 07:39:42 AM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3338418942 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3338418942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.265604361 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2530321754 ps |
| CPU time | 1.91 seconds |
| Started | Aug 21 07:39:44 AM UTC 24 |
| Finished | Aug 21 07:39:47 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=265604361 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.265604361 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.1167322249 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2109073402 ps |
| CPU time | 10.67 seconds |
| Started | Aug 21 07:39:31 AM UTC 24 |
| Finished | Aug 21 07:39:43 AM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1167322249 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.1167322249 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.3435692655 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 29145265396 ps |
| CPU time | 85.76 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:41:12 AM UTC 24 |
| Peak memory | 210228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34356926 55 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45 .sysrst_ctrl_stress_all.3435692655 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4015730323 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 7012233208 ps |
| CPU time | 25.95 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:40:12 AM UTC 24 |
| Peak memory | 226688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4015730323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.4015730323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.977381578 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 452137329926 ps |
| CPU time | 171.74 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:42:39 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=97738 1578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 45.sysrst_ctrl_ultra_low_pwr.977381578 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1411883983 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2016117861 ps |
| CPU time | 3.67 seconds |
| Started | Aug 21 07:39:57 AM UTC 24 |
| Finished | Aug 21 07:40:01 AM UTC 24 |
| Peak memory | 210132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1411883983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst _ctrl_alert_test.1411883983 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.398016466 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 105099233063 ps |
| CPU time | 151.16 seconds |
| Started | Aug 21 07:39:50 AM UTC 24 |
| Finished | Aug 21 07:42:24 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=398016466 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk _key_output.398016466 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2537803681 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 107490481110 ps |
| CPU time | 39.73 seconds |
| Started | Aug 21 07:39:50 AM UTC 24 |
| Finished | Aug 21 07:40:32 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25378 03681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 46.sysrst_ctrl_combo_detect.2537803681 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.4270939134 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 4053429420 ps |
| CPU time | 19.32 seconds |
| Started | Aug 21 07:39:49 AM UTC 24 |
| Finished | Aug 21 07:40:10 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42709 39134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sysrst_ctrl_ec_pwr_on_rst.4270939134 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.2513882164 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5099969853 ps |
| CPU time | 25.66 seconds |
| Started | Aug 21 07:39:54 AM UTC 24 |
| Finished | Aug 21 07:40:21 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25138 82164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.sysrst_ctrl_edge_detect.2513882164 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.549943238 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2611261332 ps |
| CPU time | 12.54 seconds |
| Started | Aug 21 07:39:48 AM UTC 24 |
| Finished | Aug 21 07:40:02 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549943238 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_ out.549943238 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1210355267 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2474907746 ps |
| CPU time | 5.74 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:39:52 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1210355267 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inve rted.1210355267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3921952279 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2180984265 ps |
| CPU time | 3.38 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:39:50 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3921952279 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3921952279 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.3335840032 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2531548134 ps |
| CPU time | 4.08 seconds |
| Started | Aug 21 07:39:48 AM UTC 24 |
| Finished | Aug 21 07:39:53 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3335840032 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_t est.3335840032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.456886600 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2125305648 ps |
| CPU time | 3.13 seconds |
| Started | Aug 21 07:39:45 AM UTC 24 |
| Finished | Aug 21 07:39:49 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456886600 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.456886600 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.2356737072 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 16747319106 ps |
| CPU time | 59.22 seconds |
| Started | Aug 21 07:39:55 AM UTC 24 |
| Finished | Aug 21 07:40:56 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=23567370 72 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sysrst_ctrl_stress_all.2356737072 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.56793358 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 21576828846 ps |
| CPU time | 23.17 seconds |
| Started | Aug 21 07:39:54 AM UTC 24 |
| Finished | Aug 21 07:40:19 AM UTC 24 |
| Peak memory | 220516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=56793358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysr st_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.56793358 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4234616991 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4144184869 ps |
| CPU time | 10.32 seconds |
| Started | Aug 21 07:39:50 AM UTC 24 |
| Finished | Aug 21 07:40:02 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42346 16991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 46.sysrst_ctrl_ultra_low_pwr.4234616991 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3110817031 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2024068852 ps |
| CPU time | 3.33 seconds |
| Started | Aug 21 07:40:30 AM UTC 24 |
| Finished | Aug 21 07:40:35 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3110817031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst _ctrl_alert_test.3110817031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.118100773 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3112660535 ps |
| CPU time | 6.99 seconds |
| Started | Aug 21 07:40:12 AM UTC 24 |
| Finished | Aug 21 07:40:20 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=118100773 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk _key_output.118100773 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.1012953373 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 75781750439 ps |
| CPU time | 13.09 seconds |
| Started | Aug 21 07:40:13 AM UTC 24 |
| Finished | Aug 21 07:40:28 AM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10129 53373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 47.sysrst_ctrl_combo_detect.1012953373 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.4256365223 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3398841359 ps |
| CPU time | 6.96 seconds |
| Started | Aug 21 07:40:12 AM UTC 24 |
| Finished | Aug 21 07:40:20 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42563 65223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.sysrst_ctrl_ec_pwr_on_rst.4256365223 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.353451327 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2812572988 ps |
| CPU time | 2.3 seconds |
| Started | Aug 21 07:40:18 AM UTC 24 |
| Finished | Aug 21 07:40:21 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35345 1327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.353451327 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3166949115 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2622987914 ps |
| CPU time | 4.32 seconds |
| Started | Aug 21 07:40:12 AM UTC 24 |
| Finished | Aug 21 07:40:18 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3166949115 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot _out.3166949115 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.1063617711 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 2471098855 ps |
| CPU time | 6.45 seconds |
| Started | Aug 21 07:40:02 AM UTC 24 |
| Finished | Aug 21 07:40:09 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1063617711 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inve rted.1063617711 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.1925403015 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 2222078914 ps |
| CPU time | 3.73 seconds |
| Started | Aug 21 07:40:12 AM UTC 24 |
| Finished | Aug 21 07:40:17 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1925403015 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.1925403015 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1389458545 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2522937254 ps |
| CPU time | 3.65 seconds |
| Started | Aug 21 07:40:12 AM UTC 24 |
| Finished | Aug 21 07:40:17 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389458545 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_t est.1389458545 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.708256783 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2119296727 ps |
| CPU time | 5.49 seconds |
| Started | Aug 21 07:40:00 AM UTC 24 |
| Finished | Aug 21 07:40:06 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708256783 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.708256783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1759854585 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 98564792695 ps |
| CPU time | 70.7 seconds |
| Started | Aug 21 07:40:19 AM UTC 24 |
| Finished | Aug 21 07:41:31 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17598545 85 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sysrst_ctrl_stress_all.1759854585 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2265421948 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4809018773 ps |
| CPU time | 17.17 seconds |
| Started | Aug 21 07:40:18 AM UTC 24 |
| Finished | Aug 21 07:40:36 AM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2265421948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.2265421948 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.4062735726 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3456366207 ps |
| CPU time | 8.81 seconds |
| Started | Aug 21 07:40:12 AM UTC 24 |
| Finished | Aug 21 07:40:22 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40627 35726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 47.sysrst_ctrl_ultra_low_pwr.4062735726 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1253137927 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2015244689 ps |
| CPU time | 10.43 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:47 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1253137927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst _ctrl_alert_test.1253137927 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3659658362 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3282980932 ps |
| CPU time | 2.33 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:39 AM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3659658362 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_bl k_key_output.3659658362 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1466171847 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 61896418489 ps |
| CPU time | 43.7 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:41:21 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14661 71847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 48.sysrst_ctrl_combo_detect.1466171847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1630815182 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 45036510417 ps |
| CPU time | 28.61 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:41:06 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1630815182 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ combo_detect_with_pre_cond.1630815182 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1838010886 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 417945228041 ps |
| CPU time | 585.32 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:50:27 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18380 10886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 48.sysrst_ctrl_ec_pwr_on_rst.1838010886 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3186005844 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2619410741 ps |
| CPU time | 4.25 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:41 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3186005844 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot _out.3186005844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2215130752 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2447910116 ps |
| CPU time | 7.13 seconds |
| Started | Aug 21 07:40:30 AM UTC 24 |
| Finished | Aug 21 07:40:39 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2215130752 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inve rted.2215130752 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3630452155 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 2161652436 ps |
| CPU time | 3.1 seconds |
| Started | Aug 21 07:40:35 AM UTC 24 |
| Finished | Aug 21 07:40:40 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3630452155 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3630452155 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.2891801498 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2516258083 ps |
| CPU time | 5.73 seconds |
| Started | Aug 21 07:40:35 AM UTC 24 |
| Finished | Aug 21 07:40:42 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2891801498 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_t est.2891801498 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3675704637 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2119895087 ps |
| CPU time | 3.42 seconds |
| Started | Aug 21 07:40:30 AM UTC 24 |
| Finished | Aug 21 07:40:35 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675704637 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3675704637 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1099721852 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 116476302227 ps |
| CPU time | 323.09 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:46:03 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10997218 52 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48 .sysrst_ctrl_stress_all.1099721852 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3763822346 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3433989826 ps |
| CPU time | 9.9 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:47 AM UTC 24 |
| Peak memory | 220252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3763822346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3763822346 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.483032626 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 8153848047 ps |
| CPU time | 6.55 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:43 AM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=48303 2626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 48.sysrst_ctrl_ultra_low_pwr.483032626 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.3409696669 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 2015247961 ps |
| CPU time | 9.02 seconds |
| Started | Aug 21 07:40:44 AM UTC 24 |
| Finished | Aug 21 07:40:54 AM UTC 24 |
| Peak memory | 209800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3409696669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst _ctrl_alert_test.3409696669 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1939827097 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3529352698 ps |
| CPU time | 9.42 seconds |
| Started | Aug 21 07:40:40 AM UTC 24 |
| Finished | Aug 21 07:40:51 AM UTC 24 |
| Peak memory | 210276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1939827097 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_bl k_key_output.1939827097 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3836829325 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 134776713790 ps |
| CPU time | 115.8 seconds |
| Started | Aug 21 07:40:42 AM UTC 24 |
| Finished | Aug 21 07:42:39 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38368 29325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 49.sysrst_ctrl_combo_detect.3836829325 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3955981031 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 28935334412 ps |
| CPU time | 6.87 seconds |
| Started | Aug 21 07:40:42 AM UTC 24 |
| Finished | Aug 21 07:40:50 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3955981031 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ combo_detect_with_pre_cond.3955981031 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3921800347 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 5386533726 ps |
| CPU time | 5.59 seconds |
| Started | Aug 21 07:40:40 AM UTC 24 |
| Finished | Aug 21 07:40:47 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=39218 00347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sysrst_ctrl_ec_pwr_on_rst.3921800347 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.1095966414 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3175294540 ps |
| CPU time | 3.82 seconds |
| Started | Aug 21 07:40:42 AM UTC 24 |
| Finished | Aug 21 07:40:46 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10959 66414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.sysrst_ctrl_edge_detect.1095966414 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3427464249 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2616089803 ps |
| CPU time | 6.44 seconds |
| Started | Aug 21 07:40:40 AM UTC 24 |
| Finished | Aug 21 07:40:48 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3427464249 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot _out.3427464249 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.99515965 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2465532066 ps |
| CPU time | 3.52 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:41 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99515965 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.99515965 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.565556672 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2116989876 ps |
| CPU time | 2.3 seconds |
| Started | Aug 21 07:40:37 AM UTC 24 |
| Finished | Aug 21 07:40:40 AM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=565556672 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/op entitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.565556672 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.2835334838 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2532486148 ps |
| CPU time | 2.52 seconds |
| Started | Aug 21 07:40:39 AM UTC 24 |
| Finished | Aug 21 07:40:43 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2835334838 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_t est.2835334838 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.89614496 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2109976191 ps |
| CPU time | 10.46 seconds |
| Started | Aug 21 07:40:36 AM UTC 24 |
| Finished | Aug 21 07:40:48 AM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89614496 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita n/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.89614496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.3031791217 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 1613571927270 ps |
| CPU time | 401.25 seconds |
| Started | Aug 21 07:40:44 AM UTC 24 |
| Finished | Aug 21 07:47:29 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30317912 17 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sysrst_ctrl_stress_all.3031791217 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.401637959 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3999849230 ps |
| CPU time | 13.38 seconds |
| Started | Aug 21 07:40:43 AM UTC 24 |
| Finished | Aug 21 07:40:57 AM UTC 24 |
| Peak memory | 226872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=401637959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sys rst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.401637959 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2412832465 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2767665294 ps |
| CPU time | 3.27 seconds |
| Started | Aug 21 07:40:42 AM UTC 24 |
| Finished | Aug 21 07:40:46 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24128 32465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 49.sysrst_ctrl_ultra_low_pwr.2412832465 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.99725224 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2041952197 ps |
| CPU time | 3.05 seconds |
| Started | Aug 21 07:29:04 AM UTC 24 |
| Finished | Aug 21 07:29:08 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99725224 -a ssert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct rl_alert_test.99725224 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3115163534 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3806266460 ps |
| CPU time | 7.62 seconds |
| Started | Aug 21 07:28:43 AM UTC 24 |
| Finished | Aug 21 07:28:51 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3115163534 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk _key_output.3115163534 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3415050032 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 127890608442 ps |
| CPU time | 415.23 seconds |
| Started | Aug 21 07:28:47 AM UTC 24 |
| Finished | Aug 21 07:35:47 AM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34150 50032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 5.sysrst_ctrl_combo_detect.3415050032 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3430673520 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 42107961554 ps |
| CPU time | 34.74 seconds |
| Started | Aug 21 07:28:51 AM UTC 24 |
| Finished | Aug 21 07:29:27 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3430673520 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_c ombo_detect_with_pre_cond.3430673520 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.604051282 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3606402702 ps |
| CPU time | 9.78 seconds |
| Started | Aug 21 07:28:39 AM UTC 24 |
| Finished | Aug 21 07:28:50 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=60405 1282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 5.sysrst_ctrl_ec_pwr_on_rst.604051282 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.1728966427 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3926345707 ps |
| CPU time | 9.46 seconds |
| Started | Aug 21 07:28:48 AM UTC 24 |
| Finished | Aug 21 07:28:59 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17289 66427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.sysrst_ctrl_edge_detect.1728966427 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.572661793 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2629109255 ps |
| CPU time | 3.81 seconds |
| Started | Aug 21 07:28:38 AM UTC 24 |
| Finished | Aug 21 07:28:43 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=572661793 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.572661793 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.606697876 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 2455743547 ps |
| CPU time | 8.95 seconds |
| Started | Aug 21 07:28:28 AM UTC 24 |
| Finished | Aug 21 07:28:38 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=606697876 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.606697876 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.3664987809 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2258796832 ps |
| CPU time | 6.32 seconds |
| Started | Aug 21 07:28:34 AM UTC 24 |
| Finished | Aug 21 07:28:42 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3664987809 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.3664987809 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2231821489 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2516512141 ps |
| CPU time | 8.68 seconds |
| Started | Aug 21 07:28:36 AM UTC 24 |
| Finished | Aug 21 07:28:46 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2231821489 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_te st.2231821489 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3458535227 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2110823721 ps |
| CPU time | 10.25 seconds |
| Started | Aug 21 07:28:26 AM UTC 24 |
| Finished | Aug 21 07:28:37 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458535227 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3458535227 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3075352339 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 9541484716 ps |
| CPU time | 6.38 seconds |
| Started | Aug 21 07:28:59 AM UTC 24 |
| Finished | Aug 21 07:29:07 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30753523 39 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5. sysrst_ctrl_stress_all.3075352339 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4224640062 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 8962177523 ps |
| CPU time | 2.41 seconds |
| Started | Aug 21 07:28:44 AM UTC 24 |
| Finished | Aug 21 07:28:47 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42246 40062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 5.sysrst_ctrl_ultra_low_pwr.4224640062 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1504321439 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 133924875766 ps |
| CPU time | 136.51 seconds |
| Started | Aug 21 07:40:46 AM UTC 24 |
| Finished | Aug 21 07:43:05 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1504321439 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_ combo_detect_with_pre_cond.1504321439 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3375243190 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 48421708714 ps |
| CPU time | 183.27 seconds |
| Started | Aug 21 07:40:47 AM UTC 24 |
| Finished | Aug 21 07:43:53 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3375243190 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_ combo_detect_with_pre_cond.3375243190 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.491557267 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 24580452722 ps |
| CPU time | 80.76 seconds |
| Started | Aug 21 07:40:47 AM UTC 24 |
| Finished | Aug 21 07:42:10 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=491557267 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_c ombo_detect_with_pre_cond.491557267 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2806501416 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 31081572444 ps |
| CPU time | 101.99 seconds |
| Started | Aug 21 07:40:48 AM UTC 24 |
| Finished | Aug 21 07:42:32 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2806501416 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_ combo_detect_with_pre_cond.2806501416 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2335783061 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 79084387334 ps |
| CPU time | 164.72 seconds |
| Started | Aug 21 07:40:49 AM UTC 24 |
| Finished | Aug 21 07:43:36 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2335783061 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_ combo_detect_with_pre_cond.2335783061 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4567388 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 78532717597 ps |
| CPU time | 236.53 seconds |
| Started | Aug 21 07:40:49 AM UTC 24 |
| Finished | Aug 21 07:44:48 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4567388 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_com bo_detect_with_pre_cond.4567388 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3210891452 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 191591045935 ps |
| CPU time | 492.77 seconds |
| Started | Aug 21 07:40:49 AM UTC 24 |
| Finished | Aug 21 07:49:07 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3210891452 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_ combo_detect_with_pre_cond.3210891452 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.1613316006 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2019791981 ps |
| CPU time | 6.22 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:40 AM UTC 24 |
| Peak memory | 209816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613316006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ ctrl_alert_test.1613316006 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1744842513 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3717561684 ps |
| CPU time | 3.27 seconds |
| Started | Aug 21 07:29:20 AM UTC 24 |
| Finished | Aug 21 07:29:25 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1744842513 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk _key_output.1744842513 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.819589385 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 28010183899 ps |
| CPU time | 80.13 seconds |
| Started | Aug 21 07:29:24 AM UTC 24 |
| Finished | Aug 21 07:30:45 AM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81958 9385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 6.sysrst_ctrl_combo_detect.819589385 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2944651989 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 55889250274 ps |
| CPU time | 13.85 seconds |
| Started | Aug 21 07:29:24 AM UTC 24 |
| Finished | Aug 21 07:29:39 AM UTC 24 |
| Peak memory | 210584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2944651989 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_c ombo_detect_with_pre_cond.2944651989 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2417060369 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3188623258 ps |
| CPU time | 4.31 seconds |
| Started | Aug 21 07:29:19 AM UTC 24 |
| Finished | Aug 21 07:29:25 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24170 60369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.sysrst_ctrl_ec_pwr_on_rst.2417060369 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.997986847 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2632983161 ps |
| CPU time | 4.41 seconds |
| Started | Aug 21 07:29:14 AM UTC 24 |
| Finished | Aug 21 07:29:20 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=997986847 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.997986847 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.767773080 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2471350998 ps |
| CPU time | 2.37 seconds |
| Started | Aug 21 07:29:09 AM UTC 24 |
| Finished | Aug 21 07:29:13 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=767773080 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.767773080 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.1552228819 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2239774357 ps |
| CPU time | 9.86 seconds |
| Started | Aug 21 07:29:12 AM UTC 24 |
| Finished | Aug 21 07:29:23 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1552228819 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1552228819 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.842113378 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2523471384 ps |
| CPU time | 4.27 seconds |
| Started | Aug 21 07:29:14 AM UTC 24 |
| Finished | Aug 21 07:29:19 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=842113378 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.842113378 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.874623408 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2110868164 ps |
| CPU time | 9.95 seconds |
| Started | Aug 21 07:29:07 AM UTC 24 |
| Finished | Aug 21 07:29:19 AM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=874623408 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.874623408 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1893068345 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 8783091567 ps |
| CPU time | 11.62 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:45 AM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18930683 45 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6. sysrst_ctrl_stress_all.1893068345 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1389943635 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 13282558501 ps |
| CPU time | 17.54 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:51 AM UTC 24 |
| Peak memory | 220492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389943635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1389943635 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1004344990 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 4529801122 ps |
| CPU time | 3.82 seconds |
| Started | Aug 21 07:29:20 AM UTC 24 |
| Finished | Aug 21 07:29:25 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10043 44990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 6.sysrst_ctrl_ultra_low_pwr.1004344990 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.989043715 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 52781804044 ps |
| CPU time | 87.4 seconds |
| Started | Aug 21 07:40:52 AM UTC 24 |
| Finished | Aug 21 07:42:21 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=989043715 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_c ombo_detect_with_pre_cond.989043715 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1424513679 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 88938197412 ps |
| CPU time | 38.63 seconds |
| Started | Aug 21 07:40:55 AM UTC 24 |
| Finished | Aug 21 07:41:35 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1424513679 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_ combo_detect_with_pre_cond.1424513679 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1480500906 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 74263858152 ps |
| CPU time | 190.59 seconds |
| Started | Aug 21 07:40:55 AM UTC 24 |
| Finished | Aug 21 07:44:08 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480500906 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_ combo_detect_with_pre_cond.1480500906 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3253439374 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 31037114831 ps |
| CPU time | 28.94 seconds |
| Started | Aug 21 07:40:58 AM UTC 24 |
| Finished | Aug 21 07:41:28 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3253439374 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_ combo_detect_with_pre_cond.3253439374 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1220541323 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 54762014991 ps |
| CPU time | 100.74 seconds |
| Started | Aug 21 07:40:59 AM UTC 24 |
| Finished | Aug 21 07:42:42 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220541323 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_ combo_detect_with_pre_cond.1220541323 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.897499119 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 42851835160 ps |
| CPU time | 134.94 seconds |
| Started | Aug 21 07:41:06 AM UTC 24 |
| Finished | Aug 21 07:43:24 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=897499119 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_c ombo_detect_with_pre_cond.897499119 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3089087836 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 28097808208 ps |
| CPU time | 18.5 seconds |
| Started | Aug 21 07:41:13 AM UTC 24 |
| Finished | Aug 21 07:41:33 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3089087836 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_ combo_detect_with_pre_cond.3089087836 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1968942280 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2011170769 ps |
| CPU time | 10.1 seconds |
| Started | Aug 21 07:29:44 AM UTC 24 |
| Finished | Aug 21 07:29:55 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1968942280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ ctrl_alert_test.1968942280 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2275820251 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 43378382133 ps |
| CPU time | 71.43 seconds |
| Started | Aug 21 07:29:41 AM UTC 24 |
| Finished | Aug 21 07:30:54 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2275820251 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_c ombo_detect_with_pre_cond.2275820251 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2015598589 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2664378393 ps |
| CPU time | 8.27 seconds |
| Started | Aug 21 07:29:38 AM UTC 24 |
| Finished | Aug 21 07:29:47 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20155 98589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.sysrst_ctrl_ec_pwr_on_rst.2015598589 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.3463728788 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2938042431 ps |
| CPU time | 10.76 seconds |
| Started | Aug 21 07:29:41 AM UTC 24 |
| Finished | Aug 21 07:29:53 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34637 28788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.sysrst_ctrl_edge_detect.3463728788 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.135757783 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2617825597 ps |
| CPU time | 4.11 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:38 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=135757783 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.135757783 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.1081001500 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2469427590 ps |
| CPU time | 14.05 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:47 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1081001500 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowr isc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inver ted.1081001500 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3491994832 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2221045172 ps |
| CPU time | 8.05 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:41 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491994832 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.3491994832 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.574699045 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2536016882 ps |
| CPU time | 4.33 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:38 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=574699045 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.574699045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.116487586 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2134972581 ps |
| CPU time | 3.37 seconds |
| Started | Aug 21 07:29:32 AM UTC 24 |
| Finished | Aug 21 07:29:37 AM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=116487586 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit an/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.116487586 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.933412745 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 587292744473 ps |
| CPU time | 879.92 seconds |
| Started | Aug 21 07:29:44 AM UTC 24 |
| Finished | Aug 21 07:44:33 AM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=93341274 5 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.s ysrst_ctrl_stress_all.933412745 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3214461128 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 16192656281 ps |
| CPU time | 15.85 seconds |
| Started | Aug 21 07:29:44 AM UTC 24 |
| Finished | Aug 21 07:30:01 AM UTC 24 |
| Peak memory | 220556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214461128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3214461128 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1973589476 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4404457244 ps |
| CPU time | 9.86 seconds |
| Started | Aug 21 07:29:39 AM UTC 24 |
| Finished | Aug 21 07:29:50 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19735 89476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 7.sysrst_ctrl_ultra_low_pwr.1973589476 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.867602050 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 25597327016 ps |
| CPU time | 23.19 seconds |
| Started | Aug 21 07:41:23 AM UTC 24 |
| Finished | Aug 21 07:41:47 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867602050 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_c ombo_detect_with_pre_cond.867602050 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1042014312 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 98753420611 ps |
| CPU time | 158.14 seconds |
| Started | Aug 21 07:41:25 AM UTC 24 |
| Finished | Aug 21 07:44:06 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1042014312 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_ combo_detect_with_pre_cond.1042014312 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1248549010 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 38798623559 ps |
| CPU time | 52.47 seconds |
| Started | Aug 21 07:41:27 AM UTC 24 |
| Finished | Aug 21 07:42:21 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1248549010 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_ combo_detect_with_pre_cond.1248549010 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.4185310549 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 28452576572 ps |
| CPU time | 21.75 seconds |
| Started | Aug 21 07:41:29 AM UTC 24 |
| Finished | Aug 21 07:41:52 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4185310549 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_ combo_detect_with_pre_cond.4185310549 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4259217168 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 22080156525 ps |
| CPU time | 67.36 seconds |
| Started | Aug 21 07:41:32 AM UTC 24 |
| Finished | Aug 21 07:42:41 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4259217168 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_ combo_detect_with_pre_cond.4259217168 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1743280129 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 59161408393 ps |
| CPU time | 225.34 seconds |
| Started | Aug 21 07:41:34 AM UTC 24 |
| Finished | Aug 21 07:45:23 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743280129 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_ combo_detect_with_pre_cond.1743280129 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3077250465 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 26590839745 ps |
| CPU time | 39.47 seconds |
| Started | Aug 21 07:41:35 AM UTC 24 |
| Finished | Aug 21 07:42:16 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3077250465 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_ combo_detect_with_pre_cond.3077250465 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.740936045 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 57632564343 ps |
| CPU time | 25.01 seconds |
| Started | Aug 21 07:41:35 AM UTC 24 |
| Finished | Aug 21 07:42:02 AM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=740936045 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_c ombo_detect_with_pre_cond.740936045 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2403489363 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2010900802 ps |
| CPU time | 10.27 seconds |
| Started | Aug 21 07:29:59 AM UTC 24 |
| Finished | Aug 21 07:30:10 AM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2403489363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ ctrl_alert_test.2403489363 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3943670708 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3060040141 ps |
| CPU time | 9.71 seconds |
| Started | Aug 21 07:29:53 AM UTC 24 |
| Finished | Aug 21 07:30:03 AM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3943670708 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk _key_output.3943670708 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1766517654 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 26604105374 ps |
| CPU time | 20.52 seconds |
| Started | Aug 21 07:29:56 AM UTC 24 |
| Finished | Aug 21 07:30:18 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1766517654 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_c ombo_detect_with_pre_cond.1766517654 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3611768864 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3993788981 ps |
| CPU time | 16.25 seconds |
| Started | Aug 21 07:29:52 AM UTC 24 |
| Finished | Aug 21 07:30:09 AM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36117 68864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sysrst_ctrl_ec_pwr_on_rst.3611768864 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3638472233 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2537122380 ps |
| CPU time | 5.98 seconds |
| Started | Aug 21 07:29:55 AM UTC 24 |
| Finished | Aug 21 07:30:02 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36384 72233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.sysrst_ctrl_edge_detect.3638472233 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1825366151 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2613990657 ps |
| CPU time | 7.27 seconds |
| Started | Aug 21 07:29:50 AM UTC 24 |
| Finished | Aug 21 07:29:59 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1825366151 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_ out.1825366151 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.312697659 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2502405166 ps |
| CPU time | 4.8 seconds |
| Started | Aug 21 07:29:46 AM UTC 24 |
| Finished | Aug 21 07:29:52 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=312697659 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowri sc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.312697659 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2073639942 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2194561841 ps |
| CPU time | 4.2 seconds |
| Started | Aug 21 07:29:47 AM UTC 24 |
| Finished | Aug 21 07:29:52 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2073639942 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2073639942 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.2036675263 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2524195143 ps |
| CPU time | 4.28 seconds |
| Started | Aug 21 07:29:48 AM UTC 24 |
| Finished | Aug 21 07:29:54 AM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2036675263 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc /opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_te st.2036675263 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.2892786632 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2113298433 ps |
| CPU time | 7.93 seconds |
| Started | Aug 21 07:29:46 AM UTC 24 |
| Finished | Aug 21 07:29:55 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2892786632 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2892786632 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.363416657 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 82138550718 ps |
| CPU time | 132.24 seconds |
| Started | Aug 21 07:29:57 AM UTC 24 |
| Finished | Aug 21 07:32:12 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36341665 7 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ysrst_ctrl_stress_all.363416657 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2820615069 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 6857172478 ps |
| CPU time | 17.48 seconds |
| Started | Aug 21 07:29:56 AM UTC 24 |
| Finished | Aug 21 07:30:15 AM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2820615069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.2820615069 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2718611844 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 7028737353 ps |
| CPU time | 6.73 seconds |
| Started | Aug 21 07:29:54 AM UTC 24 |
| Finished | Aug 21 07:30:01 AM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27186 11844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 8.sysrst_ctrl_ultra_low_pwr.2718611844 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1484112755 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 26589975483 ps |
| CPU time | 49.06 seconds |
| Started | Aug 21 07:41:38 AM UTC 24 |
| Finished | Aug 21 07:42:28 AM UTC 24 |
| Peak memory | 210320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1484112755 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_ combo_detect_with_pre_cond.1484112755 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1712851059 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 57831126829 ps |
| CPU time | 54.53 seconds |
| Started | Aug 21 07:41:40 AM UTC 24 |
| Finished | Aug 21 07:42:36 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1712851059 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_ combo_detect_with_pre_cond.1712851059 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.781848592 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 95636758325 ps |
| CPU time | 291.2 seconds |
| Started | Aug 21 07:41:45 AM UTC 24 |
| Finished | Aug 21 07:46:40 AM UTC 24 |
| Peak memory | 210304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=781848592 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_c ombo_detect_with_pre_cond.781848592 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3891020241 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 27099065050 ps |
| CPU time | 18.85 seconds |
| Started | Aug 21 07:41:46 AM UTC 24 |
| Finished | Aug 21 07:42:06 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3891020241 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_ combo_detect_with_pre_cond.3891020241 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1967172160 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 55721906313 ps |
| CPU time | 170.85 seconds |
| Started | Aug 21 07:41:48 AM UTC 24 |
| Finished | Aug 21 07:44:41 AM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967172160 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_ combo_detect_with_pre_cond.1967172160 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1439316913 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 26365317243 ps |
| CPU time | 17.33 seconds |
| Started | Aug 21 07:41:53 AM UTC 24 |
| Finished | Aug 21 07:42:11 AM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1439316913 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_ combo_detect_with_pre_cond.1439316913 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1460948786 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 26338294933 ps |
| CPU time | 63.31 seconds |
| Started | Aug 21 07:42:02 AM UTC 24 |
| Finished | Aug 21 07:43:07 AM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1460948786 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_ combo_detect_with_pre_cond.1460948786 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.252951028 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 48482205500 ps |
| CPU time | 86.72 seconds |
| Started | Aug 21 07:42:03 AM UTC 24 |
| Finished | Aug 21 07:43:32 AM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=252951028 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_c ombo_detect_with_pre_cond.252951028 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2789674780 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 29878809320 ps |
| CPU time | 11.32 seconds |
| Started | Aug 21 07:42:06 AM UTC 24 |
| Finished | Aug 21 07:42:19 AM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2789674780 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_ combo_detect_with_pre_cond.2789674780 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.346888419 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2029136055 ps |
| CPU time | 4.11 seconds |
| Started | Aug 21 07:30:18 AM UTC 24 |
| Finished | Aug 21 07:30:23 AM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=346888419 - assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c trl_alert_test.346888419 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4091610611 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3650727862 ps |
| CPU time | 7.61 seconds |
| Started | Aug 21 07:30:09 AM UTC 24 |
| Finished | Aug 21 07:30:18 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4091610611 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk _key_output.4091610611 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3683666333 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 159932720599 ps |
| CPU time | 46.6 seconds |
| Started | Aug 21 07:30:11 AM UTC 24 |
| Finished | Aug 21 07:30:59 AM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=36836 66333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_na me 9.sysrst_ctrl_combo_detect.3683666333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3232835583 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 86378284672 ps |
| CPU time | 120.82 seconds |
| Started | Aug 21 07:30:12 AM UTC 24 |
| Finished | Aug 21 07:32:15 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232835583 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_c ombo_detect_with_pre_cond.3232835583 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2154392333 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 296598436237 ps |
| CPU time | 732.5 seconds |
| Started | Aug 21 07:30:08 AM UTC 24 |
| Finished | Aug 21 07:42:28 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=21543 92333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 9.sysrst_ctrl_ec_pwr_on_rst.2154392333 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4260319754 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2687081592 ps |
| CPU time | 11.08 seconds |
| Started | Aug 21 07:30:11 AM UTC 24 |
| Finished | Aug 21 07:30:23 AM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=42603 19754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.sysrst_ctrl_edge_detect.4260319754 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3710778906 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2628003983 ps |
| CPU time | 5.06 seconds |
| Started | Aug 21 07:30:06 AM UTC 24 |
| Finished | Aug 21 07:30:12 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3710778906 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_ out.3710778906 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.24578397 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2441993896 ps |
| CPU time | 7.68 seconds |
| Started | Aug 21 07:30:02 AM UTC 24 |
| Finished | Aug 21 07:30:11 AM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24578397 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowris c/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.24578397 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.2017198434 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2209062475 ps |
| CPU time | 6.65 seconds |
| Started | Aug 21 07:30:02 AM UTC 24 |
| Finished | Aug 21 07:30:10 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2017198434 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/o pentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2017198434 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.755056938 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2537757940 ps |
| CPU time | 2.38 seconds |
| Started | Aug 21 07:30:04 AM UTC 24 |
| Finished | Aug 21 07:30:08 AM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=755056938 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.755056938 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.1597922418 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2133501380 ps |
| CPU time | 3.83 seconds |
| Started | Aug 21 07:30:02 AM UTC 24 |
| Finished | Aug 21 07:30:07 AM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1597922418 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1597922418 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.3714638075 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 8724243486 ps |
| CPU time | 27.85 seconds |
| Started | Aug 21 07:30:15 AM UTC 24 |
| Finished | Aug 21 07:30:44 AM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37146380 75 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9. sysrst_ctrl_stress_all.3714638075 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3464754496 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 13564573357 ps |
| CPU time | 19.52 seconds |
| Started | Aug 21 07:30:12 AM UTC 24 |
| Finished | Aug 21 07:30:33 AM UTC 24 |
| Peak memory | 220468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns= 10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464754496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sy srst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3464754496 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1641372724 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 6342294562 ps |
| CPU time | 12.21 seconds |
| Started | Aug 21 07:30:10 AM UTC 24 |
| Finished | Aug 21 07:30:23 AM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16413 72724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n ame 9.sysrst_ctrl_ultra_low_pwr.1641372724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1846814724 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 71588695179 ps |
| CPU time | 84.49 seconds |
| Started | Aug 21 07:42:12 AM UTC 24 |
| Finished | Aug 21 07:43:39 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1846814724 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_ combo_detect_with_pre_cond.1846814724 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1411341812 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 101519036819 ps |
| CPU time | 283.22 seconds |
| Started | Aug 21 07:42:17 AM UTC 24 |
| Finished | Aug 21 07:47:03 AM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1411341812 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_ combo_detect_with_pre_cond.1411341812 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2482655380 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 27829821857 ps |
| CPU time | 85.62 seconds |
| Started | Aug 21 07:42:19 AM UTC 24 |
| Finished | Aug 21 07:43:46 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2482655380 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_ combo_detect_with_pre_cond.2482655380 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2263406230 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 107944268751 ps |
| CPU time | 63.83 seconds |
| Started | Aug 21 07:42:20 AM UTC 24 |
| Finished | Aug 21 07:43:25 AM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263406230 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_ combo_detect_with_pre_cond.2263406230 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.4027524519 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 24337563191 ps |
| CPU time | 35.83 seconds |
| Started | Aug 21 07:42:22 AM UTC 24 |
| Finished | Aug 21 07:42:59 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027524519 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_ combo_detect_with_pre_cond.4027524519 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2669769169 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 141665915051 ps |
| CPU time | 207.43 seconds |
| Started | Aug 21 07:42:22 AM UTC 24 |
| Finished | Aug 21 07:45:52 AM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2669769169 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_ combo_detect_with_pre_cond.2669769169 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3455053582 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 28376502793 ps |
| CPU time | 36.25 seconds |
| Started | Aug 21 07:42:25 AM UTC 24 |
| Finished | Aug 21 07:43:03 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3455053582 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_ combo_detect_with_pre_cond.3455053582 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3382462929 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 92596489701 ps |
| CPU time | 273.43 seconds |
| Started | Aug 21 07:42:28 AM UTC 24 |
| Finished | Aug 21 07:47:05 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3382462929 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_ combo_detect_with_pre_cond.3382462929 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2283427936 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 33326219260 ps |
| CPU time | 23.81 seconds |
| Started | Aug 21 07:42:29 AM UTC 24 |
| Finished | Aug 21 07:42:54 AM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2283427936 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_ combo_detect_with_pre_cond.2283427936 |
| Directory | /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest |
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