Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
4610 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
2 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
3390 |
1 |
|
|
T4 |
2 |
|
T5 |
2 |
|
T6 |
2 |
auto[1] |
1220 |
1 |
|
|
T24 |
2 |
|
T25 |
2 |
|
T15 |
2 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
2291 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
2 |
auto[1] |
2319 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T26 |
2 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
| | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
1675 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
2 |
all_values[0] |
auto[0] |
auto[1] |
1715 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T26 |
2 |
all_values[0] |
auto[1] |
auto[0] |
616 |
1 |
|
|
T24 |
2 |
|
T25 |
2 |
|
T15 |
1 |
all_values[0] |
auto[1] |
auto[1] |
604 |
1 |
|
|
T15 |
1 |
|
T17 |
2 |
|
T9 |
2 |