Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.11 99.35 96.81 100.00 97.44 98.78 99.61 87.79


Total tests in report: 920
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
42.38 42.38 66.34 66.34 46.36 46.36 54.79 54.79 4.49 4.49 69.17 69.17 54.05 54.05 1.46 1.46 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1925737091
67.48 25.10 88.11 21.78 73.66 27.30 58.68 3.88 73.08 68.59 88.84 19.67 86.22 32.18 3.75 2.30 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1488348031
75.56 8.08 91.58 3.47 84.15 10.49 87.67 29.00 73.08 0.00 92.46 3.62 87.76 1.54 12.21 8.45 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3422485083
78.76 3.20 94.87 3.28 88.90 4.75 88.81 1.14 73.72 0.64 95.82 3.36 89.69 1.93 19.48 7.28 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.576823612
81.31 2.55 95.84 0.97 89.94 1.04 95.21 6.39 73.72 0.00 96.01 0.18 90.27 0.58 28.16 8.68 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1071572620
83.54 2.23 96.40 0.56 91.03 1.09 95.55 0.34 73.72 0.00 96.19 0.18 92.29 2.02 39.59 11.42 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1958419146
85.21 1.67 97.13 0.73 91.13 0.10 96.69 1.14 82.69 8.97 96.75 0.55 92.39 0.10 39.70 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.2204539361
86.82 1.61 97.54 0.41 91.41 0.28 96.69 0.00 86.54 3.85 97.08 0.33 93.64 1.25 44.85 5.15 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.408172269
88.07 1.25 97.56 0.02 92.32 0.91 97.37 0.68 86.54 0.00 97.12 0.04 93.64 0.00 51.96 7.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1757333515
89.00 0.93 97.70 0.15 92.80 0.48 97.37 0.00 86.54 0.00 97.12 0.00 93.74 0.10 57.73 5.77 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3565376270
89.86 0.87 98.21 0.50 93.17 0.38 97.37 0.00 89.74 3.21 97.49 0.37 95.28 1.54 57.78 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1340183256
90.64 0.78 98.21 0.00 93.28 0.10 97.37 0.00 89.74 0.00 97.52 0.04 95.28 0.00 63.10 5.32 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2911253794
91.20 0.55 98.25 0.04 93.53 0.25 97.37 0.00 89.74 0.00 97.56 0.04 95.47 0.19 66.46 3.36 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2123012837
91.75 0.55 98.32 0.07 93.63 0.10 97.37 0.00 89.74 0.00 97.60 0.04 95.57 0.10 69.99 3.53 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.4207938139
92.19 0.45 98.38 0.06 93.71 0.08 97.37 0.00 89.74 0.00 97.63 0.04 95.57 0.00 72.96 2.97 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1906910897
92.57 0.37 98.51 0.13 94.03 0.33 97.37 0.00 91.03 1.28 97.82 0.18 96.24 0.67 72.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2246746904
92.88 0.32 98.51 0.00 94.06 0.03 99.20 1.83 91.03 0.00 97.82 0.00 96.34 0.10 73.24 0.28 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.4062127232
93.18 0.29 98.54 0.04 94.11 0.05 99.20 0.00 91.03 0.00 97.82 0.00 96.34 0.00 75.20 1.96 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.979262786
93.46 0.28 98.54 0.00 94.11 0.00 99.20 0.00 91.03 0.00 97.82 0.00 97.21 0.87 76.32 1.12 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3081710934
93.74 0.27 98.58 0.04 94.99 0.88 99.66 0.46 91.03 0.00 97.82 0.00 97.30 0.10 76.76 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1994746966
94.00 0.26 98.66 0.07 95.12 0.13 99.66 0.00 92.31 1.28 97.89 0.07 97.59 0.29 76.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.383525137
94.24 0.24 98.73 0.07 95.17 0.05 99.66 0.00 93.59 1.28 97.97 0.07 97.78 0.19 76.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.1479635419
94.45 0.21 98.79 0.06 95.58 0.40 99.66 0.00 93.59 0.00 98.11 0.15 98.55 0.77 76.88 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.472258562
94.65 0.20 98.84 0.06 95.63 0.05 99.66 0.00 94.23 0.64 98.19 0.07 98.65 0.10 77.38 0.50 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3252364275
94.86 0.20 98.90 0.06 95.75 0.13 99.66 0.00 94.87 0.64 98.26 0.07 98.94 0.29 77.60 0.22 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.4289579716
95.04 0.19 98.94 0.04 95.75 0.00 99.66 0.00 94.87 0.00 98.26 0.00 98.94 0.00 78.89 1.29 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2010859065
95.20 0.15 98.94 0.00 95.75 0.00 99.66 0.00 94.87 0.00 98.26 0.00 98.94 0.00 79.96 1.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1387630497
95.34 0.14 99.03 0.09 95.78 0.03 99.66 0.00 95.51 0.64 98.41 0.15 99.04 0.10 79.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.298028136
95.47 0.13 99.05 0.02 96.11 0.33 99.77 0.11 95.51 0.00 98.45 0.04 99.13 0.10 80.29 0.34 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3292189005
95.60 0.13 99.09 0.04 96.21 0.10 99.77 0.00 96.15 0.64 98.48 0.04 99.23 0.10 80.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1260261822
95.73 0.12 99.12 0.04 96.26 0.05 99.77 0.00 96.79 0.64 98.52 0.04 99.33 0.10 80.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2706620791
95.85 0.12 99.14 0.02 96.26 0.00 99.77 0.00 96.79 0.00 98.52 0.00 99.33 0.00 81.13 0.84 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.630536065
95.97 0.12 99.18 0.04 96.28 0.03 99.77 0.00 97.44 0.64 98.56 0.04 99.42 0.10 81.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.957071419
96.07 0.10 99.18 0.00 96.28 0.00 99.77 0.00 97.44 0.00 98.56 0.00 99.42 0.00 81.86 0.73 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2228350620
96.16 0.09 99.18 0.00 96.28 0.00 99.77 0.00 97.44 0.00 98.56 0.00 99.42 0.00 82.47 0.62 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3834553181
96.24 0.08 99.18 0.00 96.31 0.03 99.77 0.00 97.44 0.00 98.56 0.00 99.42 0.00 82.98 0.50 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3786368503
96.30 0.07 99.18 0.00 96.33 0.03 99.77 0.00 97.44 0.00 98.56 0.00 99.42 0.00 83.43 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2001984415
96.36 0.06 99.23 0.06 96.41 0.08 100.00 0.23 97.44 0.00 98.60 0.04 99.42 0.00 83.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1301941927
96.42 0.06 99.23 0.00 96.41 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.42 0.00 83.82 0.39 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2048614185
96.47 0.06 99.23 0.00 96.41 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.42 0.00 84.21 0.39 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1397225646
96.52 0.05 99.23 0.00 96.41 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.42 0.00 84.55 0.34 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.4171588969
96.57 0.05 99.23 0.00 96.41 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.42 0.00 84.88 0.34 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.683914118
96.61 0.04 99.25 0.02 96.44 0.03 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.10 85.05 0.17 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.786245189
96.65 0.04 99.25 0.00 96.44 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 85.33 0.28 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1771859387
96.69 0.04 99.25 0.00 96.44 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 85.61 0.28 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3997157525
96.73 0.04 99.25 0.00 96.49 0.05 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 85.83 0.22 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2834575016
96.76 0.03 99.25 0.00 96.49 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.52 0.00 86.06 0.22 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2158951950
96.79 0.03 99.25 0.00 96.54 0.05 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.10 86.11 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3166013491
96.82 0.02 99.25 0.00 96.54 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.28 0.17 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3067094698
96.83 0.02 99.25 0.00 96.66 0.13 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2029228022
96.85 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.39 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1788726252
96.87 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.51 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1381110097
96.88 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.62 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1436102550
96.90 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.73 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.49999855
96.91 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.84 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3761790651
96.93 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 86.95 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2316666761
96.95 0.02 99.25 0.00 96.66 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 87.07 0.11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2447308084
96.96 0.02 99.27 0.02 96.66 0.00 100.00 0.00 97.44 0.00 98.63 0.04 99.61 0.00 87.12 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3282734422
96.97 0.01 99.27 0.00 96.69 0.03 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.18 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.4012161278
96.98 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.23 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.767349306
96.99 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.29 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2175681952
97.00 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.35 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1910371864
97.01 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.40 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3659519508
97.01 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.46 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2460946737
97.02 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.51 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1059744559
97.03 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.57 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1849984292
97.04 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.63 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.9208738
97.05 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.68 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.2446396621
97.05 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.74 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4106575387
97.06 0.01 99.27 0.00 96.69 0.00 100.00 0.00 97.44 0.00 98.63 0.00 99.61 0.00 87.79 0.06 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.390983874
97.07 0.01 99.29 0.02 96.69 0.00 100.00 0.00 97.44 0.00 98.67 0.04 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.268299581
97.08 0.01 99.31 0.02 96.69 0.00 100.00 0.00 97.44 0.00 98.71 0.04 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2375559732
97.09 0.01 99.33 0.02 96.69 0.00 100.00 0.00 97.44 0.00 98.74 0.04 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.2940184562
97.09 0.01 99.35 0.02 96.69 0.00 100.00 0.00 97.44 0.00 98.78 0.04 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.3206374417
97.10 0.01 99.35 0.00 96.74 0.05 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3276009758
97.11 0.01 99.35 0.00 96.76 0.03 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.4280630365
97.11 0.01 99.35 0.00 96.79 0.03 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 87.79 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3111263118

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3912727111
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1348194705
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.515429792
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1528229446
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3256736590
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.389016329
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1481620138
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3990518141
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2237443540
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3291734659
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1386565988
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2082903059
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2024673006
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3983370770
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.989257186
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4244721048
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2281719739
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.19563116
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2898294658
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2437199798
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1786473871
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2313408425
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1449574548
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3447447438
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3010867903
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1087446110
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3520242317
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.716828634
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1941749097
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2634011042
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2769215670
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.25748287
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2925075252
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.4128939299
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3732252044
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.4170990081
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3231726349
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3086968102
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.305340100
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.386170838
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3792987061
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2581774810
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2162066862
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3949516808
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3605620942
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3975230624
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3190198060
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3369463696
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4097400462
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1038047305
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3745299081
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2643575781
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4228132996
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2363223887
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1399421903
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3340862637
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.594160876
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2510351015
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.96939393
/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2050416090
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3971320305
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.254688437
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3241306582
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/workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.47661001
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Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1761629194 Aug 23 05:15:11 PM UTC 24 Aug 23 05:15:13 PM UTC 24 2239367639 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2403629115 Aug 23 05:15:11 PM UTC 24 Aug 23 05:15:13 PM UTC 24 2526385440 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.692059555 Aug 23 05:15:12 PM UTC 24 Aug 23 05:15:15 PM UTC 24 3469028123 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.3931075111 Aug 23 05:15:11 PM UTC 24 Aug 23 05:15:15 PM UTC 24 2120440372 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1071572620 Aug 23 05:15:12 PM UTC 24 Aug 23 05:15:15 PM UTC 24 2530541983 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2175681952 Aug 23 05:15:12 PM UTC 24 Aug 23 05:15:16 PM UTC 24 2802665160 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.2934474941 Aug 23 05:15:11 PM UTC 24 Aug 23 05:15:18 PM UTC 24 2035128533 ps
T1 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1925737091 Aug 23 05:15:11 PM UTC 24 Aug 23 05:15:19 PM UTC 24 2530410809 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.3696167937 Aug 23 05:15:16 PM UTC 24 Aug 23 05:15:19 PM UTC 24 2115432455 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.2221834204 Aug 23 05:15:15 PM UTC 24 Aug 23 05:15:19 PM UTC 24 2120491323 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1284470504 Aug 23 05:15:16 PM UTC 24 Aug 23 05:15:19 PM UTC 24 2387870977 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1677376495 Aug 23 05:15:12 PM UTC 24 Aug 23 05:15:20 PM UTC 24 2609753086 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3292189005 Aug 23 05:15:13 PM UTC 24 Aug 23 05:15:20 PM UTC 24 5419355735 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1223053512 Aug 23 05:15:17 PM UTC 24 Aug 23 05:15:20 PM UTC 24 2661727991 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2933908965 Aug 23 05:15:17 PM UTC 24 Aug 23 05:15:21 PM UTC 24 2668382960 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1301941927 Aug 23 05:15:15 PM UTC 24 Aug 23 05:15:22 PM UTC 24 2014582705 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.479650478 Aug 23 05:15:14 PM UTC 24 Aug 23 05:15:22 PM UTC 24 2782756100 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3672577539 Aug 23 05:15:15 PM UTC 24 Aug 23 05:15:23 PM UTC 24 2431758483 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3219285686 Aug 23 05:15:20 PM UTC 24 Aug 23 05:15:23 PM UTC 24 3655108745 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2422421533 Aug 23 05:15:16 PM UTC 24 Aug 23 05:15:23 PM UTC 24 2397442058 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1788726252 Aug 23 05:15:16 PM UTC 24 Aug 23 05:15:24 PM UTC 24 2513866329 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.460483312 Aug 23 05:15:20 PM UTC 24 Aug 23 05:15:24 PM UTC 24 3571611763 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2834575016 Aug 23 05:15:23 PM UTC 24 Aug 23 05:15:26 PM UTC 24 2556844907 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.791268794 Aug 23 05:15:23 PM UTC 24 Aug 23 05:15:26 PM UTC 24 2229715417 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2941540847 Aug 23 05:15:14 PM UTC 24 Aug 23 05:15:26 PM UTC 24 4213401169 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2650779050 Aug 23 05:15:23 PM UTC 24 Aug 23 05:15:26 PM UTC 24 2462196435 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.1316172079 Aug 23 05:15:23 PM UTC 24 Aug 23 05:15:27 PM UTC 24 2228592535 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.4171588969 Aug 23 05:15:18 PM UTC 24 Aug 23 05:15:27 PM UTC 24 3118154597 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.716406105 Aug 23 05:15:24 PM UTC 24 Aug 23 05:15:27 PM UTC 24 5472334971 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3422485083 Aug 23 05:15:21 PM UTC 24 Aug 23 05:15:28 PM UTC 24 12359553411 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.658980550 Aug 23 05:15:24 PM UTC 24 Aug 23 05:15:28 PM UTC 24 3863323724 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.2021254055 Aug 23 05:15:22 PM UTC 24 Aug 23 05:15:28 PM UTC 24 2010483681 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3875819508 Aug 23 05:15:22 PM UTC 24 Aug 23 05:15:28 PM UTC 24 2110324953 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2984141479 Aug 23 05:15:24 PM UTC 24 Aug 23 05:15:29 PM UTC 24 5197765386 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3180021229 Aug 23 05:15:24 PM UTC 24 Aug 23 05:15:29 PM UTC 24 2613284650 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.691233920 Aug 23 05:15:23 PM UTC 24 Aug 23 05:15:30 PM UTC 24 2263175504 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.3227352657 Aug 23 05:15:28 PM UTC 24 Aug 23 05:15:31 PM UTC 24 2037390919 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.4251250462 Aug 23 05:15:27 PM UTC 24 Aug 23 05:15:31 PM UTC 24 4892293463 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2050721939 Aug 23 05:15:29 PM UTC 24 Aug 23 05:15:32 PM UTC 24 2557212385 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.26646109 Aug 23 05:15:30 PM UTC 24 Aug 23 05:15:32 PM UTC 24 2551459007 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2707846629 Aug 23 05:15:30 PM UTC 24 Aug 23 05:15:33 PM UTC 24 2634785752 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2983067619 Aug 23 05:15:30 PM UTC 24 Aug 23 05:15:33 PM UTC 24 3148214994 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.338245744 Aug 23 05:15:28 PM UTC 24 Aug 23 05:15:34 PM UTC 24 2108713685 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1469905634 Aug 23 05:15:31 PM UTC 24 Aug 23 05:15:35 PM UTC 24 2932690846 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.327683693 Aug 23 05:15:29 PM UTC 24 Aug 23 05:15:35 PM UTC 24 2478366918 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2971102507 Aug 23 05:15:29 PM UTC 24 Aug 23 05:15:36 PM UTC 24 2069014252 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1793385428 Aug 23 05:15:29 PM UTC 24 Aug 23 05:15:36 PM UTC 24 2239733199 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.2204539361 Aug 23 05:15:14 PM UTC 24 Aug 23 05:15:36 PM UTC 24 38445874048 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3805830138 Aug 23 05:15:14 PM UTC 24 Aug 23 05:15:36 PM UTC 24 8763803394 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3652161413 Aug 23 05:15:21 PM UTC 24 Aug 23 05:15:36 PM UTC 24 22058105211 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3655562221 Aug 23 05:15:33 PM UTC 24 Aug 23 05:15:37 PM UTC 24 3905449647 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.2139568644 Aug 23 05:15:35 PM UTC 24 Aug 23 05:15:38 PM UTC 24 2030619393 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.3132558134 Aug 23 05:15:37 PM UTC 24 Aug 23 05:15:39 PM UTC 24 2535415884 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.246465344 Aug 23 05:15:32 PM UTC 24 Aug 23 05:15:39 PM UTC 24 6601600046 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2469205119 Aug 23 05:15:37 PM UTC 24 Aug 23 05:15:41 PM UTC 24 2119907922 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3221360066 Aug 23 05:15:35 PM UTC 24 Aug 23 05:15:41 PM UTC 24 7075990482 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.915321544 Aug 23 05:15:28 PM UTC 24 Aug 23 05:15:42 PM UTC 24 22072852583 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2746181435 Aug 23 05:15:14 PM UTC 24 Aug 23 05:15:42 PM UTC 24 25587348356 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.1154279846 Aug 23 05:15:37 PM UTC 24 Aug 23 05:15:43 PM UTC 24 2024807210 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3701251231 Aug 23 05:15:40 PM UTC 24 Aug 23 05:15:43 PM UTC 24 3317225465 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1739744996 Aug 23 05:15:37 PM UTC 24 Aug 23 05:15:44 PM UTC 24 2228592850 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.656693192 Aug 23 05:15:37 PM UTC 24 Aug 23 05:15:44 PM UTC 24 2517071454 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.878814233 Aug 23 05:15:45 PM UTC 24 Aug 23 05:15:53 PM UTC 24 2514295045 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1260261822 Aug 23 05:15:42 PM UTC 24 Aug 23 05:15:45 PM UTC 24 3842669143 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.1758683124 Aug 23 05:15:38 PM UTC 24 Aug 23 05:15:45 PM UTC 24 2515124914 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.931151627 Aug 23 05:15:39 PM UTC 24 Aug 23 05:15:48 PM UTC 24 2612304194 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.1051130095 Aug 23 05:15:45 PM UTC 24 Aug 23 05:15:48 PM UTC 24 2171519863 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.4164399478 Aug 23 05:15:39 PM UTC 24 Aug 23 05:15:48 PM UTC 24 2999239253 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.619583047 Aug 23 05:15:40 PM UTC 24 Aug 23 05:15:48 PM UTC 24 3235989108 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.2197587321 Aug 23 05:15:45 PM UTC 24 Aug 23 05:15:50 PM UTC 24 2471734654 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2810633549 Aug 23 05:15:44 PM UTC 24 Aug 23 05:15:51 PM UTC 24 2013100874 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.2422852758 Aug 23 05:15:44 PM UTC 24 Aug 23 05:15:51 PM UTC 24 2111932847 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2760357086 Aug 23 05:15:49 PM UTC 24 Aug 23 05:15:53 PM UTC 24 2599363079 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.2493024770 Aug 23 05:15:51 PM UTC 24 Aug 23 05:15:54 PM UTC 24 2846167558 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.576823612 Aug 23 05:15:27 PM UTC 24 Aug 23 05:15:55 PM UTC 24 11935639503 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.4062127232 Aug 23 05:15:15 PM UTC 24 Aug 23 05:15:56 PM UTC 24 42102587785 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1479306155 Aug 23 05:15:49 PM UTC 24 Aug 23 05:15:56 PM UTC 24 3263613419 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1949898024 Aug 23 05:15:49 PM UTC 24 Aug 23 05:15:56 PM UTC 24 2613102296 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2751668875 Aug 23 05:15:43 PM UTC 24 Aug 23 05:15:56 PM UTC 24 4702841809 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.3879192500 Aug 23 05:15:54 PM UTC 24 Aug 23 05:15:57 PM UTC 24 2040610645 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1958419146 Aug 23 05:15:20 PM UTC 24 Aug 23 05:15:58 PM UTC 24 98528696848 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.4200505116 Aug 23 05:15:56 PM UTC 24 Aug 23 05:15:59 PM UTC 24 2467783127 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.4057087957 Aug 23 05:15:56 PM UTC 24 Aug 23 05:15:59 PM UTC 24 2532992809 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3081710934 Aug 23 05:15:52 PM UTC 24 Aug 23 05:16:02 PM UTC 24 12111574567 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.2023208485 Aug 23 05:15:55 PM UTC 24 Aug 23 05:16:02 PM UTC 24 2112017158 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.659625961 Aug 23 05:15:58 PM UTC 24 Aug 23 05:16:02 PM UTC 24 3594902768 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2498417202 Aug 23 05:15:27 PM UTC 24 Aug 23 05:16:02 PM UTC 24 1165993539652 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3317036365 Aug 23 05:15:56 PM UTC 24 Aug 23 05:16:03 PM UTC 24 2054136142 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4197356476 Aug 23 05:15:57 PM UTC 24 Aug 23 05:16:03 PM UTC 24 3622612954 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1355256245 Aug 23 05:15:59 PM UTC 24 Aug 23 05:16:04 PM UTC 24 4886369636 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2706620791 Aug 23 05:16:00 PM UTC 24 Aug 23 05:16:05 PM UTC 24 3679435059 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1488348031 Aug 23 05:15:21 PM UTC 24 Aug 23 05:16:06 PM UTC 24 37572470387 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1588691 Aug 23 05:16:04 PM UTC 24 Aug 23 05:16:06 PM UTC 24 2154289946 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2539779500 Aug 23 05:15:57 PM UTC 24 Aug 23 05:16:06 PM UTC 24 2612161923 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3889274800 Aug 23 05:16:03 PM UTC 24 Aug 23 05:16:06 PM UTC 24 9675166634 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2718899097 Aug 23 05:15:54 PM UTC 24 Aug 23 05:16:07 PM UTC 24 9252821713 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.4215225983 Aug 23 05:16:05 PM UTC 24 Aug 23 05:16:07 PM UTC 24 2238482970 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.996082209 Aug 23 05:16:04 PM UTC 24 Aug 23 05:16:09 PM UTC 24 2464557191 ps
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T218 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4113282872 Aug 23 05:16:06 PM UTC 24 Aug 23 05:16:09 PM UTC 24 2620739096 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.533411285 Aug 23 05:16:03 PM UTC 24 Aug 23 05:16:09 PM UTC 24 2012618371 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.720754880 Aug 23 05:15:44 PM UTC 24 Aug 23 05:16:10 PM UTC 24 22027500735 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2981932311 Aug 23 05:16:07 PM UTC 24 Aug 23 05:16:11 PM UTC 24 3403128844 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2018141914 Aug 23 05:16:08 PM UTC 24 Aug 23 05:16:11 PM UTC 24 2949647766 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2247574996 Aug 23 05:16:07 PM UTC 24 Aug 23 05:16:13 PM UTC 24 3446989419 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.1111712534 Aug 23 05:16:10 PM UTC 24 Aug 23 05:16:13 PM UTC 24 2134590012 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2228350620 Aug 23 05:16:06 PM UTC 24 Aug 23 05:16:13 PM UTC 24 2508819486 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.3396312738 Aug 23 05:16:10 PM UTC 24 Aug 23 05:16:14 PM UTC 24 2015378537 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2932478892 Aug 23 05:16:11 PM UTC 24 Aug 23 05:16:14 PM UTC 24 2476022353 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.906609286 Aug 23 05:16:03 PM UTC 24 Aug 23 05:16:17 PM UTC 24 4813999165 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2976437317 Aug 23 05:16:11 PM UTC 24 Aug 23 05:16:18 PM UTC 24 2208715246 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3393813167 Aug 23 05:16:03 PM UTC 24 Aug 23 05:16:21 PM UTC 24 27862870576 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2910384745 Aug 23 05:16:15 PM UTC 24 Aug 23 05:16:21 PM UTC 24 3718288391 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.64966426 Aug 23 05:16:14 PM UTC 24 Aug 23 05:16:21 PM UTC 24 2512685800 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1535020846 Aug 23 05:16:16 PM UTC 24 Aug 23 05:16:22 PM UTC 24 7972430551 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3082429811 Aug 23 05:16:15 PM UTC 24 Aug 23 05:16:22 PM UTC 24 2614719945 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3565376270 Aug 23 05:15:32 PM UTC 24 Aug 23 05:16:23 PM UTC 24 53541303125 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.2617878918 Aug 23 05:16:19 PM UTC 24 Aug 23 05:16:23 PM UTC 24 4538715542 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1533068038 Aug 23 05:16:10 PM UTC 24 Aug 23 05:16:24 PM UTC 24 10578533794 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.94577304 Aug 23 05:16:23 PM UTC 24 Aug 23 05:16:26 PM UTC 24 2124784267 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.961434898 Aug 23 05:16:22 PM UTC 24 Aug 23 05:16:26 PM UTC 24 2022947609 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.3434854075 Aug 23 05:16:24 PM UTC 24 Aug 23 05:16:26 PM UTC 24 2152135074 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3432672514 Aug 23 05:15:52 PM UTC 24 Aug 23 05:16:28 PM UTC 24 26588919021 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2851810649 Aug 23 05:16:23 PM UTC 24 Aug 23 05:16:29 PM UTC 24 2464501983 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.569705850 Aug 23 05:16:09 PM UTC 24 Aug 23 05:16:29 PM UTC 24 33513391724 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.2207622223 Aug 23 05:16:25 PM UTC 24 Aug 23 05:16:30 PM UTC 24 2515965525 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2631445828 Aug 23 05:16:26 PM UTC 24 Aug 23 05:16:31 PM UTC 24 2616770026 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2558503393 Aug 23 05:16:21 PM UTC 24 Aug 23 05:16:31 PM UTC 24 4691496639 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1489073652 Aug 23 05:16:26 PM UTC 24 Aug 23 05:16:32 PM UTC 24 3300119679 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3072655466 Aug 23 05:16:31 PM UTC 24 Aug 23 05:16:35 PM UTC 24 3896788621 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2803302653 Aug 23 05:16:28 PM UTC 24 Aug 23 05:16:36 PM UTC 24 8140014635 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3199395900 Aug 23 05:16:27 PM UTC 24 Aug 23 05:16:37 PM UTC 24 2948192145 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.3628489784 Aug 23 05:16:33 PM UTC 24 Aug 23 05:16:39 PM UTC 24 2013052097 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3250131584 Aug 23 05:15:20 PM UTC 24 Aug 23 05:16:41 PM UTC 24 59972357588 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.4129118955 Aug 23 05:16:36 PM UTC 24 Aug 23 05:16:42 PM UTC 24 2110777615 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1940633260 Aug 23 05:16:37 PM UTC 24 Aug 23 05:16:44 PM UTC 24 2197400410 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2320571539 Aug 23 05:16:32 PM UTC 24 Aug 23 05:16:44 PM UTC 24 4422205799 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.143194456 Aug 23 05:16:37 PM UTC 24 Aug 23 05:16:44 PM UTC 24 2482616015 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3595243299 Aug 23 05:16:21 PM UTC 24 Aug 23 05:16:45 PM UTC 24 43892657843 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.4253008421 Aug 23 05:15:50 PM UTC 24 Aug 23 05:16:46 PM UTC 24 91973220739 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.772227929 Aug 23 05:16:40 PM UTC 24 Aug 23 05:16:48 PM UTC 24 2511738515 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2123012837 Aug 23 05:16:10 PM UTC 24 Aug 23 05:16:48 PM UTC 24 70532692451 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3201486989 Aug 23 05:16:45 PM UTC 24 Aug 23 05:16:48 PM UTC 24 5834729287 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3110166153 Aug 23 05:16:41 PM UTC 24 Aug 23 05:16:48 PM UTC 24 2608493398 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2658255270 Aug 23 05:16:43 PM UTC 24 Aug 23 05:16:51 PM UTC 24 5233785256 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3368221434 Aug 23 05:16:48 PM UTC 24 Aug 23 05:16:51 PM UTC 24 2049102937 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.1944513987 Aug 23 05:16:22 PM UTC 24 Aug 23 05:16:53 PM UTC 24 12923303518 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2149613942 Aug 23 05:16:44 PM UTC 24 Aug 23 05:16:53 PM UTC 24 3351318083 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3028692570 Aug 23 05:16:46 PM UTC 24 Aug 23 05:16:53 PM UTC 24 3306897632 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.4058768815 Aug 23 05:16:52 PM UTC 24 Aug 23 05:16:54 PM UTC 24 2498472395 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1663029000 Aug 23 05:16:52 PM UTC 24 Aug 23 05:16:54 PM UTC 24 2089360715 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.132544663 Aug 23 05:16:50 PM UTC 24 Aug 23 05:16:56 PM UTC 24 2112432532 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2953344874 Aug 23 05:16:54 PM UTC 24 Aug 23 05:16:56 PM UTC 24 3832242276 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.786245189 Aug 23 05:15:13 PM UTC 24 Aug 23 05:16:56 PM UTC 24 44544406326 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1035140690 Aug 23 05:16:15 PM UTC 24 Aug 23 05:16:57 PM UTC 24 74134828695 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.474426464 Aug 23 05:16:55 PM UTC 24 Aug 23 05:16:57 PM UTC 24 5978514205 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1004903499 Aug 23 05:16:48 PM UTC 24 Aug 23 05:16:57 PM UTC 24 2932650171 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3735762912 Aug 23 05:16:54 PM UTC 24 Aug 23 05:16:58 PM UTC 24 2517890664 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3969856023 Aug 23 05:16:55 PM UTC 24 Aug 23 05:17:00 PM UTC 24 3503829340 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2534044500 Aug 23 05:16:58 PM UTC 24 Aug 23 05:17:01 PM UTC 24 2021552805 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.139516374 Aug 23 05:16:54 PM UTC 24 Aug 23 05:17:02 PM UTC 24 2610351016 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1984771683 Aug 23 05:16:59 PM UTC 24 Aug 23 05:17:03 PM UTC 24 2116203709 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.3210963323 Aug 23 05:17:01 PM UTC 24 Aug 23 05:17:05 PM UTC 24 2456185375 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3703751621 Aug 23 05:16:57 PM UTC 24 Aug 23 05:17:07 PM UTC 24 3684724833 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.3107180724 Aug 23 05:16:57 PM UTC 24 Aug 23 05:17:07 PM UTC 24 3906806448 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.3769857869 Aug 23 05:17:02 PM UTC 24 Aug 23 05:17:09 PM UTC 24 2039380608 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.4089931674 Aug 23 05:17:02 PM UTC 24 Aug 23 05:17:10 PM UTC 24 2508913184 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3339790202 Aug 23 05:17:03 PM UTC 24 Aug 23 05:17:12 PM UTC 24 2609140182 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3133346548 Aug 23 05:17:08 PM UTC 24 Aug 23 05:17:12 PM UTC 24 4978420566 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3425835322 Aug 23 05:16:30 PM UTC 24 Aug 23 05:17:12 PM UTC 24 63765627711 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.268299581 Aug 23 05:17:08 PM UTC 24 Aug 23 05:17:12 PM UTC 24 3423725245 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.794891343 Aug 23 05:17:13 PM UTC 24 Aug 23 05:17:16 PM UTC 24 2030593740 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1502226002 Aug 23 05:15:35 PM UTC 24 Aug 23 05:17:16 PM UTC 24 42010144378 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3563931927 Aug 23 05:17:11 PM UTC 24 Aug 23 05:17:16 PM UTC 24 3805626492 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2552987351 Aug 23 05:17:06 PM UTC 24 Aug 23 05:17:17 PM UTC 24 3819287577 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1025853755 Aug 23 05:16:46 PM UTC 24 Aug 23 05:17:18 PM UTC 24 42421785614 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1804983145 Aug 23 05:17:16 PM UTC 24 Aug 23 05:17:19 PM UTC 24 2130042446 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1578280286 Aug 23 05:17:17 PM UTC 24 Aug 23 05:17:19 PM UTC 24 2506496382 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.306060597 Aug 23 05:17:17 PM UTC 24 Aug 23 05:17:20 PM UTC 24 2046132146 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3801955196 Aug 23 05:17:18 PM UTC 24 Aug 23 05:17:21 PM UTC 24 2536700360 ps
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T473 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.393968273 Aug 23 05:17:19 PM UTC 24 Aug 23 05:17:25 PM UTC 24 2613355313 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3184135933 Aug 23 05:17:20 PM UTC 24 Aug 23 05:17:27 PM UTC 24 12926950040 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1547710264 Aug 23 05:17:13 PM UTC 24 Aug 23 05:17:27 PM UTC 24 20147284492 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2453781455 Aug 23 05:17:19 PM UTC 24 Aug 23 05:17:30 PM UTC 24 3789746867 ps
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T476 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.201643544 Aug 23 05:17:34 PM UTC 24 Aug 23 05:17:38 PM UTC 24 2131304190 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1076211143 Aug 23 05:17:32 PM UTC 24 Aug 23 05:17:38 PM UTC 24 2012680776 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.4163377428 Aug 23 05:17:29 PM UTC 24 Aug 23 05:17:41 PM UTC 24 4243912103 ps
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T367 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1860204423 Aug 23 05:17:42 PM UTC 24 Aug 23 05:17:44 PM UTC 24 2547631233 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.461937849 Aug 23 05:17:40 PM UTC 24 Aug 23 05:17:47 PM UTC 24 2095108180 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3957053557 Aug 23 05:17:44 PM UTC 24 Aug 23 05:17:47 PM UTC 24 2626343974 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.1112858041 Aug 23 05:17:40 PM UTC 24 Aug 23 05:17:48 PM UTC 24 2484469384 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.4103398789 Aug 23 05:17:47 PM UTC 24 Aug 23 05:17:51 PM UTC 24 4084904097 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3997157525 Aug 23 05:17:13 PM UTC 24 Aug 23 05:17:52 PM UTC 24 62978460412 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2936712738 Aug 23 05:17:49 PM UTC 24 Aug 23 05:17:53 PM UTC 24 5949271380 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1093208979 Aug 23 05:17:46 PM UTC 24 Aug 23 05:17:53 PM UTC 24 4371017819 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.4276437062 Aug 23 05:17:53 PM UTC 24 Aug 23 05:17:57 PM UTC 24 2021299722 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1381110097 Aug 23 05:17:21 PM UTC 24 Aug 23 05:17:58 PM UTC 24 139049057584 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2411517700 Aug 23 05:17:50 PM UTC 24 Aug 23 05:17:59 PM UTC 24 2694366921 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3659519508 Aug 23 05:16:57 PM UTC 24 Aug 23 05:18:01 PM UTC 24 78956963414 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2431646608 Aug 23 05:17:58 PM UTC 24 Aug 23 05:18:04 PM UTC 24 2111521284 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1794334353 Aug 23 05:18:00 PM UTC 24 Aug 23 05:18:04 PM UTC 24 2231899410 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.1140873499 Aug 23 05:18:02 PM UTC 24 Aug 23 05:18:05 PM UTC 24 2540407879 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.2216610023 Aug 23 05:17:59 PM UTC 24 Aug 23 05:18:05 PM UTC 24 2448575225 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.263019191 Aug 23 05:16:58 PM UTC 24 Aug 23 05:18:05 PM UTC 24 117270770576 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1242889921 Aug 23 05:18:06 PM UTC 24 Aug 23 05:18:10 PM UTC 24 3947905364 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.844011346 Aug 23 05:18:06 PM UTC 24 Aug 23 05:18:11 PM UTC 24 5971459676 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2362089547 Aug 23 05:18:05 PM UTC 24 Aug 23 05:18:13 PM UTC 24 2609500315 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1020453371 Aug 23 05:18:05 PM UTC 24 Aug 23 05:18:16 PM UTC 24 3933751277 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1667287602 Aug 23 05:18:11 PM UTC 24 Aug 23 05:18:18 PM UTC 24 2724509920 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.2715863677 Aug 23 05:18:19 PM UTC 24 Aug 23 05:18:23 PM UTC 24 2018931994 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1147847256 Aug 23 05:15:42 PM UTC 24 Aug 23 05:18:25 PM UTC 24 73345565675 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.24407352 Aug 23 05:18:13 PM UTC 24 Aug 23 05:18:26 PM UTC 24 20473936029 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.585931921 Aug 23 05:16:57 PM UTC 24 Aug 23 05:18:28 PM UTC 24 140497080077 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3148905070 Aug 23 05:17:53 PM UTC 24 Aug 23 05:18:28 PM UTC 24 14706483790 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3627480716 Aug 23 05:18:17 PM UTC 24 Aug 23 05:18:30 PM UTC 24 9250661358 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.2665837217 Aug 23 05:18:23 PM UTC 24 Aug 23 05:18:30 PM UTC 24 2109385552 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.184068179 Aug 23 05:18:27 PM UTC 24 Aug 23 05:18:30 PM UTC 24 2155993914 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2168238810 Aug 23 05:18:25 PM UTC 24 Aug 23 05:18:33 PM UTC 24 2461315774 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2386343279 Aug 23 05:18:29 PM UTC 24 Aug 23 05:18:33 PM UTC 24 2516228649 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.452948785 Aug 23 05:15:34 PM UTC 24 Aug 23 05:18:34 PM UTC 24 74987079081 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.699506153 Aug 23 05:18:32 PM UTC 24 Aug 23 05:18:36 PM UTC 24 3874090287 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.457771854 Aug 23 05:18:29 PM UTC 24 Aug 23 05:18:36 PM UTC 24 2612086400 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.594306664 Aug 23 05:18:31 PM UTC 24 Aug 23 05:18:36 PM UTC 24 3236137849 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3061860424 Aug 23 05:18:34 PM UTC 24 Aug 23 05:18:37 PM UTC 24 4459922502 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.3835479626 Aug 23 05:18:37 PM UTC 24 Aug 23 05:18:39 PM UTC 24 2064504707 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2029876909 Aug 23 05:18:38 PM UTC 24 Aug 23 05:18:45 PM UTC 24 2110545000 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3166566852 Aug 23 05:18:40 PM UTC 24 Aug 23 05:18:45 PM UTC 24 2467029809 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2407842697 Aug 23 05:18:37 PM UTC 24 Aug 23 05:18:46 PM UTC 24 15962971680 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.2157896477 Aug 23 05:18:45 PM UTC 24 Aug 23 05:18:48 PM UTC 24 2030166371 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.416821032 Aug 23 05:18:37 PM UTC 24 Aug 23 05:18:49 PM UTC 24 15772667915 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.2411435229 Aug 23 05:18:46 PM UTC 24 Aug 23 05:18:50 PM UTC 24 2523850295 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1035075605 Aug 23 05:18:35 PM UTC 24 Aug 23 05:18:51 PM UTC 24 28620020840 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1387630497 Aug 23 05:16:00 PM UTC 24 Aug 23 05:18:53 PM UTC 24 101739355746 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.612499461 Aug 23 05:18:46 PM UTC 24 Aug 23 05:18:54 PM UTC 24 2612355144 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.124150287 Aug 23 05:18:48 PM UTC 24 Aug 23 05:18:55 PM UTC 24 4535466467 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.2358636916 Aug 23 05:18:54 PM UTC 24 Aug 23 05:18:56 PM UTC 24 4029065789 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2816815688 Aug 23 05:18:49 PM UTC 24 Aug 23 05:18:58 PM UTC 24 3399069200 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.354969321 Aug 23 05:18:58 PM UTC 24 Aug 23 05:19:00 PM UTC 24 2045782472 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.85439795 Aug 23 05:18:59 PM UTC 24 Aug 23 05:19:03 PM UTC 24 2120256636 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2597648500 Aug 23 05:18:56 PM UTC 24 Aug 23 05:19:04 PM UTC 24 40831288072 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.578717107 Aug 23 05:19:01 PM UTC 24 Aug 23 05:19:06 PM UTC 24 2466091200 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1403972815 Aug 23 05:15:27 PM UTC 24 Aug 23 05:19:07 PM UTC 24 96114664609 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.171520625 Aug 23 05:19:05 PM UTC 24 Aug 23 05:19:08 PM UTC 24 2520065939 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.182084776 Aug 23 05:19:04 PM UTC 24 Aug 23 05:19:08 PM UTC 24 2227969410 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1146773517 Aug 23 05:18:56 PM UTC 24 Aug 23 05:19:09 PM UTC 24 9015487183 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.4099912709 Aug 23 05:19:07 PM UTC 24 Aug 23 05:19:11 PM UTC 24 3087950246 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_22/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2278179199 Aug 23 05:19:09 PM UTC 24 Aug 23 05:19:14 PM UTC 24 3821902477 ps
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