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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 28 68 70.83 28
Automatically Generated Cross Bins 96 28 68 70.83 28
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 36 1 T21 1 T50 2 T117 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 16 1 T46 1 T80 1 T82 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 47 1 T21 2 T65 1 T49 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 16 1 T82 1 T156 1 T308 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 52 1 T21 1 T65 1 T49 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 21 1 T82 1 T156 1 T308 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 45 1 T50 1 T47 1 T157 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 23 1 T156 2 T325 1 T322 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 40 1 T21 1 T65 1 T49 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 16 1 T46 1 T80 1 T322 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 41 1 T50 1 T47 1 T121 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 23 1 T46 1 T82 2 T322 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 68 1 T21 1 T49 3 T115 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 17 1 T80 1 T82 1 T156 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 49 1 T47 3 T121 2 T301 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 34 1 T308 2 T325 1 T322 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 48 1 T65 1 T49 2 T50 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 28 1 T46 2 T80 4 T82 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 52 1 T65 2 T49 1 T300 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 11 1 T80 1 T322 1 T312 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 48 1 T49 1 T50 1 T47 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 30 1 T46 1 T82 1 T156 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 45 1 T65 2 T47 1 T80 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 47 1 T46 1 T82 1 T156 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 40 1 T98 1 T65 2 T49 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 23 1 T156 2 T308 1 T322 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 47 1 T65 1 T47 1 T157 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 24 1 T46 2 T80 2 T325 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 68 1 T49 1 T50 3 T82 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 29 1 T46 2 T80 1 T115 7
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 93 1 T98 9 T157 5 T121 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 97 1 T157 3 T308 2 T322 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 46 1 T323 2 T309 1 T171 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 18 1 T46 1 T80 1 T325 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 34 1 T21 2 T46 1 T49 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 22 1 T46 2 T80 1 T82 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 51 1 T21 1 T65 1 T49 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 20 1 T46 2 T82 3 T156 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 34 1 T50 2 T48 1 T310 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 23 1 T46 1 T325 1 T322 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 36 1 T65 1 T50 1 T47 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 16 1 T156 1 T325 2 T124 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 57 1 T21 6 T115 1 T121 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 29 1 T156 1 T325 1 T312 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 43 1 T21 6 T47 1 T308 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 22 1 T82 1 T324 1 T125 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 47 1 T65 1 T49 2 T50 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 63 1 T325 1 T312 2 T324 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 56 1 T49 2 T50 1 T115 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 26 1 T156 1 T308 2 T325 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 30 1 T65 1 T49 1 T48 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 21 1 T80 1 T156 2 T157 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 40 1 T65 1 T121 1 T310 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 32 1 T46 1 T80 1 T308 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 116 1 T65 1 T100 10 T48 12
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 60 1 T46 1 T80 1 T156 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 47 1 T99 1 T47 1 T310 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 26 1 T82 1 T308 1 T325 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 51 1 T156 1 T121 1 T300 10
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 18 1 T312 1 T124 1 T389 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 58 1 T65 1 T99 9 T47 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 49 1 T80 3 T82 1 T115 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 148 1 T46 2 T65 2 T49 7
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 107 1 T46 2 T80 4 T82 6
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T397 1 - - - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 1 1 T402 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T397 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 2 1 T389 1 T404 1 - -


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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