Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_ac_present
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_bat_disable
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key0_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key1_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_key2_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_lid_open
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_in
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_pwrb_out
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
2 |
0 |
0.00 |
Automatically Generated Bins for cp_z3_wakeup
Uncovered bins
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0] - auto[1]] |
-- |
-- |
2 |
|
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_inXval
Uncovered bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key0_outXval
Uncovered bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_inXval
Uncovered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key1_outXval
Uncovered bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_inXval
Uncovered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for key2_outXval
Uncovered bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_inXval
Uncovered bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for pwrb_outXval
Uncovered bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for ac_presentXval
Uncovered bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Uncovered bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
4 |
0 |
0.00 |
4 |
Automatically Generated Cross Bins for lid_openXval
Uncovered bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | NUMBER | STATUS |
| * |
* |
-- |
-- |
4 |
|
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
2 |
0 |
0.00 |
2 |
| Automatically Generated Cross Bins |
2 |
2 |
0 |
0.00 |
2 |
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Uncovered bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[0]] |
0 |
1 |
1 |
|
| [auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
683 |
1 |
|
|
T5 |
7 |
|
T36 |
7 |
|
T37 |
11 |
| auto[1] |
637 |
1 |
|
|
T5 |
13 |
|
T36 |
13 |
|
T37 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
649 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
671 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
669 |
1 |
|
|
T5 |
12 |
|
T36 |
14 |
|
T37 |
11 |
| auto[1] |
651 |
1 |
|
|
T5 |
8 |
|
T36 |
6 |
|
T37 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
672 |
1 |
|
|
T5 |
7 |
|
T36 |
12 |
|
T37 |
12 |
| auto[1] |
648 |
1 |
|
|
T5 |
13 |
|
T36 |
8 |
|
T37 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
650 |
1 |
|
|
T5 |
9 |
|
T36 |
12 |
|
T37 |
10 |
| auto[1] |
670 |
1 |
|
|
T5 |
11 |
|
T36 |
8 |
|
T37 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
656 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
664 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
656 |
1 |
|
|
T5 |
12 |
|
T36 |
12 |
|
T37 |
13 |
| auto[1] |
664 |
1 |
|
|
T5 |
8 |
|
T36 |
8 |
|
T37 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
630 |
1 |
|
|
T5 |
13 |
|
T36 |
11 |
|
T37 |
13 |
| auto[1] |
690 |
1 |
|
|
T5 |
7 |
|
T36 |
9 |
|
T37 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
679 |
1 |
|
|
T5 |
8 |
|
T36 |
7 |
|
T37 |
13 |
| auto[1] |
641 |
1 |
|
|
T5 |
12 |
|
T36 |
13 |
|
T37 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
659 |
1 |
|
|
T5 |
11 |
|
T36 |
9 |
|
T37 |
9 |
| auto[1] |
661 |
1 |
|
|
T5 |
9 |
|
T36 |
11 |
|
T37 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
666 |
1 |
|
|
T5 |
8 |
|
T36 |
14 |
|
T37 |
11 |
| auto[1] |
654 |
1 |
|
|
T5 |
12 |
|
T36 |
6 |
|
T37 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
686 |
1 |
|
|
T5 |
12 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
634 |
1 |
|
|
T5 |
8 |
|
T36 |
10 |
|
T37 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
680 |
1 |
|
|
T5 |
17 |
|
T36 |
12 |
|
T37 |
14 |
| auto[1] |
640 |
1 |
|
|
T5 |
3 |
|
T36 |
8 |
|
T37 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
649 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
671 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
612 |
1 |
|
|
T5 |
5 |
|
T36 |
6 |
|
T37 |
10 |
| auto[1] |
708 |
1 |
|
|
T5 |
15 |
|
T36 |
14 |
|
T37 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
667 |
1 |
|
|
T5 |
12 |
|
T36 |
10 |
|
T37 |
9 |
| auto[1] |
653 |
1 |
|
|
T5 |
8 |
|
T36 |
10 |
|
T37 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
621 |
1 |
|
|
T5 |
11 |
|
T36 |
8 |
|
T37 |
13 |
| auto[1] |
699 |
1 |
|
|
T5 |
9 |
|
T36 |
12 |
|
T37 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
645 |
1 |
|
|
T5 |
6 |
|
T36 |
12 |
|
T37 |
14 |
| auto[1] |
675 |
1 |
|
|
T5 |
14 |
|
T36 |
8 |
|
T37 |
6 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
690 |
1 |
|
|
T5 |
13 |
|
T36 |
13 |
|
T37 |
5 |
| auto[1] |
630 |
1 |
|
|
T5 |
7 |
|
T36 |
7 |
|
T37 |
15 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
678 |
1 |
|
|
T5 |
8 |
|
T36 |
12 |
|
T37 |
9 |
| auto[1] |
642 |
1 |
|
|
T5 |
12 |
|
T36 |
8 |
|
T37 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
662 |
1 |
|
|
T5 |
9 |
|
T36 |
9 |
|
T37 |
10 |
| auto[1] |
658 |
1 |
|
|
T5 |
11 |
|
T36 |
11 |
|
T37 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
644 |
1 |
|
|
T5 |
10 |
|
T36 |
7 |
|
T37 |
14 |
| auto[1] |
676 |
1 |
|
|
T5 |
10 |
|
T36 |
13 |
|
T37 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
629 |
1 |
|
|
T5 |
7 |
|
T36 |
6 |
|
T37 |
12 |
| auto[1] |
691 |
1 |
|
|
T5 |
13 |
|
T36 |
14 |
|
T37 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
686 |
1 |
|
|
T5 |
12 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
634 |
1 |
|
|
T5 |
8 |
|
T36 |
10 |
|
T37 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
311 |
1 |
|
|
T5 |
2 |
|
T36 |
5 |
|
T37 |
4 |
| auto[0] |
auto[1] |
301 |
1 |
|
|
T5 |
3 |
|
T36 |
1 |
|
T37 |
6 |
| auto[1] |
auto[0] |
358 |
1 |
|
|
T5 |
10 |
|
T36 |
9 |
|
T37 |
7 |
| auto[1] |
auto[1] |
350 |
1 |
|
|
T5 |
5 |
|
T36 |
5 |
|
T37 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
340 |
1 |
|
|
T5 |
3 |
|
T36 |
6 |
|
T37 |
4 |
| auto[0] |
auto[1] |
327 |
1 |
|
|
T5 |
9 |
|
T36 |
4 |
|
T37 |
5 |
| auto[1] |
auto[0] |
332 |
1 |
|
|
T5 |
4 |
|
T36 |
6 |
|
T37 |
8 |
| auto[1] |
auto[1] |
321 |
1 |
|
|
T5 |
4 |
|
T36 |
4 |
|
T37 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
303 |
1 |
|
|
T5 |
5 |
|
T36 |
6 |
|
T37 |
8 |
| auto[0] |
auto[1] |
318 |
1 |
|
|
T5 |
6 |
|
T36 |
2 |
|
T37 |
5 |
| auto[1] |
auto[0] |
347 |
1 |
|
|
T5 |
4 |
|
T36 |
6 |
|
T37 |
2 |
| auto[1] |
auto[1] |
352 |
1 |
|
|
T5 |
5 |
|
T36 |
6 |
|
T37 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
318 |
1 |
|
|
T5 |
3 |
|
T36 |
7 |
|
T37 |
9 |
| auto[0] |
auto[1] |
327 |
1 |
|
|
T5 |
3 |
|
T36 |
5 |
|
T37 |
5 |
| auto[1] |
auto[0] |
338 |
1 |
|
|
T5 |
7 |
|
T36 |
3 |
|
T37 |
2 |
| auto[1] |
auto[1] |
337 |
1 |
|
|
T5 |
7 |
|
T36 |
5 |
|
T37 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
340 |
1 |
|
|
T5 |
7 |
|
T36 |
9 |
|
T37 |
3 |
| auto[0] |
auto[1] |
350 |
1 |
|
|
T5 |
6 |
|
T36 |
4 |
|
T37 |
2 |
| auto[1] |
auto[0] |
316 |
1 |
|
|
T5 |
5 |
|
T36 |
3 |
|
T37 |
10 |
| auto[1] |
auto[1] |
314 |
1 |
|
|
T5 |
2 |
|
T36 |
4 |
|
T37 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
321 |
1 |
|
|
T5 |
5 |
|
T36 |
8 |
|
T37 |
5 |
| auto[0] |
auto[1] |
357 |
1 |
|
|
T5 |
3 |
|
T36 |
4 |
|
T37 |
4 |
| auto[1] |
auto[0] |
309 |
1 |
|
|
T5 |
8 |
|
T36 |
3 |
|
T37 |
8 |
| auto[1] |
auto[1] |
333 |
1 |
|
|
T5 |
4 |
|
T36 |
5 |
|
T37 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
319 |
1 |
|
|
T5 |
6 |
|
T36 |
2 |
|
T37 |
8 |
| auto[0] |
auto[1] |
325 |
1 |
|
|
T5 |
4 |
|
T36 |
5 |
|
T37 |
6 |
| auto[1] |
auto[0] |
340 |
1 |
|
|
T5 |
5 |
|
T36 |
7 |
|
T37 |
1 |
| auto[1] |
auto[1] |
336 |
1 |
|
|
T5 |
5 |
|
T36 |
6 |
|
T37 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
315 |
1 |
|
|
T5 |
3 |
|
T36 |
4 |
|
T37 |
8 |
| auto[0] |
auto[1] |
314 |
1 |
|
|
T5 |
4 |
|
T36 |
2 |
|
T37 |
4 |
| auto[1] |
auto[0] |
351 |
1 |
|
|
T5 |
5 |
|
T36 |
10 |
|
T37 |
3 |
| auto[1] |
auto[1] |
340 |
1 |
|
|
T5 |
8 |
|
T36 |
4 |
|
T37 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
347 |
1 |
|
|
T5 |
5 |
|
T36 |
5 |
|
T37 |
9 |
| auto[0] |
auto[1] |
333 |
1 |
|
|
T5 |
12 |
|
T36 |
7 |
|
T37 |
5 |
| auto[1] |
auto[0] |
336 |
1 |
|
|
T5 |
2 |
|
T36 |
2 |
|
T37 |
2 |
| auto[1] |
auto[1] |
304 |
1 |
|
|
T5 |
1 |
|
T36 |
6 |
|
T37 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
649 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
auto[1] |
671 |
1 |
|
|
T5 |
10 |
|
T36 |
10 |
|
T37 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
335 |
1 |
|
|
T5 |
4 |
|
T36 |
4 |
|
T37 |
7 |
| auto[0] |
auto[1] |
327 |
1 |
|
|
T5 |
5 |
|
T36 |
5 |
|
T37 |
3 |
| auto[1] |
auto[0] |
344 |
1 |
|
|
T5 |
4 |
|
T36 |
3 |
|
T37 |
6 |
| auto[1] |
auto[1] |
314 |
1 |
|
|
T5 |
7 |
|
T36 |
8 |
|
T37 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
686 |
1 |
|
|
T5 |
12 |
|
T36 |
10 |
|
T37 |
11 |
| auto[1] |
auto[1] |
634 |
1 |
|
|
T5 |
8 |
|
T36 |
10 |
|
T37 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T114 |
11 |
| auto[1] |
9 |
1 |
|
|
T114 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T114 |
9 |
| auto[1] |
11 |
1 |
|
|
T114 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T114 |
12 |
| auto[1] |
8 |
1 |
|
|
T114 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T114 |
9 |
| auto[1] |
11 |
1 |
|
|
T114 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T114 |
10 |
| auto[1] |
10 |
1 |
|
|
T114 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T114 |
8 |
| auto[1] |
12 |
1 |
|
|
T114 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T114 |
10 |
| auto[1] |
10 |
1 |
|
|
T114 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T114 |
14 |
| auto[1] |
6 |
1 |
|
|
T114 |
6 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T114 |
11 |
| auto[1] |
9 |
1 |
|
|
T114 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T114 |
11 |
| auto[1] |
9 |
1 |
|
|
T114 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T114 |
9 |
| auto[1] |
11 |
1 |
|
|
T114 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T114 |
10 |
| auto[1] |
10 |
1 |
|
|
T114 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T114 |
8 |
| auto[1] |
12 |
1 |
|
|
T114 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T114 |
9 |
| auto[1] |
11 |
1 |
|
|
T114 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T114 |
13 |
| auto[1] |
7 |
1 |
|
|
T114 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T114 |
8 |
| auto[1] |
12 |
1 |
|
|
T114 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T114 |
11 |
| auto[1] |
9 |
1 |
|
|
T114 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T114 |
9 |
| auto[1] |
11 |
1 |
|
|
T114 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T114 |
10 |
| auto[1] |
10 |
1 |
|
|
T114 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T114 |
12 |
| auto[1] |
8 |
1 |
|
|
T114 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T114 |
12 |
| auto[1] |
8 |
1 |
|
|
T114 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T114 |
12 |
| auto[1] |
8 |
1 |
|
|
T114 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T114 |
8 |
| auto[1] |
12 |
1 |
|
|
T114 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T114 |
10 |
| auto[1] |
10 |
1 |
|
|
T114 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T114 |
8 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T114 |
5 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T114 |
4 |
| auto[1] |
auto[1] |
3 |
1 |
|
|
T114 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
4 |
1 |
|
|
T114 |
4 |
| auto[0] |
auto[1] |
4 |
1 |
|
|
T114 |
4 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T114 |
5 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T114 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T114 |
5 |
| auto[0] |
auto[1] |
6 |
1 |
|
|
T114 |
6 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T114 |
5 |
| auto[1] |
auto[1] |
4 |
1 |
|
|
T114 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
3 |
1 |
|
|
T114 |
3 |
| auto[0] |
auto[1] |
6 |
1 |
|
|
T114 |
6 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T114 |
5 |
| auto[1] |
auto[1] |
6 |
1 |
|
|
T114 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
6 |
1 |
|
|
T114 |
6 |
| auto[0] |
auto[1] |
4 |
1 |
|
|
T114 |
4 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T114 |
4 |
| auto[1] |
auto[1] |
6 |
1 |
|
|
T114 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
9 |
1 |
|
|
T114 |
9 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T114 |
3 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T114 |
5 |
| auto[1] |
auto[1] |
3 |
1 |
|
|
T114 |
3 |