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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 29 67 69.79 29
Automatically Generated Cross Bins 96 29 67 69.79 29
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * [auto[0]] * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] * [auto[1]] [auto[1]] [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 60 1 T31 4 T37 1 T40 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 28 1 T39 2 T41 1 T98 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 42 1 T40 1 T105 1 T86 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 13 1 T41 3 T184 1 T273 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 49 1 T31 1 T43 1 T299 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 18 1 T98 2 T184 1 T107 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 42 1 T38 2 T42 2 T43 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 17 1 T41 1 T184 1 T280 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 50 1 T31 3 T40 1 T42 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 23 1 T98 1 T184 1 T107 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 59 1 T31 4 T37 1 T38 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 35 1 T31 4 T41 1 T98 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 48 1 T44 2 T105 2 T106 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 24 1 T39 1 T41 2 T347 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 55 1 T40 1 T38 1 T42 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 22 1 T39 2 T41 2 T107 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 39 1 T40 1 T42 1 T43 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 25 1 T107 1 T347 2 T349 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 36 1 T98 1 T119 1 T270 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 17 1 T184 1 T107 1 T349 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 37 1 T43 1 T44 2 T119 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 27 1 T107 1 T347 1 T349 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 55 1 T39 1 T40 1 T84 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 28 1 T39 1 T98 2 T184 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 37 1 T37 1 T43 1 T44 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 21 1 T39 1 T98 1 T350 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 33 1 T40 2 T85 1 T105 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 45 1 T41 2 T85 6 T107 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 66 1 T40 1 T41 1 T43 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 36 1 T107 2 T347 1 T349 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 90 1 T44 2 T86 7 T106 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 79 1 T39 2 T107 1 T280 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 37 1 T84 1 T85 1 T119 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T37 2 T41 1 T98 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 50 1 T40 1 T42 1 T85 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 22 1 T39 1 T184 1 T107 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 36 1 T40 1 T38 1 T43 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 24 1 T39 2 T98 1 T347 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 46 1 T38 1 T44 2 T299 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 25 1 T98 1 T184 1 T346 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 35 1 T83 1 T42 1 T43 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 19 1 T39 1 T184 1 T107 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 40 1 T40 1 T43 2 T44 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 29 1 T263 1 T107 1 T349 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 49 1 T40 1 T43 1 T44 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 43 1 T39 3 T41 4 T38 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 78 1 T83 9 T38 2 T42 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 72 1 T37 7 T38 8 T184 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 29 1 T42 2 T43 1 T44 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 16 1 T39 1 T98 2 T184 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 36 1 T42 3 T43 1 T119 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 18 1 T39 1 T98 1 T184 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 34 1 T40 2 T85 1 T43 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 37 1 T85 1 T184 1 T347 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 65 1 T84 1 T42 4 T43 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 54 1 T84 9 T85 1 T184 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 49 1 T40 1 T42 1 T43 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 46 1 T37 1 T41 2 T184 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 32 1 T40 1 T44 2 T354 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 77 1 T39 1 T98 1 T263 8
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 25 1 T40 2 T105 1 T86 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 57 1 T184 1 T280 1 T288 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 104 1 T39 3 T40 11 T42 10
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 117 1 T39 2 T41 6 T98 9
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 1 1 T368 1 - - - -
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 2 1 T373 2 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 25 1 T280 1 T346 2 T273 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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