Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 98.75 96.73 100.00 95.51 98.23 99.33 93.13


Total tests in report: 913
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
43.35 43.35 61.93 61.93 43.73 43.73 79.57 79.57 1.28 1.28 64.70 64.70 50.77 50.77 1.50 1.50 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2664273771
72.26 28.91 88.62 26.68 77.58 33.85 85.73 6.16 73.08 71.79 88.69 23.99 87.09 36.32 5.06 3.56 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.921216753
77.22 4.95 90.26 1.64 81.40 3.82 90.75 5.02 73.08 0.00 90.24 1.55 91.14 4.05 23.66 18.60 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.187949334
81.10 3.88 95.76 5.50 87.69 6.29 95.66 4.91 73.08 0.00 95.64 5.40 92.87 1.73 26.97 3.31 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3334963021
83.32 2.22 96.17 0.41 88.68 0.99 96.23 0.57 73.08 0.00 95.97 0.33 93.06 0.19 40.01 13.05 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.411520566
85.27 1.96 97.03 0.86 89.76 1.09 96.46 0.23 79.49 6.41 96.64 0.67 95.57 2.50 41.95 1.94 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.727063956
86.58 1.31 97.05 0.02 90.85 1.09 97.15 0.68 79.49 0.00 96.67 0.04 95.57 0.00 49.31 7.37 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.616688944
87.61 1.03 97.24 0.19 91.23 0.38 97.15 0.00 79.49 0.00 96.71 0.04 95.66 0.10 55.81 6.49 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3534528436
88.44 0.83 97.24 0.00 91.23 0.00 97.15 0.00 79.49 0.00 96.71 0.00 95.66 0.00 61.61 5.81 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.923159914
89.21 0.77 97.31 0.07 91.35 0.13 97.15 0.00 79.49 0.00 96.71 0.00 95.86 0.19 66.60 4.99 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.90237301
89.87 0.66 97.39 0.07 91.66 0.30 97.15 0.00 81.41 1.92 96.82 0.11 96.24 0.39 68.41 1.81 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.579392046
90.45 0.58 97.59 0.21 92.06 0.40 97.15 0.00 81.41 0.00 96.89 0.07 96.34 0.10 71.72 3.31 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2709541395
90.99 0.54 97.65 0.06 92.14 0.08 97.15 0.00 81.41 0.00 96.89 0.00 96.34 0.00 75.34 3.62 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3263462046
91.48 0.49 97.70 0.06 93.43 1.29 97.15 0.00 81.41 0.00 96.89 0.00 96.53 0.19 77.22 1.87 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.414056566
91.96 0.48 97.80 0.09 93.55 0.13 97.60 0.46 83.33 1.92 97.01 0.11 97.01 0.48 77.40 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1356926958
92.31 0.35 97.95 0.15 93.63 0.08 97.60 0.00 83.33 0.00 97.01 0.00 97.01 0.00 79.65 2.25 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1048444776
92.66 0.35 97.98 0.04 93.93 0.30 97.83 0.23 84.62 1.28 97.08 0.07 97.50 0.48 79.71 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2562097485
93.00 0.34 98.08 0.09 93.98 0.05 97.83 0.00 86.54 1.92 97.19 0.11 97.69 0.19 79.71 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.764189983
93.30 0.30 98.08 0.00 94.01 0.03 99.43 1.60 86.54 0.00 97.19 0.00 97.78 0.10 80.09 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.18331359
93.59 0.29 98.08 0.00 94.01 0.00 99.43 0.00 86.54 0.00 97.19 0.00 97.78 0.00 82.08 2.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.168680442
93.86 0.27 98.08 0.00 94.82 0.81 99.43 0.00 86.54 0.00 97.19 0.00 97.98 0.19 82.96 0.87 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1362371711
94.07 0.22 98.13 0.06 94.84 0.03 99.43 0.00 87.82 1.28 97.26 0.07 98.07 0.10 82.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.229021589
94.29 0.22 98.19 0.06 94.87 0.03 99.43 0.00 89.10 1.28 97.34 0.07 98.17 0.10 82.96 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.481376932
94.50 0.21 98.25 0.06 95.42 0.56 99.66 0.23 89.10 0.00 97.45 0.11 98.17 0.00 83.46 0.50 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.563972239
94.70 0.20 98.28 0.04 95.42 0.00 99.66 0.00 90.38 1.28 97.52 0.07 98.17 0.00 83.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1748179824
94.86 0.16 98.34 0.06 95.63 0.20 99.66 0.00 90.38 0.00 97.60 0.07 98.94 0.77 83.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3019960994
95.01 0.15 98.34 0.00 95.63 0.00 99.66 0.00 90.38 0.00 97.63 0.04 98.94 0.00 84.46 1.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2425045046
95.15 0.15 98.40 0.06 95.65 0.03 99.66 0.00 91.03 0.64 97.71 0.07 99.04 0.10 84.58 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.492972985
95.29 0.14 98.40 0.00 95.78 0.13 99.66 0.00 91.03 0.00 97.71 0.00 99.04 0.00 85.46 0.87 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.3374803290
95.44 0.14 98.40 0.00 95.78 0.00 99.66 0.00 91.03 0.00 97.71 0.00 99.04 0.00 86.45 1.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3514226415
95.57 0.14 98.40 0.00 95.80 0.03 99.66 0.00 91.03 0.00 97.71 0.00 99.04 0.00 87.39 0.94 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.3993917553
95.70 0.13 98.45 0.06 95.83 0.03 99.66 0.00 91.67 0.64 97.78 0.07 99.13 0.10 87.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2643405493
95.82 0.12 98.49 0.04 95.85 0.03 99.66 0.00 92.31 0.64 97.82 0.04 99.23 0.10 87.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.910404725
95.94 0.12 98.53 0.04 95.88 0.03 99.66 0.00 92.95 0.64 97.86 0.04 99.33 0.10 87.39 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.214300428
96.06 0.12 98.53 0.00 95.90 0.03 99.66 0.00 92.95 0.00 97.86 0.00 99.33 0.00 88.20 0.81 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2447427952
96.16 0.10 98.54 0.02 95.90 0.00 99.66 0.00 93.59 0.64 97.89 0.04 99.33 0.00 88.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.4020260314
96.26 0.10 98.56 0.02 95.90 0.00 99.66 0.00 94.23 0.64 97.93 0.04 99.33 0.00 88.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1425562106
96.36 0.10 98.58 0.02 95.90 0.00 99.66 0.00 94.87 0.64 97.97 0.04 99.33 0.00 88.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.8539213
96.45 0.09 98.58 0.00 95.90 0.00 99.66 0.00 95.51 0.64 97.97 0.00 99.33 0.00 88.20 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1818233315
96.54 0.09 98.58 0.00 95.90 0.00 99.66 0.00 95.51 0.00 97.97 0.00 99.33 0.00 88.83 0.62 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1053734319
96.61 0.08 98.58 0.00 96.06 0.15 99.77 0.11 95.51 0.00 98.04 0.07 99.33 0.00 89.01 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3121430254
96.69 0.07 98.58 0.00 96.06 0.00 99.77 0.00 95.51 0.00 98.04 0.00 99.33 0.00 89.51 0.50 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.460108676
96.75 0.06 98.64 0.06 96.13 0.08 100.00 0.23 95.51 0.00 98.04 0.00 99.33 0.00 89.58 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.752217690
96.80 0.05 98.64 0.00 96.13 0.00 100.00 0.00 95.51 0.00 98.04 0.00 99.33 0.00 89.95 0.37 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.123149025
96.85 0.05 98.69 0.06 96.18 0.05 100.00 0.00 95.51 0.00 98.08 0.04 99.33 0.00 90.14 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.615838127
96.89 0.04 98.73 0.04 96.36 0.18 100.00 0.00 95.51 0.00 98.15 0.07 99.33 0.00 90.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3030960806
96.92 0.04 98.73 0.00 96.36 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 90.39 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3686799382
96.96 0.04 98.73 0.00 96.36 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 90.64 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3491780034
96.99 0.03 98.73 0.00 96.59 0.23 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 90.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.957916734
97.02 0.03 98.73 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 90.82 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3782290935
97.05 0.03 98.73 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 91.01 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.777102419
97.07 0.03 98.73 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 91.20 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1372872875
97.10 0.03 98.73 0.00 96.59 0.00 100.00 0.00 95.51 0.00 98.15 0.00 99.33 0.00 91.39 0.19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.95881166
97.12 0.03 98.75 0.02 96.59 0.00 100.00 0.00 95.51 0.00 98.19 0.04 99.33 0.00 91.51 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.562099404
97.15 0.02 98.75 0.00 96.64 0.05 100.00 0.00 95.51 0.00 98.23 0.04 99.33 0.00 91.57 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1502731699
97.16 0.02 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 91.70 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1818458064
97.18 0.02 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 91.82 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3117424484
97.20 0.02 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 91.95 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2364670295
97.22 0.02 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.07 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3003071109
97.24 0.02 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.20 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1683410776
97.24 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.26 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.35518179
97.25 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.32 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1137866360
97.26 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.38 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.78650786
97.27 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.45 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.459194176
97.28 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.51 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.727008798
97.29 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.57 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1312763432
97.30 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.63 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3447201135
97.31 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.70 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2611380370
97.32 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.76 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3277515652
97.32 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.82 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2243041016
97.33 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.88 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1211053834
97.34 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 92.95 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1258041627
97.35 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 93.01 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2673579026
97.36 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 93.07 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2773297723
97.37 0.01 98.75 0.00 96.64 0.00 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 93.13 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.964637385
97.38 0.01 98.75 0.00 96.69 0.05 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 93.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.102632805
97.38 0.01 98.75 0.00 96.71 0.03 100.00 0.00 95.51 0.00 98.23 0.00 99.33 0.00 93.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4091472791

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2782805926
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3878964385
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1405962423
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4247206967
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3319703175
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1229231084
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2289785631
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3770713014
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2728043762
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3518028836
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3377545273
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4153809340
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4242388108
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3033478320
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.137152294
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3794786099
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1157296557
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2804734130
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2347728113
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1028335382
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2780215865
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1094465399
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.399841185
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1835196877
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2014042421
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1143145797
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.841800481
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.95851282
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.587474052
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2001697326
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3801580594
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3548317399
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.967328347
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2575780157
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2261281800
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.919046887
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.41986641
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.498943463
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3379810147
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2289389239
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1813655698
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.513403812
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1337940401
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.943694697
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1354653738
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.603598590
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.123340066
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.938145636
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2752748736
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2959782007
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3290979021
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4041286325
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1718131932
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.922874645
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1188886643
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2658163
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.255294017
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2071824180
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3490671348
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1945222620
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1695222610
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2505435352
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.386640111
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2159499320
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2751839220
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3230708275
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1461180297
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1179595050
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1485677326
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1165569812
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.606263590
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3534838164
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1588748095
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.126409964
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523607281
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2655963968
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Total test records in report: 913
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3306491372 Aug 25 06:29:41 AM UTC 24 Aug 25 06:29:46 AM UTC 24 2482276037 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2456471524 Aug 25 06:29:40 AM UTC 24 Aug 25 06:29:47 AM UTC 24 2114813075 ps
T1 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3420924253 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:48 AM UTC 24 2613875752 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.521909104 Aug 25 06:29:46 AM UTC 24 Aug 25 06:29:49 AM UTC 24 2500528010 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2060150205 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:50 AM UTC 24 2030852594 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2461769886 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:50 AM UTC 24 11123376859 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.774925844 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:50 AM UTC 24 3261448594 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.4102077810 Aug 25 06:29:47 AM UTC 24 Aug 25 06:29:50 AM UTC 24 2047111910 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3121430254 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:52 AM UTC 24 2621349983 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2664273771 Aug 25 06:29:46 AM UTC 24 Aug 25 06:29:53 AM UTC 24 2230584728 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2676496097 Aug 25 06:29:48 AM UTC 24 Aug 25 06:29:53 AM UTC 24 2630953469 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.480526581 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:53 AM UTC 24 2120900873 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3334963021 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:54 AM UTC 24 2515282952 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2562097485 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:55 AM UTC 24 4067943234 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.3651792412 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:56 AM UTC 24 2135223147 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1232980399 Aug 25 06:29:50 AM UTC 24 Aug 25 06:29:57 AM UTC 24 4269923069 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3888738760 Aug 25 06:30:37 AM UTC 24 Aug 25 06:30:42 AM UTC 24 4246685153 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2921533361 Aug 25 06:29:45 AM UTC 24 Aug 25 06:29:57 AM UTC 24 2399095315 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3974215775 Aug 25 06:29:55 AM UTC 24 Aug 25 06:29:58 AM UTC 24 2174293600 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1325124731 Aug 25 06:29:52 AM UTC 24 Aug 25 06:30:00 AM UTC 24 2741073317 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2972532680 Aug 25 06:29:56 AM UTC 24 Aug 25 06:30:01 AM UTC 24 2479523309 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1689320410 Aug 25 06:29:57 AM UTC 24 Aug 25 06:30:02 AM UTC 24 2346325083 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.1033741096 Aug 25 06:29:55 AM UTC 24 Aug 25 06:30:02 AM UTC 24 2020844846 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.921719333 Aug 25 06:29:45 AM UTC 24 Aug 25 06:30:02 AM UTC 24 3105408130 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3137747015 Aug 25 06:29:59 AM UTC 24 Aug 25 06:30:03 AM UTC 24 2048382267 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.563972239 Aug 25 06:29:51 AM UTC 24 Aug 25 06:30:03 AM UTC 24 10155567232 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1137866360 Aug 25 06:29:48 AM UTC 24 Aug 25 06:30:04 AM UTC 24 2510173598 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1079761907 Aug 25 06:29:47 AM UTC 24 Aug 25 06:30:04 AM UTC 24 2506179266 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2502073941 Aug 25 06:29:59 AM UTC 24 Aug 25 06:30:06 AM UTC 24 2615413702 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3578230669 Aug 25 06:30:03 AM UTC 24 Aug 25 06:30:07 AM UTC 24 438298108558 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.921216753 Aug 25 06:29:53 AM UTC 24 Aug 25 06:30:07 AM UTC 24 37025362924 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3597325243 Aug 25 06:30:03 AM UTC 24 Aug 25 06:30:08 AM UTC 24 3289034318 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.414056566 Aug 25 06:30:02 AM UTC 24 Aug 25 06:30:10 AM UTC 24 3170604539 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.629648082 Aug 25 06:29:51 AM UTC 24 Aug 25 06:30:11 AM UTC 24 3905840577 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3586559582 Aug 25 06:29:57 AM UTC 24 Aug 25 06:30:11 AM UTC 24 2438482082 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3463069040 Aug 25 06:29:59 AM UTC 24 Aug 25 06:30:12 AM UTC 24 2509901662 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.4242056854 Aug 25 06:30:08 AM UTC 24 Aug 25 06:30:13 AM UTC 24 2484519284 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.562099404 Aug 25 06:29:54 AM UTC 24 Aug 25 06:30:14 AM UTC 24 19671647554 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1931730842 Aug 25 06:29:45 AM UTC 24 Aug 25 06:30:15 AM UTC 24 9336678077 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.325849251 Aug 25 06:30:08 AM UTC 24 Aug 25 06:30:15 AM UTC 24 2217953567 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.752217690 Aug 25 06:30:05 AM UTC 24 Aug 25 06:30:15 AM UTC 24 2013524586 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3046343432 Aug 25 06:30:14 AM UTC 24 Aug 25 06:30:17 AM UTC 24 3015392925 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2470932857 Aug 25 06:30:12 AM UTC 24 Aug 25 06:30:17 AM UTC 24 2640318486 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2646136870 Aug 25 06:30:07 AM UTC 24 Aug 25 06:30:19 AM UTC 24 2109334564 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4005490865 Aug 25 06:30:04 AM UTC 24 Aug 25 06:30:20 AM UTC 24 6281798480 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3111237918 Aug 25 06:30:09 AM UTC 24 Aug 25 06:30:22 AM UTC 24 2359272704 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.214726763 Aug 25 06:30:11 AM UTC 24 Aug 25 06:30:22 AM UTC 24 2091702666 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.555557915 Aug 25 06:30:14 AM UTC 24 Aug 25 06:30:23 AM UTC 24 3392188304 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.168981085 Aug 25 06:30:02 AM UTC 24 Aug 25 06:30:24 AM UTC 24 3861633408 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1888737842 Aug 25 06:30:21 AM UTC 24 Aug 25 06:30:26 AM UTC 24 2027965810 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2856814124 Aug 25 06:30:23 AM UTC 24 Aug 25 06:30:26 AM UTC 24 2572006230 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3009618337 Aug 25 06:30:16 AM UTC 24 Aug 25 06:30:26 AM UTC 24 3703620755 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2906362534 Aug 25 06:30:15 AM UTC 24 Aug 25 06:30:26 AM UTC 24 7595911480 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3491780034 Aug 25 06:30:12 AM UTC 24 Aug 25 06:30:26 AM UTC 24 2510523908 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1039410552 Aug 25 06:30:23 AM UTC 24 Aug 25 06:30:27 AM UTC 24 2194179644 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4195835613 Aug 25 06:30:24 AM UTC 24 Aug 25 06:30:28 AM UTC 24 2342111304 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1031169 Aug 25 06:30:18 AM UTC 24 Aug 25 06:30:28 AM UTC 24 7547560026 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2153622043 Aug 25 06:30:21 AM UTC 24 Aug 25 06:30:31 AM UTC 24 2109384818 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.948896478 Aug 25 06:30:05 AM UTC 24 Aug 25 06:30:31 AM UTC 24 11217992440 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1813150549 Aug 25 06:30:26 AM UTC 24 Aug 25 06:30:32 AM UTC 24 2621286274 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4183231324 Aug 25 06:30:28 AM UTC 24 Aug 25 06:30:32 AM UTC 24 9126019899 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1458192422 Aug 25 06:30:29 AM UTC 24 Aug 25 06:30:33 AM UTC 24 3245550946 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.3517296066 Aug 25 06:30:26 AM UTC 24 Aug 25 06:30:33 AM UTC 24 2523482388 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2274557534 Aug 25 06:30:28 AM UTC 24 Aug 25 06:30:34 AM UTC 24 3241636659 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.18331359 Aug 25 06:29:45 AM UTC 24 Aug 25 06:30:34 AM UTC 24 42126127899 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2959451543 Aug 25 06:30:32 AM UTC 24 Aug 25 06:30:35 AM UTC 24 2093588702 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.615838127 Aug 25 06:29:45 AM UTC 24 Aug 25 06:30:36 AM UTC 24 39009427158 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.187949334 Aug 25 06:30:18 AM UTC 24 Aug 25 06:30:36 AM UTC 24 15102611095 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1053086031 Aug 25 06:30:33 AM UTC 24 Aug 25 06:30:36 AM UTC 24 2181719189 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.4069523600 Aug 25 06:30:25 AM UTC 24 Aug 25 06:30:37 AM UTC 24 2147511722 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1180498797 Aug 25 06:30:35 AM UTC 24 Aug 25 06:30:39 AM UTC 24 2526429622 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.562387937 Aug 25 06:30:37 AM UTC 24 Aug 25 06:30:41 AM UTC 24 2979621181 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3555663217 Aug 25 06:30:36 AM UTC 24 Aug 25 06:30:42 AM UTC 24 2632217981 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3432855060 Aug 25 06:30:35 AM UTC 24 Aug 25 06:30:44 AM UTC 24 2464351900 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.1933612168 Aug 25 06:30:35 AM UTC 24 Aug 25 06:30:45 AM UTC 24 2122935790 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2640632111 Aug 25 06:30:36 AM UTC 24 Aug 25 06:30:45 AM UTC 24 2604079244 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1428805804 Aug 25 06:30:28 AM UTC 24 Aug 25 06:30:45 AM UTC 24 3402891282 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4246594125 Aug 25 06:30:46 AM UTC 24 Aug 25 06:30:52 AM UTC 24 2132464123 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1006037952 Aug 25 06:30:37 AM UTC 24 Aug 25 06:30:53 AM UTC 24 3654608514 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3821076320 Aug 25 06:30:46 AM UTC 24 Aug 25 06:30:54 AM UTC 24 2523016131 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3158298425 Aug 25 06:30:29 AM UTC 24 Aug 25 06:30:55 AM UTC 24 5906731450 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.579392046 Aug 25 06:30:43 AM UTC 24 Aug 25 06:30:56 AM UTC 24 7919863177 ps
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T196 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.2028941224 Aug 25 06:30:43 AM UTC 24 Aug 25 06:30:57 AM UTC 24 2012393099 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.1808273165 Aug 25 06:30:05 AM UTC 24 Aug 25 06:30:58 AM UTC 24 42105553528 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.4156579121 Aug 25 06:30:46 AM UTC 24 Aug 25 06:30:58 AM UTC 24 2456031717 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1502263196 Aug 25 06:30:55 AM UTC 24 Aug 25 06:30:59 AM UTC 24 3453013757 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4147419687 Aug 25 06:30:53 AM UTC 24 Aug 25 06:31:00 AM UTC 24 2616313202 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.897770402 Aug 25 06:30:55 AM UTC 24 Aug 25 06:31:01 AM UTC 24 3771500829 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.923159914 Aug 25 06:30:32 AM UTC 24 Aug 25 06:31:01 AM UTC 24 13879932718 ps
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T194 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1474531127 Aug 25 06:30:57 AM UTC 24 Aug 25 06:31:05 AM UTC 24 3529058773 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.274194527 Aug 25 06:31:04 AM UTC 24 Aug 25 06:31:07 AM UTC 24 2743794050 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3044492747 Aug 25 06:31:04 AM UTC 24 Aug 25 06:31:09 AM UTC 24 2535320531 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2705070401 Aug 25 06:31:01 AM UTC 24 Aug 25 06:31:09 AM UTC 24 2120063673 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.704802261 Aug 25 06:31:06 AM UTC 24 Aug 25 06:31:10 AM UTC 24 2832628190 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3318522175 Aug 25 06:30:59 AM UTC 24 Aug 25 06:31:11 AM UTC 24 6705020966 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.3014521061 Aug 25 06:31:03 AM UTC 24 Aug 25 06:31:11 AM UTC 24 2457684238 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2813736082 Aug 25 06:30:58 AM UTC 24 Aug 25 06:31:12 AM UTC 24 3759264259 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3733138289 Aug 25 06:30:59 AM UTC 24 Aug 25 06:31:12 AM UTC 24 2015265200 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.1662782153 Aug 25 06:31:03 AM UTC 24 Aug 25 06:31:13 AM UTC 24 2080322160 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3665456699 Aug 25 06:31:07 AM UTC 24 Aug 25 06:31:15 AM UTC 24 2962800752 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.271315005 Aug 25 06:31:13 AM UTC 24 Aug 25 06:31:17 AM UTC 24 2139193111 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.3544859430 Aug 25 06:31:13 AM UTC 24 Aug 25 06:31:18 AM UTC 24 2034156075 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.156320873 Aug 25 06:31:14 AM UTC 24 Aug 25 06:31:19 AM UTC 24 2489561789 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2529870721 Aug 25 06:31:19 AM UTC 24 Aug 25 06:31:23 AM UTC 24 2643398919 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3383812027 Aug 25 06:31:07 AM UTC 24 Aug 25 06:31:24 AM UTC 24 3339485896 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1489739267 Aug 25 06:31:15 AM UTC 24 Aug 25 06:31:26 AM UTC 24 2121176498 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.142656576 Aug 25 06:31:10 AM UTC 24 Aug 25 06:31:26 AM UTC 24 3565819238 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1274928889 Aug 25 06:31:24 AM UTC 24 Aug 25 06:31:26 AM UTC 24 3588805919 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3694773201 Aug 25 06:31:20 AM UTC 24 Aug 25 06:31:28 AM UTC 24 4359783036 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.2310834990 Aug 25 06:31:26 AM UTC 24 Aug 25 06:31:29 AM UTC 24 3152489975 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1183451413 Aug 25 06:31:18 AM UTC 24 Aug 25 06:31:33 AM UTC 24 2510123312 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.404335603 Aug 25 06:31:30 AM UTC 24 Aug 25 06:31:35 AM UTC 24 2027811080 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3335367498 Aug 25 06:31:12 AM UTC 24 Aug 25 06:31:36 AM UTC 24 4584448028 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.4116908694 Aug 25 06:31:33 AM UTC 24 Aug 25 06:31:38 AM UTC 24 2468582059 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1048444776 Aug 25 06:30:58 AM UTC 24 Aug 25 06:31:38 AM UTC 24 44801947307 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.865150998 Aug 25 06:31:35 AM UTC 24 Aug 25 06:31:40 AM UTC 24 2090522313 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.2387786135 Aug 25 06:31:36 AM UTC 24 Aug 25 06:31:40 AM UTC 24 2565746440 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.3033638452 Aug 25 06:31:32 AM UTC 24 Aug 25 06:31:40 AM UTC 24 2118269426 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2287394509 Aug 25 06:31:39 AM UTC 24 Aug 25 06:31:47 AM UTC 24 2616817945 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3335694792 Aug 25 06:31:28 AM UTC 24 Aug 25 06:31:47 AM UTC 24 3897877647 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2709541395 Aug 25 06:30:28 AM UTC 24 Aug 25 06:31:48 AM UTC 24 71285001034 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.492972985 Aug 25 06:31:41 AM UTC 24 Aug 25 06:31:48 AM UTC 24 6348657954 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.949017411 Aug 25 06:31:41 AM UTC 24 Aug 25 06:31:49 AM UTC 24 3931325507 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.411520566 Aug 25 06:29:45 AM UTC 24 Aug 25 06:31:50 AM UTC 24 59735757926 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.4001222635 Aug 25 06:31:39 AM UTC 24 Aug 25 06:31:52 AM UTC 24 3892620494 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.707245592 Aug 25 06:31:49 AM UTC 24 Aug 25 06:31:53 AM UTC 24 2124739879 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.226329032 Aug 25 06:31:51 AM UTC 24 Aug 25 06:31:55 AM UTC 24 2504028815 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.3333744216 Aug 25 06:31:51 AM UTC 24 Aug 25 06:31:55 AM UTC 24 2055625998 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1536206456 Aug 25 06:29:52 AM UTC 24 Aug 25 06:31:59 AM UTC 24 65972452376 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2425045046 Aug 25 06:31:48 AM UTC 24 Aug 25 06:31:59 AM UTC 24 18310926750 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1701818595 Aug 25 06:31:48 AM UTC 24 Aug 25 06:32:00 AM UTC 24 2016580169 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3669570918 Aug 25 06:31:53 AM UTC 24 Aug 25 06:32:02 AM UTC 24 2517663192 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3100325631 Aug 25 06:31:56 AM UTC 24 Aug 25 06:32:03 AM UTC 24 3916858299 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4176724816 Aug 25 06:30:57 AM UTC 24 Aug 25 06:32:08 AM UTC 24 144179016221 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1867941199 Aug 25 06:32:01 AM UTC 24 Aug 25 06:32:09 AM UTC 24 3946598846 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3266662667 Aug 25 06:31:55 AM UTC 24 Aug 25 06:32:09 AM UTC 24 3572053547 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2639473539 Aug 25 06:31:54 AM UTC 24 Aug 25 06:32:10 AM UTC 24 2609236560 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.55485327 Aug 25 06:31:59 AM UTC 24 Aug 25 06:32:11 AM UTC 24 4124758133 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.135973436 Aug 25 06:32:03 AM UTC 24 Aug 25 06:32:12 AM UTC 24 5637506163 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.1283249008 Aug 25 06:32:09 AM UTC 24 Aug 25 06:32:13 AM UTC 24 2041793681 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2387196789 Aug 25 06:32:04 AM UTC 24 Aug 25 06:32:14 AM UTC 24 9673816723 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2808949488 Aug 25 06:32:12 AM UTC 24 Aug 25 06:32:17 AM UTC 24 2529227962 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.760797618 Aug 25 06:32:14 AM UTC 24 Aug 25 06:32:18 AM UTC 24 3035176478 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4293148703 Aug 25 06:32:13 AM UTC 24 Aug 25 06:32:21 AM UTC 24 2614385088 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2565884197 Aug 25 06:32:10 AM UTC 24 Aug 25 06:32:21 AM UTC 24 2109150014 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.1224656769 Aug 25 06:32:10 AM UTC 24 Aug 25 06:32:21 AM UTC 24 2455131787 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3664302186 Aug 25 06:32:15 AM UTC 24 Aug 25 06:32:23 AM UTC 24 3888257738 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.630625118 Aug 25 06:32:12 AM UTC 24 Aug 25 06:32:23 AM UTC 24 2102900082 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2354820007 Aug 25 06:32:24 AM UTC 24 Aug 25 06:32:27 AM UTC 24 2530588783 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2964570957 Aug 25 06:32:24 AM UTC 24 Aug 25 06:32:28 AM UTC 24 2033266656 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.3083217456 Aug 25 06:32:21 AM UTC 24 Aug 25 06:32:29 AM UTC 24 3505852381 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.3601093162 Aug 25 06:32:24 AM UTC 24 Aug 25 06:32:30 AM UTC 24 2114219237 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3129225769 Aug 25 06:32:17 AM UTC 24 Aug 25 06:32:31 AM UTC 24 13998479694 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.1167046762 Aug 25 06:32:23 AM UTC 24 Aug 25 06:32:33 AM UTC 24 6452047895 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.1205991388 Aug 25 06:32:29 AM UTC 24 Aug 25 06:32:33 AM UTC 24 2585483583 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.123149025 Aug 25 06:30:37 AM UTC 24 Aug 25 06:32:33 AM UTC 24 93813204117 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2342312751 Aug 25 06:32:30 AM UTC 24 Aug 25 06:32:33 AM UTC 24 2664000540 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.621223357 Aug 25 06:32:33 AM UTC 24 Aug 25 06:32:38 AM UTC 24 11544728419 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1588176813 Aug 25 06:32:34 AM UTC 24 Aug 25 06:32:39 AM UTC 24 4542657250 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.10799059 Aug 25 06:32:28 AM UTC 24 Aug 25 06:32:41 AM UTC 24 2209451321 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3277662048 Aug 25 06:32:23 AM UTC 24 Aug 25 06:32:41 AM UTC 24 3512108695 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.953588618 Aug 25 06:32:41 AM UTC 24 Aug 25 06:32:46 AM UTC 24 2125674126 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.3324495238 Aug 25 06:32:42 AM UTC 24 Aug 25 06:32:48 AM UTC 24 2490593055 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1198236035 Aug 25 06:32:32 AM UTC 24 Aug 25 06:32:48 AM UTC 24 2982658552 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1533683927 Aug 25 06:32:39 AM UTC 24 Aug 25 06:32:50 AM UTC 24 2014560178 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1502731699 Aug 25 06:32:32 AM UTC 24 Aug 25 06:32:52 AM UTC 24 3527524084 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1009659484 Aug 25 06:32:35 AM UTC 24 Aug 25 06:32:52 AM UTC 24 2937575966 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.244058236 Aug 25 06:29:54 AM UTC 24 Aug 25 06:32:55 AM UTC 24 419282032434 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.540748797 Aug 25 06:32:01 AM UTC 24 Aug 25 06:32:56 AM UTC 24 41915508089 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2614180421 Aug 25 06:32:53 AM UTC 24 Aug 25 06:32:56 AM UTC 24 5470667513 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.115060338 Aug 25 06:32:47 AM UTC 24 Aug 25 06:32:58 AM UTC 24 2130885946 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1003375746 Aug 25 06:32:51 AM UTC 24 Aug 25 06:32:59 AM UTC 24 4572170050 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3482260859 Aug 25 06:32:49 AM UTC 24 Aug 25 06:33:01 AM UTC 24 2511438596 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2752601242 Aug 25 06:32:49 AM UTC 24 Aug 25 06:33:02 AM UTC 24 2607459188 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1748179824 Aug 25 06:32:56 AM UTC 24 Aug 25 06:33:07 AM UTC 24 5033599973 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.315387742 Aug 25 06:33:02 AM UTC 24 Aug 25 06:33:09 AM UTC 24 2118760586 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.2639700439 Aug 25 06:33:05 AM UTC 24 Aug 25 06:33:09 AM UTC 24 2097944643 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.4169439801 Aug 25 06:29:55 AM UTC 24 Aug 25 06:33:11 AM UTC 24 42007872910 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.112239533 Aug 25 06:33:01 AM UTC 24 Aug 25 06:33:11 AM UTC 24 2010289753 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1685070020 Aug 25 06:33:08 AM UTC 24 Aug 25 06:33:13 AM UTC 24 2640652695 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2644059826 Aug 25 06:32:58 AM UTC 24 Aug 25 06:33:14 AM UTC 24 11207970991 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3117424484 Aug 25 06:30:16 AM UTC 24 Aug 25 06:33:15 AM UTC 24 70186860220 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.4081989660 Aug 25 06:33:03 AM UTC 24 Aug 25 06:33:16 AM UTC 24 2465007778 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.600565195 Aug 25 06:29:52 AM UTC 24 Aug 25 06:33:17 AM UTC 24 175958869959 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.756719082 Aug 25 06:32:34 AM UTC 24 Aug 25 06:33:17 AM UTC 24 41676707040 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2844254749 Aug 25 06:29:45 AM UTC 24 Aug 25 06:33:20 AM UTC 24 94819447121 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.1283687321 Aug 25 06:33:17 AM UTC 24 Aug 25 06:33:22 AM UTC 24 8029373146 ps
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T414 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.791914622 Aug 25 06:33:08 AM UTC 24 Aug 25 06:33:22 AM UTC 24 2513867765 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3542739635 Aug 25 06:33:10 AM UTC 24 Aug 25 06:33:25 AM UTC 24 3314729163 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3583581661 Aug 25 06:33:21 AM UTC 24 Aug 25 06:33:26 AM UTC 24 2063233568 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.631699082 Aug 25 06:33:23 AM UTC 24 Aug 25 06:33:27 AM UTC 24 2639633258 ps
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T457 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2274865328 Aug 25 06:33:24 AM UTC 24 Aug 25 06:33:29 AM UTC 24 2729378191 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.3827667443 Aug 25 06:33:18 AM UTC 24 Aug 25 06:33:29 AM UTC 24 2010604683 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1054686384 Aug 25 06:33:20 AM UTC 24 Aug 25 06:33:30 AM UTC 24 2456646051 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.4028053704 Aug 25 06:31:25 AM UTC 24 Aug 25 06:33:30 AM UTC 24 52753005651 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.90237301 Aug 25 06:32:39 AM UTC 24 Aug 25 06:33:31 AM UTC 24 67071514683 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1123009025 Aug 25 06:33:27 AM UTC 24 Aug 25 06:33:31 AM UTC 24 2596819685 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2923213826 Aug 25 06:33:24 AM UTC 24 Aug 25 06:33:31 AM UTC 24 3631820560 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1794665046 Aug 25 06:30:19 AM UTC 24 Aug 25 06:33:32 AM UTC 24 42012317266 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.690690108 Aug 25 06:33:30 AM UTC 24 Aug 25 06:33:32 AM UTC 24 2141792494 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1643120071 Aug 25 06:33:25 AM UTC 24 Aug 25 06:33:33 AM UTC 24 5262069259 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3116232466 Aug 25 06:33:31 AM UTC 24 Aug 25 06:33:34 AM UTC 24 2188043543 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.4188575752 Aug 25 06:33:30 AM UTC 24 Aug 25 06:33:35 AM UTC 24 2134927419 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2527396555 Aug 25 06:33:23 AM UTC 24 Aug 25 06:33:36 AM UTC 24 2509323794 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1629711045 Aug 25 06:33:33 AM UTC 24 Aug 25 06:33:37 AM UTC 24 3766905309 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1818233315 Aug 25 06:33:29 AM UTC 24 Aug 25 06:33:37 AM UTC 24 69079533374 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.707115774 Aug 25 06:33:34 AM UTC 24 Aug 25 06:33:39 AM UTC 24 5112341907 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.137987080 Aug 25 06:33:16 AM UTC 24 Aug 25 06:33:39 AM UTC 24 4630963194 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.3374803290 Aug 25 06:31:12 AM UTC 24 Aug 25 06:33:40 AM UTC 24 164895059524 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.762393593 Aug 25 06:33:39 AM UTC 24 Aug 25 06:33:43 AM UTC 24 2036947662 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.1350139503 Aug 25 06:33:31 AM UTC 24 Aug 25 06:33:44 AM UTC 24 2459313330 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2853951309 Aug 25 06:33:40 AM UTC 24 Aug 25 06:33:45 AM UTC 24 2122142038 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.991861673 Aug 25 06:33:32 AM UTC 24 Aug 25 06:33:45 AM UTC 24 2510851779 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.2591011131 Aug 25 06:30:32 AM UTC 24 Aug 25 06:33:45 AM UTC 24 42009521175 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2192599614 Aug 25 06:33:33 AM UTC 24 Aug 25 06:33:45 AM UTC 24 2610149457 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3910247900 Aug 25 06:33:41 AM UTC 24 Aug 25 06:33:45 AM UTC 24 2082615866 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.658297375 Aug 25 06:33:41 AM UTC 24 Aug 25 06:33:45 AM UTC 24 2471032335 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2758174245 Aug 25 06:33:00 AM UTC 24 Aug 25 06:33:49 AM UTC 24 9323210796 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3049848550 Aug 25 06:33:34 AM UTC 24 Aug 25 06:33:51 AM UTC 24 3250292176 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1133060434 Aug 25 06:33:35 AM UTC 24 Aug 25 06:33:51 AM UTC 24 4245478307 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.3549669732 Aug 25 06:33:47 AM UTC 24 Aug 25 06:33:51 AM UTC 24 4680324423 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.1190462514 Aug 25 06:33:30 AM UTC 24 Aug 25 06:33:54 AM UTC 24 11683314003 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3088426239 Aug 25 06:33:45 AM UTC 24 Aug 25 06:33:54 AM UTC 24 2620207415 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3912370948 Aug 25 06:33:44 AM UTC 24 Aug 25 06:33:57 AM UTC 24 2508856594 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.186346565 Aug 25 06:33:52 AM UTC 24 Aug 25 06:33:58 AM UTC 24 10085146723 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.360718251 Aug 25 06:33:54 AM UTC 24 Aug 25 06:33:59 AM UTC 24 2506640533 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.873452052 Aug 25 06:33:55 AM UTC 24 Aug 25 06:33:59 AM UTC 24 2112126258 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3010483149 Aug 25 06:33:47 AM UTC 24 Aug 25 06:34:02 AM UTC 24 5967949288 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.1682183765 Aug 25 06:33:52 AM UTC 24 Aug 25 06:34:02 AM UTC 24 2010337047 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.803500210 Aug 25 06:35:01 AM UTC 24 Aug 25 06:35:07 AM UTC 24 3024763652 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2052393260 Aug 25 06:33:52 AM UTC 24 Aug 25 06:34:03 AM UTC 24 2111950499 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3944882623 Aug 25 06:33:36 AM UTC 24 Aug 25 06:34:03 AM UTC 24 6658124940 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1039278365 Aug 25 06:33:58 AM UTC 24 Aug 25 06:34:05 AM UTC 24 2513520982 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2158115404 Aug 25 06:34:00 AM UTC 24 Aug 25 06:34:05 AM UTC 24 3368726280 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1433752462 Aug 25 06:33:47 AM UTC 24 Aug 25 06:34:08 AM UTC 24 3400222986 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.822616822 Aug 25 06:34:00 AM UTC 24 Aug 25 06:34:11 AM UTC 24 4014071169 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2015086223 Aug 25 06:33:45 AM UTC 24 Aug 25 06:34:12 AM UTC 24 5211168264 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.58451864 Aug 25 06:34:09 AM UTC 24 Aug 25 06:34:13 AM UTC 24 2136922758 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.189666764 Aug 25 06:32:19 AM UTC 24 Aug 25 06:34:13 AM UTC 24 26366077739 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3568469882 Aug 25 06:33:59 AM UTC 24 Aug 25 06:34:13 AM UTC 24 2614526548 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.457742622 Aug 25 06:34:06 AM UTC 24 Aug 25 06:34:16 AM UTC 24 2014539485 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2837589805 Aug 25 06:34:14 AM UTC 24 Aug 25 06:34:17 AM UTC 24 2727699858 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3449930889 Aug 25 06:34:13 AM UTC 24 Aug 25 06:34:17 AM UTC 24 2159748747 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1735331868 Aug 25 06:34:04 AM UTC 24 Aug 25 06:34:19 AM UTC 24 2831063602 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1079143125 Aug 25 06:34:04 AM UTC 24 Aug 25 06:34:22 AM UTC 24 7346766735 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.537692177 Aug 25 06:34:14 AM UTC 24 Aug 25 06:34:23 AM UTC 24 2512740840 ps
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