Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
381 |
1 |
|
|
T71 |
7 |
|
T72 |
7 |
|
T167 |
4 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
210 |
1 |
|
|
T71 |
7 |
|
T72 |
5 |
|
T139 |
5 |
auto[1] |
171 |
1 |
|
|
T72 |
2 |
|
T167 |
4 |
|
T139 |
2 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
151 |
1 |
|
|
T71 |
1 |
|
T72 |
1 |
|
T167 |
3 |
auto[1] |
230 |
1 |
|
|
T71 |
6 |
|
T72 |
6 |
|
T167 |
1 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
| | | | | | | | | | | | |
auto[0] |
224 |
1 |
|
|
T71 |
3 |
|
T72 |
3 |
|
T167 |
3 |
auto[1] |
157 |
1 |
|
|
T71 |
4 |
|
T72 |
4 |
|
T167 |
1 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
| | | | | |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
| | | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
81 |
1 |
|
|
T71 |
1 |
|
T72 |
1 |
|
T139 |
3 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
41 |
1 |
|
|
T71 |
2 |
|
T72 |
1 |
|
T392 |
2 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
70 |
1 |
|
|
T167 |
3 |
|
T139 |
2 |
|
T107 |
3 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
32 |
1 |
|
|
T72 |
1 |
|
T107 |
1 |
|
T260 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
88 |
1 |
|
|
T71 |
4 |
|
T72 |
3 |
|
T139 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
69 |
1 |
|
|
T72 |
1 |
|
T167 |
1 |
|
T107 |
2 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |