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 LINE       6608
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T18,T11,T28
1	1	Covered	T19,T77,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T18,T19,T66
1	1	Covered	T28,T88,T310

 LINE       6608
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T15,T18,T19
1	1	Covered	T19,T26,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T26,T29
1	1	Covered	T15,T26,T77

 LINE       6608
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T15,T18,T11
1	1	Covered	T26,T77,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T11,T51,T88
1	1	Covered	T15,T16,T18

 LINE       6608
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T11,T28,T51
1	1	Covered	T15,T77,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T18,T19
1	1	Covered	T19,T29,T81

 LINE       6608
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T18,T11,T28
1	1	Covered	T77,T28,T51

 LINE       6608
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T26,T11,T28
1	1	Covered	T18,T19,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T77,T11,T28
1	1	Covered	T19,T77,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T18,T7
1	1	Covered	T26,T28,T51

 LINE       6608
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T11,T28,T51
1	1	Covered	T16,T26,T10

 LINE       6608
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T26,T11,T51
1	1	Covered	T19,T26,T29

 LINE       6608
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T11,T28,T51
1	1	Covered	T26,T28,T51

 LINE       6608
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T18,T19
1	1	Covered	T77,T28,T51

 LINE       6608
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T15,T18,T19
1	1	Covered	T26,T29,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T19,T10,T11
1	1	Covered	T81,T77,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T15,T19,T10
1	1	Covered	T19,T24,T28

 LINE       6608
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T18,T19
1	1	Covered	T7,T29,T10

 LINE       6608
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T6,T8
1	1	Covered	T15,T19,T3

 LINE       6655
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T17,T20
1	1	0	Covered	T301,T303,T311
1	1	1	Covered	T1,T17,T20

 LINE       6658
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T24,T26,T28
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T71,T72,T167

 LINE       6661
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T14,T15,T26
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T14,T81,T206

 LINE       6664
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T19,T10,T28
1	1	0	Covered	T303,T312,T313
1	1	1	Covered	T32,T33,T34

 LINE       6667
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T15,T16
1	1	0	Covered	T301,T314,T315
1	1	1	Covered	T1,T18,T24

 LINE       6669
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T2,T19,T26
1	1	0	Covered	T301,T302,T311
1	1	1	Covered	T2,T9,T25

 LINE       6671
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T2,T19,T26
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T2,T9,T25

 LINE       6673
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T2,T19,T26
1	1	0	Covered	T301,T302,T312
1	1	1	Covered	T2,T9,T25

 LINE       6675
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T2,T26,T9
1	1	0	Covered	T312,T315,T316
1	1	1	Covered	T2,T9,T11

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T2,T19,T9
1	1	0	Covered	T301,T303,T317
1	1	1	Covered	T2,T9,T36

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T14,T2,T19
1	1	0	Covered	T312,T313,T311
1	1	1	Covered	T2,T9,T11

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T4,T13,T26
1	1	0	Covered	T301,T303,T312
1	1	1	Covered	T4,T13,T26

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T4,T13,T15
1	1	0	Covered	T301,T302,T311
1	1	1	Covered	T4,T13,T17

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T4,T1,T13
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T4,T1,T13

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T17,T18,T19
1	1	0	Covered	T318,T301,T303
1	1	1	Covered	T17,T19,T27

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T3,T6,T8
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T3,T6,T8

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T15,T18
1	1	0	Covered	T301,T302,T312
1	1	1	Covered	T1,T18,T3

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T26,T29
1	1	0	Covered	T301,T319,T303
1	1	1	Covered	T15,T11,T28

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T19,T77
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T15,T11,T28

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T24,T29
1	1	0	Covered	T301,T303,T312
1	1	1	Covered	T1,T29,T10

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T18,T19,T77
1	1	0	Covered	T314,T315,T316
1	1	1	Covered	T11,T30,T31

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T18,T19,T66
1	1	0	Covered	T301,T312,T311
1	1	1	Covered	T11,T30,T31

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T18,T19
1	1	0	Covered	T301,T304,T303
1	1	1	Covered	T11,T30,T31

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T15,T80
1	1	0	Covered	T304,T303,T312
1	1	1	Covered	T1,T29,T10

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T18,T26
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T11,T30,T31

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T301,T303,T312
1	1	1	Covered	T11,T30,T31

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T77,T11
1	1	0	Covered	T302,T303,T312
1	1	1	Covered	T11,T30,T31

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T18,T19
1	1	0	Covered	T301,T303,T312
1	1	1	Covered	T1,T18,T7

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T18,T77,T11
1	1	0	Covered	T303,T313,T311
1	1	1	Covered	T11,T30,T31

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T18,T19,T26
1	1	0	Covered	T303,T312,T313
1	1	1	Covered	T11,T30,T31

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T19,T77,T11
1	1	0	Covered	T303,T311,T314
1	1	1	Covered	T11,T30,T31

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T18,T7
1	1	0	Covered	T301,T303,T312
1	1	1	Covered	T1,T18,T7

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T14,T16,T26
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T11,T30,T31

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T19,T26,T29
1	1	0	Covered	T301,T302,T303
1	1	1	Covered	T11,T30,T31

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T26,T66,T11
1	1	0	Covered	T307,T301,T303
1	1	1	Covered	T11,T30,T31

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T18,T19
1	1	0	Covered	T301,T303,T312
1	1	1	Covered	T1,T18,T7

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T18,T19
1	1	0	Covered	T303,T313,T314
1	1	1	Covered	T11,T30,T31

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T19,T81,T10
1	1	0	Covered	T51,T301,T302
1	1	1	Covered	T11,T30,T31

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T19,T24
1	1	0	Covered	T303,T311,T315
1	1	1	Covered	T11,T30,T31

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T1,T18,T19
1	1	0	Covered	T303,T313,T311
1	1	1	Covered	T1,T7,T10

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T1,T13
1	0	1	Covered	T15,T19,T3
1	1	0	Covered	T301,T303,T313
1	1	1	Covered	T3,T6,T8

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T1,T13