SYSRST_CTRL Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	13.130s	2.114ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	14.460s	2.453ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	12.940s	2.438ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	15.680s	2.506ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	22.470s	4.014ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	12.650s	2.031ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	3.645m	75.433ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	12.130s	2.946ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	12.340s	2.045ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	12.650s	2.031ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.130s	2.946ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	13.946m	175.927ms	49	50	98.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	12.487m	169.925ms	90	100	90.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	12.269m	177.466ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	15.487m	1.420s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	14.330s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	12.200s	2.144ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.872m	1.066s	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	14.660s	2.609ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	10.961m	1.417s	45	50	90.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	49.010s	39.009ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	22.326m	394.269ms	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	12.740s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	12.470s	2.016ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	14.680s	2.050ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	14.680s	2.050ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	22.470s	4.014ms	5	5	100.00
		sysrst_ctrl_csr_rw	12.650s	2.031ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.130s	2.946ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	48.400s	7.862ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	22.470s	4.014ms	5	5	100.00
		sysrst_ctrl_csr_rw	12.650s	2.031ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	12.130s	2.946ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	48.400s	7.862ms	20	20	100.00
V2		TOTAL			674	692	97.40
V2S	tl_intg_err	sysrst_ctrl_sec_cm	3.215m	42.008ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	2.784m	42.356ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	2.784m	42.356ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	48.690s	2.365s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			913	932	97.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	98.75	96.73	100.00	95.51	98.23	99.33	93.13

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 7 failures:

Test sysrst_ctrl_stress_all has 2 failures.

0.sysrst_ctrl_stress_all.104795344272521740031436082408688494916607660804588158089195207679630924688156
Line 372, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4184201408 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4316701408 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 5566701408 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 5603210571 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_flash_wr_prot_vseq
  UVM_INFO @ 7602639656 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:23) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Starting the body from flash_wr_prot_vseq

9.sysrst_ctrl_stress_all.47159295116208945926749521188652128062808232281956299173161079410115812600987
Line 376, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 10611288342 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 10613788342 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
  UVM_INFO @ 12128788342 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 12133509379 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_pin_override_vseq
  UVM_INFO @ 14128807413 ps: (sysrst_ctrl_pin_override_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Starting the body from pin_override_vseq

Test sysrst_ctrl_ultra_low_pwr has 5 failures.

8.sysrst_ctrl_ultra_low_pwr.14596771245416163391488935942686542016147558577130778451042425872090328546465
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2609643167 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4462143167 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4462143167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sysrst_ctrl_ultra_low_pwr.54449748743619659968938237112403963441980367492527124800608305492031127878774
Line 372, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 6901122358 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 7018622358 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 8168622358 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 8179265840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 5 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 5 failures.

11.sysrst_ctrl_combo_detect_with_pre_cond.47732663349781639269450119540710370535811561573593664580606326833644005395646
Line 499, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 104175967137 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 104175967137 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 104175967137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.sysrst_ctrl_combo_detect_with_pre_cond.39864573983928662882269618693200228046097850104845016548536768854243045100226
Line 394, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 40255645984 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 40255645984 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 40255645984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

70.sysrst_ctrl_combo_detect_with_pre_cond.19699255290128398474217210368147507743251641889321620716879874362845768320116
Line 422, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 63921148532 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 63921148532 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 63921148532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

78.sysrst_ctrl_combo_detect_with_pre_cond.115359564814342731469206749986707792546171513943199141495122772415494058904071
Line 382, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14004732618 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 14004732618 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 14004732618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_pin_override_vseq.sv:25) [sysrst_ctrl_pin_override_vseq] Check failed out_val == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

17.sysrst_ctrl_stress_all_with_rand_reset.30565858997517909063616446236756128848571645271007299465719101304051111529163
Line 404, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8351264664 ps: (sysrst_ctrl_pin_override_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_override_vseq] Check failed out_val == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8355576985 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 4/5
  UVM_INFO @ 8357939560 ps: (dv_base_reg.sv:332) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 8367481303 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/5

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

34.sysrst_ctrl_combo_detect_with_pre_cond.44860175346092864382830177751148269470198288753247076405920512772134807751894
Line 394, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14788247822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
  UVM_INFO @ 14813247822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :1
  UVM_INFO @ 14813247822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :2
  UVM_INFO @ 14958247822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 14978247822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:239) [sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect has 1 failures.

40.sysrst_ctrl_combo_detect.76610145508252397112715687855695729475169022128774836062211271414987949146976
Line 374, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest/run.log

  UVM_ERROR @ 12451359816 ps: (sysrst_ctrl_combo_detect_vseq.sv:239) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed rdata == intr_actions (0 [0x0] vs 2 [0x2])
  UVM_ERROR @ 12451443150 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.intr_state reset value: 0x0
  UVM_INFO @ 12451443150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

58.sysrst_ctrl_combo_detect_with_pre_cond.65380960578463569500783179708043647411535945601663155329110914856773831023492
Line 383, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 18781199368 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_ERROR @ 18781199368 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 18781199368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(10) vs exp(5) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

75.sysrst_ctrl_combo_detect_with_pre_cond.27038332843340354895467286591841355908687781108697166634842480271731893428838
Line 384, in log /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13240332741 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(10) vs exp(5) +/-4
  UVM_INFO @ 13465332741 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 13485332741 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 14151421599 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
  UVM_INFO @ 14151421599 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3