Unified Coverage Report :: Assertions

Assertions

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Assertions by Category

	ASSERT	PROPERTIES	SEQUENCES
Total	1028	0	10
Category 0	1028	0	10

Assertions by Severity

	ASSERT	PROPERTIES	SEQUENCES
Total	1028	0	10
Severity 0	1028	0	10

Summary for Assertions

	NUMBER	PERCENT
Total Number	1028	100.00
Uncovered	3	0.29
Success	1025	99.71
Failure	0	0.00
Incomplete	1	0.10
Without Attempts	0	0.00

Summary for Cover Sequences

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	8	80.00
All Matches	2	20.00
First Matches	2	20.00

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COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	908179442	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	908179442	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	908179442	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	908179442	122041	122041	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	908179442	72915	72915	708

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	908179442	122041	122041	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	908179442	72915	72915	708