Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.39 98.86 94.55 100.00 98.08 98.26 98.94 86.07


Total tests in report: 753
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
44.23 44.23 66.58 66.58 44.62 44.62 55.25 55.25 15.38 15.38 69.17 69.17 55.39 55.39 3.25 3.25 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1573588595
66.90 22.67 86.96 20.38 71.23 26.62 64.16 8.90 70.51 55.13 86.88 17.71 83.62 28.23 4.96 1.71 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.2329241724
75.28 8.38 89.57 2.61 78.99 7.76 89.16 25.00 71.79 1.28 89.21 2.33 87.67 4.05 20.60 15.64 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.360720529
79.63 4.34 93.99 4.42 85.06 6.07 94.86 5.71 71.79 0.00 93.75 4.55 89.88 2.22 28.04 7.44 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3543217029
83.50 3.87 94.78 0.78 85.95 0.88 94.86 0.00 80.77 8.97 94.49 0.74 93.83 3.95 39.79 11.75 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4033241548
85.85 2.35 96.32 1.55 89.26 3.31 95.43 0.57 80.77 0.00 95.97 1.48 94.41 0.58 48.76 8.97 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3906687440
87.26 1.41 96.68 0.35 89.81 0.56 96.12 0.68 83.97 3.21 96.27 0.30 95.28 0.87 52.66 3.90 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4073114781
88.50 1.25 97.00 0.32 90.82 1.01 96.12 0.00 83.97 0.00 96.27 0.00 95.47 0.19 59.86 7.20 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.177265013
89.18 0.68 97.42 0.43 92.24 1.42 96.80 0.68 83.97 0.00 96.97 0.70 96.15 0.67 60.68 0.83 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.663417187
89.80 0.62 97.80 0.37 92.90 0.66 97.03 0.23 85.90 1.92 97.23 0.26 96.82 0.67 60.92 0.24 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2620380608
90.35 0.55 97.82 0.02 92.92 0.03 97.03 0.00 85.90 0.00 97.23 0.00 96.82 0.00 64.76 3.84 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3647297443
90.84 0.48 97.87 0.06 93.12 0.20 97.03 0.00 86.54 0.64 97.30 0.07 97.11 0.29 66.88 2.13 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3907389888
91.24 0.41 97.98 0.11 93.15 0.03 97.03 0.00 86.54 0.00 97.30 0.00 97.11 0.00 69.60 2.72 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1337660811
91.64 0.40 98.00 0.02 93.20 0.05 99.32 2.28 86.54 0.00 97.34 0.04 97.21 0.10 69.89 0.30 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3827410155
92.03 0.39 98.12 0.11 93.33 0.13 99.32 0.00 88.46 1.92 97.45 0.11 97.59 0.39 69.95 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1207518537
92.35 0.32 98.19 0.07 93.35 0.03 99.32 0.00 90.38 1.92 97.56 0.11 97.69 0.10 69.95 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1695397969
92.65 0.30 98.23 0.04 93.48 0.13 99.32 0.00 90.38 0.00 97.56 0.00 97.69 0.00 71.90 1.95 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.728918113
92.93 0.28 98.26 0.04 93.48 0.00 99.32 0.00 91.67 1.28 97.67 0.11 97.78 0.10 72.31 0.41 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3572087586
93.20 0.27 98.26 0.00 93.48 0.00 99.32 0.00 91.67 0.00 97.67 0.00 97.78 0.00 74.20 1.89 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2301301136
93.40 0.21 98.28 0.02 93.55 0.08 99.32 0.00 91.67 0.00 97.67 0.00 98.07 0.29 75.27 1.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4015501801
93.61 0.21 98.30 0.02 93.58 0.03 99.32 0.00 91.67 0.00 97.71 0.04 98.07 0.00 76.62 1.36 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2244350886
93.79 0.18 98.36 0.06 93.63 0.05 99.32 0.00 92.31 0.64 97.78 0.07 98.27 0.19 76.86 0.24 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1935624727
93.95 0.16 98.38 0.02 93.63 0.00 99.32 0.00 92.31 0.00 97.78 0.00 98.27 0.00 77.98 1.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.448057452
94.10 0.15 98.38 0.00 93.68 0.05 99.32 0.00 92.31 0.00 97.82 0.04 98.27 0.00 78.93 0.94 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.2090485431
94.24 0.14 98.41 0.04 93.76 0.08 99.32 0.00 92.95 0.64 97.86 0.04 98.46 0.19 78.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2636078952
94.37 0.13 98.45 0.04 93.78 0.03 99.32 0.00 93.59 0.64 97.89 0.04 98.65 0.19 78.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1672253017
94.50 0.13 98.49 0.04 93.83 0.05 99.32 0.00 94.23 0.64 97.93 0.04 98.75 0.10 78.98 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.31473076
94.62 0.12 98.51 0.02 93.88 0.05 99.32 0.00 94.87 0.64 97.97 0.04 98.84 0.10 78.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1068503493
94.74 0.12 98.54 0.04 93.91 0.03 99.32 0.00 95.51 0.64 98.00 0.04 98.94 0.10 78.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1038819966
94.86 0.12 98.54 0.00 93.91 0.00 99.32 0.00 95.51 0.00 98.00 0.00 98.94 0.00 79.81 0.83 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.551752535
94.98 0.12 98.56 0.02 94.06 0.15 99.77 0.46 95.51 0.00 98.08 0.07 98.94 0.00 79.93 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2686736319
95.09 0.11 98.58 0.02 94.11 0.05 99.77 0.00 96.15 0.64 98.11 0.04 98.94 0.00 79.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3313779499
95.19 0.10 98.60 0.02 94.11 0.00 99.77 0.00 96.79 0.64 98.15 0.04 98.94 0.00 79.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1821588442
95.28 0.10 98.62 0.02 94.11 0.00 99.77 0.00 97.44 0.64 98.19 0.04 98.94 0.00 79.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3455562917
95.38 0.10 98.64 0.02 94.11 0.00 99.77 0.00 98.08 0.64 98.23 0.04 98.94 0.00 79.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.2429639090
95.48 0.10 98.66 0.02 94.11 0.00 99.77 0.00 98.08 0.00 98.23 0.00 98.94 0.00 80.58 0.65 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1057131414
95.56 0.08 98.66 0.00 94.11 0.00 99.77 0.00 98.08 0.00 98.23 0.00 98.94 0.00 81.11 0.53 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.757060629
95.63 0.07 98.66 0.00 94.14 0.03 99.77 0.00 98.08 0.00 98.23 0.00 98.94 0.00 81.58 0.47 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1707746294
95.69 0.07 98.66 0.00 94.14 0.00 99.77 0.00 98.08 0.00 98.23 0.00 98.94 0.00 82.05 0.47 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.929858422
95.75 0.05 98.71 0.06 94.21 0.08 100.00 0.23 98.08 0.00 98.23 0.00 98.94 0.00 82.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.4138135591
95.80 0.05 98.71 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 82.41 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.745899544
95.85 0.05 98.71 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 82.76 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2578961128
95.90 0.05 98.71 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 83.12 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3420432329
95.94 0.04 98.71 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 83.41 0.30 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.217917288
95.98 0.04 98.73 0.02 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 83.65 0.24 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3403738852
96.01 0.03 98.73 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 83.88 0.24 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1824528626
96.04 0.03 98.73 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.06 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3291731740
96.06 0.03 98.73 0.00 94.21 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.24 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2942695386
96.09 0.02 98.77 0.04 94.29 0.08 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.30 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3847413081
96.11 0.02 98.79 0.02 94.31 0.03 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.42 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3187189104
96.13 0.02 98.79 0.00 94.34 0.03 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.53 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2198227234
96.15 0.02 98.79 0.00 94.34 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.65 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1253983582
96.16 0.02 98.79 0.00 94.34 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.77 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2619292955
96.18 0.02 98.79 0.00 94.34 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 84.89 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.440721851
96.20 0.02 98.79 0.00 94.34 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 85.01 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3502780861
96.21 0.02 98.79 0.00 94.34 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 85.12 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3024346513
96.23 0.02 98.79 0.00 94.34 0.00 100.00 0.00 98.08 0.00 98.23 0.00 98.94 0.00 85.24 0.12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.773792811
96.25 0.02 98.81 0.02 94.34 0.00 100.00 0.00 98.08 0.00 98.26 0.04 98.94 0.00 85.30 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1294714978
96.26 0.02 98.81 0.00 94.39 0.05 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.36 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2253858101
96.28 0.01 98.82 0.02 94.46 0.08 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.36 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.703758383
96.28 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.42 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2810653623
96.29 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.48 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2399143180
96.30 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.54 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3259945942
96.31 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.60 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.230795946
96.32 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.66 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1037109968
96.33 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.71 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.514370859
96.33 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.77 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2848427552
96.34 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.83 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3215968380
96.35 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.89 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2618024809
96.36 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 85.95 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1868555622
96.37 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 86.01 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2956858547
96.38 0.01 98.82 0.00 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 86.07 0.06 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3820407198
96.38 0.01 98.86 0.04 94.46 0.00 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 86.07 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1389055063
96.39 0.01 98.86 0.00 94.49 0.03 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 86.07 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1627085163
96.39 0.01 98.86 0.00 94.51 0.03 100.00 0.00 98.08 0.00 98.26 0.00 98.94 0.00 86.07 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1084811556

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.172762674
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4282528805
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2070453517
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3196977011
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.63738492
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1317421885
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.503356112
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1553539108
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1775636672
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2637888971
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.614625467
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3321038477
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.748564021
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2796315857
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1922298656
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1990220914



Total test records in report: 753
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2686736319 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:30 PM UTC 24 2565258845 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4282528805 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:31 PM UTC 24 2212869746 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1170798536 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:31 PM UTC 24 2147935353 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1814557768 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:32 PM UTC 24 2639588231 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.339594980 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:33 PM UTC 24 5198253991 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2145308248 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:34 PM UTC 24 2118111256 ps
T1 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1573588595 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:35 PM UTC 24 4114982576 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.130395502 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:36 PM UTC 24 2265870862 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3543217029 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:37 PM UTC 24 2448210485 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3110245597 Aug 27 07:26:37 PM UTC 24 Aug 27 07:26:40 PM UTC 24 2439592863 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3366759370 Aug 27 07:26:36 PM UTC 24 Aug 27 07:26:42 PM UTC 24 2489459102 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.3334102903 Aug 27 07:26:38 PM UTC 24 Aug 27 07:26:43 PM UTC 24 2206148642 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.50169120 Aug 27 07:26:27 PM UTC 24 Aug 27 07:26:43 PM UTC 24 11196477946 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.175012881 Aug 27 07:26:36 PM UTC 24 Aug 27 07:26:44 PM UTC 24 2145976278 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.4138135591 Aug 27 07:26:35 PM UTC 24 Aug 27 07:26:48 PM UTC 24 2012031326 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.623682161 Aug 27 07:26:35 PM UTC 24 Aug 27 07:26:48 PM UTC 24 2111699096 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3101785645 Aug 27 07:26:40 PM UTC 24 Aug 27 07:26:48 PM UTC 24 2615518782 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.256883950 Aug 27 07:26:43 PM UTC 24 Aug 27 07:26:51 PM UTC 24 3259944579 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.4064534608 Aug 27 07:26:40 PM UTC 24 Aug 27 07:26:54 PM UTC 24 2513360428 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3519061275 Aug 27 07:26:44 PM UTC 24 Aug 27 07:26:59 PM UTC 24 5178215196 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.2483679153 Aug 27 07:26:56 PM UTC 24 Aug 27 07:27:00 PM UTC 24 2025806550 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3319238276 Aug 27 07:26:44 PM UTC 24 Aug 27 07:27:06 PM UTC 24 4166176835 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3231857489 Aug 27 07:27:00 PM UTC 24 Aug 27 07:27:07 PM UTC 24 2114531256 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.514451707 Aug 27 07:27:01 PM UTC 24 Aug 27 07:27:09 PM UTC 24 2453337500 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.137990139 Aug 27 07:27:07 PM UTC 24 Aug 27 07:27:12 PM UTC 24 2226368017 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.739350492 Aug 27 07:26:51 PM UTC 24 Aug 27 07:27:13 PM UTC 24 15386157992 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2256743430 Aug 27 07:27:08 PM UTC 24 Aug 27 07:27:13 PM UTC 24 2356860921 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.2090485431 Aug 27 07:26:32 PM UTC 24 Aug 27 07:27:13 PM UTC 24 11962246317 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1457614792 Aug 27 07:26:46 PM UTC 24 Aug 27 07:27:14 PM UTC 24 5857685732 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3963333741 Aug 27 07:27:10 PM UTC 24 Aug 27 07:27:15 PM UTC 24 2141700058 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.663417187 Aug 27 07:26:49 PM UTC 24 Aug 27 07:27:16 PM UTC 24 22697619419 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.143725289 Aug 27 07:27:14 PM UTC 24 Aug 27 07:27:18 PM UTC 24 3566538212 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3775293917 Aug 27 07:27:14 PM UTC 24 Aug 27 07:27:18 PM UTC 24 4799582382 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2821969588 Aug 27 07:27:16 PM UTC 24 Aug 27 07:27:21 PM UTC 24 4718334893 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3906687440 Aug 27 07:27:11 PM UTC 24 Aug 27 07:27:24 PM UTC 24 2517114635 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.1752334106 Aug 27 07:27:23 PM UTC 24 Aug 27 07:27:27 PM UTC 24 2041193416 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.360720529 Aug 27 07:26:45 PM UTC 24 Aug 27 07:27:27 PM UTC 24 60050228847 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1267984884 Aug 27 07:27:12 PM UTC 24 Aug 27 07:27:27 PM UTC 24 2611513147 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1221409194 Aug 27 07:27:19 PM UTC 24 Aug 27 07:27:28 PM UTC 24 3717787311 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.2002521648 Aug 27 07:27:25 PM UTC 24 Aug 27 07:27:29 PM UTC 24 2478917037 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2375865236 Aug 27 07:27:23 PM UTC 24 Aug 27 07:27:32 PM UTC 24 2107388630 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3299046477 Aug 27 07:27:28 PM UTC 24 Aug 27 07:27:32 PM UTC 24 2152534965 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1002749144 Aug 27 07:27:28 PM UTC 24 Aug 27 07:27:33 PM UTC 24 2550700537 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3211569757 Aug 27 07:27:14 PM UTC 24 Aug 27 07:27:35 PM UTC 24 3621698465 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2125079158 Aug 27 07:27:31 PM UTC 24 Aug 27 07:27:35 PM UTC 24 3861861458 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3645933678 Aug 27 07:27:29 PM UTC 24 Aug 27 07:27:36 PM UTC 24 2620497416 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2578961128 Aug 27 07:27:28 PM UTC 24 Aug 27 07:27:36 PM UTC 24 2514097540 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3827410155 Aug 27 07:26:32 PM UTC 24 Aug 27 07:27:39 PM UTC 24 42017867628 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.1737271623 Aug 27 07:27:36 PM UTC 24 Aug 27 07:27:43 PM UTC 24 2479584308 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3677046419 Aug 27 07:27:28 PM UTC 24 Aug 27 07:27:44 PM UTC 24 2423942258 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1275519113 Aug 27 07:27:41 PM UTC 24 Aug 27 07:27:45 PM UTC 24 2043306466 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1240151023 Aug 27 07:27:33 PM UTC 24 Aug 27 07:27:47 PM UTC 24 3984903075 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1389055063 Aug 27 07:26:27 PM UTC 24 Aug 27 07:27:47 PM UTC 24 41827429168 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.3004748441 Aug 27 07:27:45 PM UTC 24 Aug 27 07:27:50 PM UTC 24 2472413780 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.636991126 Aug 27 07:27:48 PM UTC 24 Aug 27 07:27:51 PM UTC 24 2124908685 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2276730785 Aug 27 07:27:48 PM UTC 24 Aug 27 07:27:51 PM UTC 24 2315739403 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2408558370 Aug 27 07:27:46 PM UTC 24 Aug 27 07:27:51 PM UTC 24 2183069787 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.901431806 Aug 27 07:27:44 PM UTC 24 Aug 27 07:27:53 PM UTC 24 2112294504 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.4087873075 Aug 27 07:26:49 PM UTC 24 Aug 27 07:27:56 PM UTC 24 71328392533 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.4255973207 Aug 27 07:27:52 PM UTC 24 Aug 27 07:27:57 PM UTC 24 2640536279 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1395055881 Aug 27 07:27:33 PM UTC 24 Aug 27 07:27:57 PM UTC 24 3880860280 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2491565105 Aug 27 07:28:11 PM UTC 24 Aug 27 07:28:26 PM UTC 24 2511481094 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2981360152 Aug 27 07:27:51 PM UTC 24 Aug 27 07:28:07 PM UTC 24 2510748570 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.86032430 Aug 27 07:27:53 PM UTC 24 Aug 27 07:28:08 PM UTC 24 5712930396 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1627085163 Aug 27 07:27:58 PM UTC 24 Aug 27 07:28:10 PM UTC 24 5157840522 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3124714505 Aug 27 07:27:37 PM UTC 24 Aug 27 07:28:10 PM UTC 24 5759219902 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.444424593 Aug 27 07:27:57 PM UTC 24 Aug 27 07:28:10 PM UTC 24 3556084276 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1245033001 Aug 27 07:28:09 PM UTC 24 Aug 27 07:28:13 PM UTC 24 2129618809 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3573320062 Aug 27 07:28:11 PM UTC 24 Aug 27 07:28:16 PM UTC 24 2480756439 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3206314445 Aug 27 07:28:07 PM UTC 24 Aug 27 07:28:21 PM UTC 24 2012333630 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2104682390 Aug 27 07:28:14 PM UTC 24 Aug 27 07:28:23 PM UTC 24 2616147343 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.3187525331 Aug 27 07:28:11 PM UTC 24 Aug 27 07:28:24 PM UTC 24 2080919857 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.320863336 Aug 27 07:28:22 PM UTC 24 Aug 27 07:28:27 PM UTC 24 3684881742 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2620380608 Aug 27 07:28:24 PM UTC 24 Aug 27 07:28:32 PM UTC 24 6944058510 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.259309780 Aug 27 07:26:27 PM UTC 24 Aug 27 07:28:38 PM UTC 24 46322958734 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2600509925 Aug 27 07:28:17 PM UTC 24 Aug 27 07:28:40 PM UTC 24 4427634105 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.553284393 Aug 27 07:27:17 PM UTC 24 Aug 27 07:28:41 PM UTC 24 23829252656 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.2329241724 Aug 27 07:26:31 PM UTC 24 Aug 27 07:28:42 PM UTC 24 38475968648 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.106092067 Aug 27 07:28:39 PM UTC 24 Aug 27 07:28:42 PM UTC 24 7958399429 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3459668257 Aug 27 07:26:52 PM UTC 24 Aug 27 07:28:43 PM UTC 24 42014981111 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.175400241 Aug 27 07:28:27 PM UTC 24 Aug 27 07:28:45 PM UTC 24 4040859448 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3551251490 Aug 27 07:28:42 PM UTC 24 Aug 27 07:28:47 PM UTC 24 2124202632 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.20047779 Aug 27 07:28:41 PM UTC 24 Aug 27 07:28:48 PM UTC 24 2014669106 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4033521692 Aug 27 07:28:43 PM UTC 24 Aug 27 07:28:48 PM UTC 24 2098968476 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3396744239 Aug 27 07:28:44 PM UTC 24 Aug 27 07:28:49 PM UTC 24 2618717561 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.3678306752 Aug 27 07:28:43 PM UTC 24 Aug 27 07:28:49 PM UTC 24 2496219121 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3187674988 Aug 27 07:27:19 PM UTC 24 Aug 27 07:28:49 PM UTC 24 22012034752 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1778755559 Aug 27 07:28:45 PM UTC 24 Aug 27 07:28:50 PM UTC 24 3969280234 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3647297443 Aug 27 07:27:15 PM UTC 24 Aug 27 07:28:51 PM UTC 24 154260648283 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3106873609 Aug 27 07:28:47 PM UTC 24 Aug 27 07:28:54 PM UTC 24 3324514436 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.2987215750 Aug 27 07:28:44 PM UTC 24 Aug 27 07:28:56 PM UTC 24 2511545218 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3417658296 Aug 27 07:29:55 PM UTC 24 Aug 27 07:29:59 PM UTC 24 2040732132 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1128692094 Aug 27 07:28:55 PM UTC 24 Aug 27 07:28:59 PM UTC 24 2141337520 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3160141738 Aug 27 07:28:33 PM UTC 24 Aug 27 07:28:59 PM UTC 24 9638976388 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3089456031 Aug 27 07:28:52 PM UTC 24 Aug 27 07:29:00 PM UTC 24 2017850097 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.3399274723 Aug 27 07:28:56 PM UTC 24 Aug 27 07:29:02 PM UTC 24 2490418888 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1326569998 Aug 27 07:28:50 PM UTC 24 Aug 27 07:29:03 PM UTC 24 4284126115 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3495352835 Aug 27 07:29:01 PM UTC 24 Aug 27 07:29:04 PM UTC 24 2653438788 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3068140290 Aug 27 07:28:49 PM UTC 24 Aug 27 07:29:04 PM UTC 24 7667860892 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.240312159 Aug 27 07:28:59 PM UTC 24 Aug 27 07:29:06 PM UTC 24 2121535885 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3723428001 Aug 27 07:28:07 PM UTC 24 Aug 27 07:29:08 PM UTC 24 22013502643 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1528840723 Aug 27 07:28:28 PM UTC 24 Aug 27 07:29:10 PM UTC 24 44766618102 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3442277056 Aug 27 07:27:38 PM UTC 24 Aug 27 07:29:12 PM UTC 24 22014517408 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3112700310 Aug 27 07:29:04 PM UTC 24 Aug 27 07:29:12 PM UTC 24 4993532148 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3996326534 Aug 27 07:28:59 PM UTC 24 Aug 27 07:29:12 PM UTC 24 2513284599 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.186366063 Aug 27 07:29:05 PM UTC 24 Aug 27 07:29:17 PM UTC 24 4435615857 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.636799766 Aug 27 07:29:13 PM UTC 24 Aug 27 07:29:18 PM UTC 24 2135316507 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4290441085 Aug 27 07:29:03 PM UTC 24 Aug 27 07:29:18 PM UTC 24 4074968597 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2799134373 Aug 27 07:29:13 PM UTC 24 Aug 27 07:29:18 PM UTC 24 2469499695 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2660887630 Aug 27 07:29:01 PM UTC 24 Aug 27 07:29:20 PM UTC 24 3066198195 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.63738492 Aug 27 07:29:14 PM UTC 24 Aug 27 07:29:21 PM UTC 24 2052578753 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2070453517 Aug 27 07:29:10 PM UTC 24 Aug 27 07:29:22 PM UTC 24 2012559175 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4073114781 Aug 27 07:29:07 PM UTC 24 Aug 27 07:29:23 PM UTC 24 41374016058 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2975878274 Aug 27 07:29:19 PM UTC 24 Aug 27 07:29:24 PM UTC 24 5202863314 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1317421885 Aug 27 07:29:15 PM UTC 24 Aug 27 07:29:26 PM UTC 24 2512303612 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3270933458 Aug 27 07:29:19 PM UTC 24 Aug 27 07:29:26 PM UTC 24 9662522407 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1142840746 Aug 27 07:29:19 PM UTC 24 Aug 27 07:29:27 PM UTC 24 3544776893 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1428468315 Aug 27 07:29:18 PM UTC 24 Aug 27 07:29:28 PM UTC 24 2611812746 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.448057452 Aug 27 07:28:50 PM UTC 24 Aug 27 07:29:28 PM UTC 24 96007921090 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2709857456 Aug 27 07:29:27 PM UTC 24 Aug 27 07:29:29 PM UTC 24 2143662143 ps
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T133 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1744179728 Aug 27 07:29:42 PM UTC 24 Aug 27 07:29:55 PM UTC 24 2254239292 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3814838991 Aug 27 07:29:22 PM UTC 24 Aug 27 07:29:31 PM UTC 24 4655688350 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.4080450368 Aug 27 07:29:28 PM UTC 24 Aug 27 07:29:33 PM UTC 24 2461525510 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1491642471 Aug 27 07:29:30 PM UTC 24 Aug 27 07:29:34 PM UTC 24 2671074934 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1384876877 Aug 27 07:29:29 PM UTC 24 Aug 27 07:29:34 PM UTC 24 2522436356 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.596419158 Aug 27 07:29:31 PM UTC 24 Aug 27 07:29:34 PM UTC 24 2895057707 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1553539108 Aug 27 07:29:34 PM UTC 24 Aug 27 07:29:37 PM UTC 24 5602564126 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.292009781 Aug 27 07:29:05 PM UTC 24 Aug 27 07:29:39 PM UTC 24 27603876180 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2142621792 Aug 27 07:29:25 PM UTC 24 Aug 27 07:29:40 PM UTC 24 9479598233 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3736105240 Aug 27 07:29:27 PM UTC 24 Aug 27 07:29:40 PM UTC 24 2013541829 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.2625142027 Aug 27 07:27:37 PM UTC 24 Aug 27 07:29:40 PM UTC 24 79879379861 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1575978763 Aug 27 07:29:29 PM UTC 24 Aug 27 07:29:42 PM UTC 24 2068899619 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2114946216 Aug 27 07:29:31 PM UTC 24 Aug 27 07:29:42 PM UTC 24 3213727072 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.282366955 Aug 27 07:29:41 PM UTC 24 Aug 27 07:29:46 PM UTC 24 2472570847 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.4107301977 Aug 27 07:27:58 PM UTC 24 Aug 27 07:29:47 PM UTC 24 59994317780 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.578514660 Aug 27 07:29:42 PM UTC 24 Aug 27 07:29:47 PM UTC 24 2525294213 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.4223700802 Aug 27 07:29:41 PM UTC 24 Aug 27 07:29:48 PM UTC 24 2108646089 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3724771708 Aug 27 07:29:35 PM UTC 24 Aug 27 07:29:51 PM UTC 24 4232823438 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.209576927 Aug 27 07:29:25 PM UTC 24 Aug 27 07:29:51 PM UTC 24 5005699561 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1711651733 Aug 27 07:29:47 PM UTC 24 Aug 27 07:29:51 PM UTC 24 2657039532 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2810653623 Aug 27 07:29:48 PM UTC 24 Aug 27 07:29:51 PM UTC 24 3663615207 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4015501801 Aug 27 07:28:01 PM UTC 24 Aug 27 07:29:53 PM UTC 24 32998301508 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1847732788 Aug 27 07:29:49 PM UTC 24 Aug 27 07:29:54 PM UTC 24 5679435950 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.3046243788 Aug 27 07:29:41 PM UTC 24 Aug 27 07:29:54 PM UTC 24 2012878304 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.2757335889 Aug 27 07:29:56 PM UTC 24 Aug 27 07:29:59 PM UTC 24 2526229928 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3937290636 Aug 27 07:29:55 PM UTC 24 Aug 27 07:30:00 PM UTC 24 2132267925 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2244350886 Aug 27 07:29:09 PM UTC 24 Aug 27 07:30:01 PM UTC 24 15397572330 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1255608389 Aug 27 07:30:00 PM UTC 24 Aug 27 07:30:05 PM UTC 24 2071173073 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1137661787 Aug 27 07:29:52 PM UTC 24 Aug 27 07:30:06 PM UTC 24 3130569807 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2313244547 Aug 27 07:30:01 PM UTC 24 Aug 27 07:30:06 PM UTC 24 2532926327 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3907389888 Aug 27 07:29:38 PM UTC 24 Aug 27 07:30:06 PM UTC 24 42912390315 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.589403070 Aug 27 07:30:01 PM UTC 24 Aug 27 07:30:06 PM UTC 24 2635035089 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2282692879 Aug 27 07:30:02 PM UTC 24 Aug 27 07:30:07 PM UTC 24 3174232166 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.1589954367 Aug 27 07:29:20 PM UTC 24 Aug 27 07:30:08 PM UTC 24 63370493703 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2332998614 Aug 27 07:27:57 PM UTC 24 Aug 27 07:30:09 PM UTC 24 74825896560 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1929660359 Aug 27 07:30:06 PM UTC 24 Aug 27 07:30:09 PM UTC 24 3166201525 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1602844797 Aug 27 07:30:09 PM UTC 24 Aug 27 07:30:15 PM UTC 24 2024852566 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.4200501952 Aug 27 07:30:10 PM UTC 24 Aug 27 07:30:15 PM UTC 24 2139540905 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2253858101 Aug 27 07:29:52 PM UTC 24 Aug 27 07:30:19 PM UTC 24 4731133023 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2133599476 Aug 27 07:30:16 PM UTC 24 Aug 27 07:30:19 PM UTC 24 2531223459 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3186338124 Aug 27 07:30:09 PM UTC 24 Aug 27 07:30:20 PM UTC 24 6767649604 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3280246785 Aug 27 07:29:35 PM UTC 24 Aug 27 07:30:20 PM UTC 24 96758465175 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.3332125092 Aug 27 07:30:16 PM UTC 24 Aug 27 07:30:20 PM UTC 24 2051399461 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1462813150 Aug 27 07:30:07 PM UTC 24 Aug 27 07:30:23 PM UTC 24 8507969522 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3710117397 Aug 27 07:30:20 PM UTC 24 Aug 27 07:30:23 PM UTC 24 2573329155 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3520420809 Aug 27 07:30:20 PM UTC 24 Aug 27 07:30:29 PM UTC 24 2613402612 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1119819632 Aug 27 07:28:50 PM UTC 24 Aug 27 07:30:31 PM UTC 24 102871527500 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2718069976 Aug 27 07:30:08 PM UTC 24 Aug 27 07:30:39 PM UTC 24 5781879430 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2245234908 Aug 27 07:30:20 PM UTC 24 Aug 27 07:30:39 PM UTC 24 3642966429 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1647160042 Aug 27 07:30:32 PM UTC 24 Aug 27 07:30:40 PM UTC 24 12146944222 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2554945725 Aug 27 07:30:20 PM UTC 24 Aug 27 07:30:41 PM UTC 24 4023839952 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.177265013 Aug 27 07:29:04 PM UTC 24 Aug 27 07:30:42 PM UTC 24 128948435696 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.475415052 Aug 27 07:30:40 PM UTC 24 Aug 27 07:30:45 PM UTC 24 2130438148 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.2139951893 Aug 27 07:30:41 PM UTC 24 Aug 27 07:30:46 PM UTC 24 2240283495 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.1062199868 Aug 27 07:30:42 PM UTC 24 Aug 27 07:30:47 PM UTC 24 2530328182 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.74082974 Aug 27 07:30:31 PM UTC 24 Aug 27 07:30:47 PM UTC 24 18372108189 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.808899332 Aug 27 07:30:40 PM UTC 24 Aug 27 07:30:51 PM UTC 24 2014434999 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.175583082 Aug 27 07:30:42 PM UTC 24 Aug 27 07:30:52 PM UTC 24 2611528169 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3940700498 Aug 27 07:30:46 PM UTC 24 Aug 27 07:30:53 PM UTC 24 3632778157 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2544067427 Aug 27 07:30:47 PM UTC 24 Aug 27 07:30:55 PM UTC 24 3112758819 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.3947827127 Aug 27 07:30:41 PM UTC 24 Aug 27 07:30:57 PM UTC 24 2455625371 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.1380053217 Aug 27 07:28:25 PM UTC 24 Aug 27 07:31:03 PM UTC 24 185461755855 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1465250177 Aug 27 07:29:23 PM UTC 24 Aug 27 07:31:04 PM UTC 24 25830065403 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.345941997 Aug 27 07:31:00 PM UTC 24 Aug 27 07:31:07 PM UTC 24 2112607066 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1045606891 Aug 27 07:30:58 PM UTC 24 Aug 27 07:31:09 PM UTC 24 2014267052 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.3777586046 Aug 27 07:31:04 PM UTC 24 Aug 27 07:31:09 PM UTC 24 2075501588 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2087144806 Aug 27 07:30:55 PM UTC 24 Aug 27 07:31:10 PM UTC 24 16813055426 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.2840950329 Aug 27 07:30:52 PM UTC 24 Aug 27 07:31:13 PM UTC 24 5294588003 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.4034380570 Aug 27 07:31:08 PM UTC 24 Aug 27 07:31:13 PM UTC 24 2626596712 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2544086242 Aug 27 07:31:03 PM UTC 24 Aug 27 07:31:15 PM UTC 24 2449546716 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1655299231 Aug 27 07:29:52 PM UTC 24 Aug 27 07:31:15 PM UTC 24 32815136064 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3632300410 Aug 27 07:31:09 PM UTC 24 Aug 27 07:31:15 PM UTC 24 4709964728 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2164941496 Aug 27 07:31:10 PM UTC 24 Aug 27 07:31:16 PM UTC 24 3521966449 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.733724203 Aug 27 07:31:05 PM UTC 24 Aug 27 07:31:17 PM UTC 24 2510058167 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1125437074 Aug 27 07:30:53 PM UTC 24 Aug 27 07:31:21 PM UTC 24 4639855778 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.666959976 Aug 27 07:31:17 PM UTC 24 Aug 27 07:31:22 PM UTC 24 2025331256 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3468242104 Aug 27 07:31:18 PM UTC 24 Aug 27 07:31:23 PM UTC 24 2123932022 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.611137034 Aug 27 07:30:07 PM UTC 24 Aug 27 07:31:25 PM UTC 24 27827534843 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.3659453849 Aug 27 07:31:22 PM UTC 24 Aug 27 07:31:26 PM UTC 24 2485633117 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3377674844 Aug 27 07:31:22 PM UTC 24 Aug 27 07:31:27 PM UTC 24 2050174905 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.381233655 Aug 27 07:31:16 PM UTC 24 Aug 27 07:31:32 PM UTC 24 3280257774 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2642953829 Aug 27 07:30:07 PM UTC 24 Aug 27 07:31:32 PM UTC 24 24225093448 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3768452494 Aug 27 07:31:27 PM UTC 24 Aug 27 07:31:33 PM UTC 24 4075618225 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3187189104 Aug 27 07:29:36 PM UTC 24 Aug 27 07:31:34 PM UTC 24 67186701938 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2838898792 Aug 27 07:31:33 PM UTC 24 Aug 27 07:31:36 PM UTC 24 3959604323 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2289974161 Aug 27 07:31:26 PM UTC 24 Aug 27 07:31:37 PM UTC 24 2611847375 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2149775798 Aug 27 07:31:23 PM UTC 24 Aug 27 07:31:38 PM UTC 24 2510946851 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1090986974 Aug 27 07:31:27 PM UTC 24 Aug 27 07:31:39 PM UTC 24 3921997526 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3998576910 Aug 27 07:31:15 PM UTC 24 Aug 27 07:31:41 PM UTC 24 70850926762 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.364343968 Aug 27 07:30:07 PM UTC 24 Aug 27 07:31:41 PM UTC 24 339862720285 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2054458232 Aug 27 07:31:40 PM UTC 24 Aug 27 07:31:44 PM UTC 24 2522403768 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.3491240678 Aug 27 07:31:39 PM UTC 24 Aug 27 07:31:44 PM UTC 24 2151284266 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.2753408852 Aug 27 07:31:39 PM UTC 24 Aug 27 07:31:44 PM UTC 24 2035269747 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3342301785 Aug 27 07:31:38 PM UTC 24 Aug 27 07:31:45 PM UTC 24 17918576165 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.503356112 Aug 27 07:29:40 PM UTC 24 Aug 27 07:31:46 PM UTC 24 83804018270 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1068503493 Aug 27 07:31:34 PM UTC 24 Aug 27 07:31:50 PM UTC 24 5033178768 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.336816825 Aug 27 07:31:45 PM UTC 24 Aug 27 07:31:50 PM UTC 24 2630287466 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.610518515 Aug 27 07:31:43 PM UTC 24 Aug 27 07:31:52 PM UTC 24 2510630762 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1777199139 Aug 27 07:31:42 PM UTC 24 Aug 27 07:31:52 PM UTC 24 2074113843 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1597447891 Aug 27 07:31:45 PM UTC 24 Aug 27 07:31:52 PM UTC 24 3736253016 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1623206132 Aug 27 07:31:46 PM UTC 24 Aug 27 07:31:52 PM UTC 24 2872497199 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2784914526 Aug 27 07:30:24 PM UTC 24 Aug 27 07:31:55 PM UTC 24 24081329104 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2661785336 Aug 27 07:31:52 PM UTC 24 Aug 27 07:31:57 PM UTC 24 2030864327 ps
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T296 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3299016780 Aug 27 07:31:37 PM UTC 24 Aug 27 07:32:07 PM UTC 24 6110343441 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2916235440 Aug 27 07:31:45 PM UTC 24 Aug 27 07:32:07 PM UTC 24 3868009846 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2680489738 Aug 27 07:32:05 PM UTC 24 Aug 27 07:32:10 PM UTC 24 9182086911 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2873824108 Aug 27 07:32:02 PM UTC 24 Aug 27 07:32:11 PM UTC 24 4666440326 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.1923487272 Aug 27 07:31:56 PM UTC 24 Aug 27 07:32:11 PM UTC 24 2452279289 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3887794306 Aug 27 07:32:02 PM UTC 24 Aug 27 07:32:16 PM UTC 24 2608506268 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1701087295 Aug 27 07:29:52 PM UTC 24 Aug 27 07:32:18 PM UTC 24 95577621043 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.775382487 Aug 27 07:32:17 PM UTC 24 Aug 27 07:32:21 PM UTC 24 2015677317 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1089863561 Aug 27 07:32:11 PM UTC 24 Aug 27 07:32:21 PM UTC 24 2675523223 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.419767418 Aug 27 07:32:02 PM UTC 24 Aug 27 07:32:22 PM UTC 24 3549431911 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4033241548 Aug 27 07:31:52 PM UTC 24 Aug 27 07:32:23 PM UTC 24 67562427179 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3690153994 Aug 27 07:32:20 PM UTC 24 Aug 27 07:32:23 PM UTC 24 2138339982 ps
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T217 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1853865308 Aug 27 07:31:52 PM UTC 24 Aug 27 07:32:25 PM UTC 24 9822916283 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1329282002 Aug 27 07:31:47 PM UTC 24 Aug 27 07:32:26 PM UTC 24 148261282597 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.172762674 Aug 27 07:26:27 PM UTC 24 Aug 27 07:32:27 PM UTC 24 125196744461 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1827665993 Aug 27 07:32:22 PM UTC 24 Aug 27 07:32:27 PM UTC 24 2230239929 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1095165729 Aug 27 07:32:23 PM UTC 24 Aug 27 07:32:28 PM UTC 24 2525695750 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.587513461 Aug 27 07:32:24 PM UTC 24 Aug 27 07:32:34 PM UTC 24 2617521214 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1671773744 Aug 27 07:32:22 PM UTC 24 Aug 27 07:32:35 PM UTC 24 2445522936 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3074734621 Aug 27 07:30:48 PM UTC 24 Aug 27 07:32:37 PM UTC 24 924041601571 ps
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