Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
756 |
1 |
|
|
T15 |
6 |
|
T17 |
12 |
|
T25 |
11 |
| auto[1] |
724 |
1 |
|
|
T15 |
14 |
|
T17 |
8 |
|
T25 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
720 |
1 |
|
|
T15 |
9 |
|
T17 |
11 |
|
T25 |
10 |
| auto[1] |
760 |
1 |
|
|
T15 |
11 |
|
T17 |
9 |
|
T25 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
725 |
1 |
|
|
T15 |
9 |
|
T17 |
8 |
|
T25 |
7 |
| auto[1] |
755 |
1 |
|
|
T15 |
11 |
|
T17 |
12 |
|
T25 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T15 |
10 |
|
T17 |
11 |
|
T25 |
9 |
| auto[1] |
694 |
1 |
|
|
T15 |
10 |
|
T17 |
9 |
|
T25 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
739 |
1 |
|
|
T15 |
12 |
|
T17 |
6 |
|
T25 |
11 |
| auto[1] |
741 |
1 |
|
|
T15 |
8 |
|
T17 |
14 |
|
T25 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
740 |
1 |
|
|
T15 |
9 |
|
T17 |
11 |
|
T25 |
10 |
| auto[1] |
740 |
1 |
|
|
T15 |
11 |
|
T17 |
9 |
|
T25 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
746 |
1 |
|
|
T15 |
12 |
|
T17 |
10 |
|
T25 |
8 |
| auto[1] |
734 |
1 |
|
|
T15 |
8 |
|
T17 |
10 |
|
T25 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
712 |
1 |
|
|
T15 |
5 |
|
T17 |
10 |
|
T25 |
6 |
| auto[1] |
768 |
1 |
|
|
T15 |
15 |
|
T17 |
10 |
|
T25 |
14 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
755 |
1 |
|
|
T15 |
7 |
|
T17 |
10 |
|
T25 |
12 |
| auto[1] |
725 |
1 |
|
|
T15 |
13 |
|
T17 |
10 |
|
T25 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
717 |
1 |
|
|
T15 |
11 |
|
T17 |
10 |
|
T25 |
9 |
| auto[1] |
763 |
1 |
|
|
T15 |
9 |
|
T17 |
10 |
|
T25 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
729 |
1 |
|
|
T15 |
8 |
|
T17 |
9 |
|
T25 |
11 |
| auto[1] |
751 |
1 |
|
|
T15 |
12 |
|
T17 |
11 |
|
T25 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
732 |
1 |
|
|
T15 |
12 |
|
T17 |
9 |
|
T25 |
7 |
| auto[1] |
748 |
1 |
|
|
T15 |
8 |
|
T17 |
11 |
|
T25 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
750 |
1 |
|
|
T15 |
10 |
|
T17 |
12 |
|
T25 |
12 |
| auto[1] |
730 |
1 |
|
|
T15 |
10 |
|
T17 |
8 |
|
T25 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
720 |
1 |
|
|
T15 |
9 |
|
T17 |
11 |
|
T25 |
10 |
| auto[1] |
760 |
1 |
|
|
T15 |
11 |
|
T17 |
9 |
|
T25 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
740 |
1 |
|
|
T15 |
7 |
|
T17 |
9 |
|
T25 |
8 |
| auto[1] |
740 |
1 |
|
|
T15 |
13 |
|
T17 |
11 |
|
T25 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
685 |
1 |
|
|
T15 |
8 |
|
T17 |
10 |
|
T25 |
10 |
| auto[1] |
795 |
1 |
|
|
T15 |
12 |
|
T17 |
10 |
|
T25 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
752 |
1 |
|
|
T15 |
11 |
|
T17 |
12 |
|
T25 |
11 |
| auto[1] |
728 |
1 |
|
|
T15 |
9 |
|
T17 |
8 |
|
T25 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
759 |
1 |
|
|
T15 |
10 |
|
T17 |
11 |
|
T25 |
8 |
| auto[1] |
721 |
1 |
|
|
T15 |
10 |
|
T17 |
9 |
|
T25 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
735 |
1 |
|
|
T15 |
12 |
|
T17 |
11 |
|
T25 |
9 |
| auto[1] |
745 |
1 |
|
|
T15 |
8 |
|
T17 |
9 |
|
T25 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
709 |
1 |
|
|
T15 |
11 |
|
T17 |
9 |
|
T25 |
11 |
| auto[1] |
771 |
1 |
|
|
T15 |
9 |
|
T17 |
11 |
|
T25 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
765 |
1 |
|
|
T15 |
8 |
|
T17 |
12 |
|
T25 |
10 |
| auto[1] |
715 |
1 |
|
|
T15 |
12 |
|
T17 |
8 |
|
T25 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
781 |
1 |
|
|
T15 |
11 |
|
T17 |
12 |
|
T25 |
6 |
| auto[1] |
699 |
1 |
|
|
T15 |
9 |
|
T17 |
8 |
|
T25 |
14 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
711 |
1 |
|
|
T15 |
12 |
|
T17 |
5 |
|
T25 |
6 |
| auto[1] |
769 |
1 |
|
|
T15 |
8 |
|
T17 |
15 |
|
T25 |
14 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
732 |
1 |
|
|
T15 |
12 |
|
T17 |
9 |
|
T25 |
7 |
| auto[1] |
748 |
1 |
|
|
T15 |
8 |
|
T17 |
11 |
|
T25 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
351 |
1 |
|
|
T15 |
2 |
|
T17 |
3 |
|
T25 |
2 |
| auto[0] |
auto[1] |
389 |
1 |
|
|
T15 |
5 |
|
T17 |
6 |
|
T25 |
6 |
| auto[1] |
auto[0] |
374 |
1 |
|
|
T15 |
7 |
|
T17 |
5 |
|
T25 |
5 |
| auto[1] |
auto[1] |
366 |
1 |
|
|
T15 |
6 |
|
T17 |
6 |
|
T25 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
354 |
1 |
|
|
T15 |
3 |
|
T17 |
5 |
|
T25 |
4 |
| auto[0] |
auto[1] |
331 |
1 |
|
|
T15 |
5 |
|
T17 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
432 |
1 |
|
|
T15 |
7 |
|
T17 |
6 |
|
T25 |
5 |
| auto[1] |
auto[1] |
363 |
1 |
|
|
T15 |
5 |
|
T17 |
4 |
|
T25 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
382 |
1 |
|
|
T15 |
5 |
|
T17 |
4 |
|
T25 |
7 |
| auto[0] |
auto[1] |
370 |
1 |
|
|
T15 |
6 |
|
T17 |
8 |
|
T25 |
4 |
| auto[1] |
auto[0] |
357 |
1 |
|
|
T15 |
7 |
|
T17 |
2 |
|
T25 |
4 |
| auto[1] |
auto[1] |
371 |
1 |
|
|
T15 |
2 |
|
T17 |
6 |
|
T25 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
386 |
1 |
|
|
T15 |
3 |
|
T17 |
6 |
|
T25 |
5 |
| auto[0] |
auto[1] |
373 |
1 |
|
|
T15 |
7 |
|
T17 |
5 |
|
T25 |
3 |
| auto[1] |
auto[0] |
354 |
1 |
|
|
T15 |
6 |
|
T17 |
5 |
|
T25 |
5 |
| auto[1] |
auto[1] |
367 |
1 |
|
|
T15 |
4 |
|
T17 |
4 |
|
T25 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
380 |
1 |
|
|
T15 |
6 |
|
T17 |
6 |
|
T25 |
4 |
| auto[0] |
auto[1] |
355 |
1 |
|
|
T15 |
6 |
|
T17 |
5 |
|
T25 |
5 |
| auto[1] |
auto[0] |
366 |
1 |
|
|
T15 |
6 |
|
T17 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
379 |
1 |
|
|
T15 |
2 |
|
T17 |
5 |
|
T25 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
350 |
1 |
|
|
T15 |
2 |
|
T17 |
5 |
|
T25 |
4 |
| auto[0] |
auto[1] |
359 |
1 |
|
|
T15 |
9 |
|
T17 |
4 |
|
T25 |
7 |
| auto[1] |
auto[0] |
362 |
1 |
|
|
T15 |
3 |
|
T17 |
5 |
|
T25 |
2 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T15 |
6 |
|
T17 |
6 |
|
T25 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
378 |
1 |
|
|
T15 |
6 |
|
T17 |
5 |
|
T25 |
3 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T15 |
5 |
|
T17 |
7 |
|
T25 |
3 |
| auto[1] |
auto[0] |
339 |
1 |
|
|
T15 |
5 |
|
T17 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
360 |
1 |
|
|
T15 |
4 |
|
T17 |
3 |
|
T25 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
349 |
1 |
|
|
T15 |
5 |
|
T17 |
1 |
|
T25 |
4 |
| auto[0] |
auto[1] |
362 |
1 |
|
|
T15 |
7 |
|
T17 |
4 |
|
T25 |
2 |
| auto[1] |
auto[0] |
380 |
1 |
|
|
T15 |
3 |
|
T17 |
8 |
|
T25 |
7 |
| auto[1] |
auto[1] |
389 |
1 |
|
|
T15 |
5 |
|
T17 |
7 |
|
T25 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
383 |
1 |
|
|
T15 |
4 |
|
T17 |
7 |
|
T25 |
7 |
| auto[0] |
auto[1] |
367 |
1 |
|
|
T15 |
6 |
|
T17 |
5 |
|
T25 |
5 |
| auto[1] |
auto[0] |
373 |
1 |
|
|
T15 |
2 |
|
T17 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
357 |
1 |
|
|
T15 |
8 |
|
T17 |
3 |
|
T25 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
720 |
1 |
|
|
T15 |
9 |
|
T17 |
11 |
|
T25 |
10 |
| auto[1] |
auto[1] |
760 |
1 |
|
|
T15 |
11 |
|
T17 |
9 |
|
T25 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
376 |
1 |
|
|
T15 |
3 |
|
T17 |
7 |
|
T25 |
5 |
| auto[0] |
auto[1] |
389 |
1 |
|
|
T15 |
5 |
|
T17 |
5 |
|
T25 |
5 |
| auto[1] |
auto[0] |
379 |
1 |
|
|
T15 |
4 |
|
T17 |
3 |
|
T25 |
7 |
| auto[1] |
auto[1] |
336 |
1 |
|
|
T15 |
8 |
|
T17 |
5 |
|
T25 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
732 |
1 |
|
|
T15 |
12 |
|
T17 |
9 |
|
T25 |
7 |
| auto[1] |
auto[1] |
748 |
1 |
|
|
T15 |
8 |
|
T17 |
11 |
|
T25 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24 |
1 |
|
|
T393 |
9 |
|
T105 |
9 |
|
T302 |
6 |
| auto[1] |
36 |
1 |
|
|
T393 |
11 |
|
T105 |
11 |
|
T302 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T393 |
13 |
|
T105 |
11 |
|
T302 |
9 |
| auto[1] |
27 |
1 |
|
|
T393 |
7 |
|
T105 |
9 |
|
T302 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T393 |
8 |
|
T105 |
10 |
|
T302 |
9 |
| auto[1] |
33 |
1 |
|
|
T393 |
12 |
|
T105 |
10 |
|
T302 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24 |
1 |
|
|
T393 |
9 |
|
T105 |
6 |
|
T302 |
9 |
| auto[1] |
36 |
1 |
|
|
T393 |
11 |
|
T105 |
14 |
|
T302 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T393 |
12 |
|
T105 |
8 |
|
T302 |
6 |
| auto[1] |
34 |
1 |
|
|
T393 |
8 |
|
T105 |
12 |
|
T302 |
14 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T393 |
8 |
|
T105 |
6 |
|
T302 |
13 |
| auto[1] |
33 |
1 |
|
|
T393 |
12 |
|
T105 |
14 |
|
T302 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T393 |
10 |
|
T105 |
9 |
|
T302 |
10 |
| auto[1] |
31 |
1 |
|
|
T393 |
10 |
|
T105 |
11 |
|
T302 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T393 |
8 |
|
T105 |
11 |
|
T302 |
7 |
| auto[1] |
34 |
1 |
|
|
T393 |
12 |
|
T105 |
9 |
|
T302 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T393 |
12 |
|
T105 |
8 |
|
T302 |
9 |
| auto[1] |
31 |
1 |
|
|
T393 |
8 |
|
T105 |
12 |
|
T302 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T393 |
10 |
|
T105 |
9 |
|
T302 |
12 |
| auto[1] |
29 |
1 |
|
|
T393 |
10 |
|
T105 |
11 |
|
T302 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
28 |
1 |
|
|
T393 |
10 |
|
T105 |
9 |
|
T302 |
9 |
| auto[1] |
32 |
1 |
|
|
T393 |
10 |
|
T105 |
11 |
|
T302 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24 |
1 |
|
|
T393 |
6 |
|
T105 |
10 |
|
T302 |
8 |
| auto[1] |
36 |
1 |
|
|
T393 |
14 |
|
T105 |
10 |
|
T302 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T393 |
14 |
|
T105 |
9 |
|
T302 |
11 |
| auto[1] |
26 |
1 |
|
|
T393 |
6 |
|
T105 |
11 |
|
T302 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T393 |
13 |
|
T105 |
11 |
|
T302 |
9 |
| auto[1] |
27 |
1 |
|
|
T393 |
7 |
|
T105 |
9 |
|
T302 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
37 |
1 |
|
|
T393 |
11 |
|
T105 |
11 |
|
T302 |
15 |
| auto[1] |
23 |
1 |
|
|
T393 |
9 |
|
T105 |
9 |
|
T302 |
5 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T393 |
12 |
|
T105 |
11 |
|
T302 |
11 |
| auto[1] |
26 |
1 |
|
|
T393 |
8 |
|
T105 |
9 |
|
T302 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T393 |
8 |
|
T105 |
9 |
|
T302 |
10 |
| auto[1] |
33 |
1 |
|
|
T393 |
12 |
|
T105 |
11 |
|
T302 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
22 |
1 |
|
|
T393 |
8 |
|
T105 |
7 |
|
T302 |
7 |
| auto[1] |
38 |
1 |
|
|
T393 |
12 |
|
T105 |
13 |
|
T302 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T393 |
7 |
|
T105 |
12 |
|
T302 |
11 |
| auto[1] |
30 |
1 |
|
|
T393 |
13 |
|
T105 |
8 |
|
T302 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T393 |
5 |
|
T105 |
12 |
|
T302 |
10 |
| auto[1] |
33 |
1 |
|
|
T393 |
15 |
|
T105 |
8 |
|
T302 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T393 |
10 |
|
T105 |
10 |
|
T302 |
9 |
| auto[1] |
31 |
1 |
|
|
T393 |
10 |
|
T105 |
10 |
|
T302 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T393 |
11 |
|
T105 |
11 |
|
T302 |
11 |
| auto[1] |
27 |
1 |
|
|
T393 |
9 |
|
T105 |
9 |
|
T302 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T393 |
9 |
|
T105 |
15 |
|
T302 |
10 |
| auto[1] |
26 |
1 |
|
|
T393 |
11 |
|
T105 |
5 |
|
T302 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
24 |
1 |
|
|
T393 |
6 |
|
T105 |
10 |
|
T302 |
8 |
| auto[1] |
36 |
1 |
|
|
T393 |
14 |
|
T105 |
10 |
|
T302 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
17 |
1 |
|
|
T393 |
3 |
|
T105 |
7 |
|
T302 |
7 |
| auto[0] |
auto[1] |
20 |
1 |
|
|
T393 |
8 |
|
T105 |
4 |
|
T302 |
8 |
| auto[1] |
auto[0] |
10 |
1 |
|
|
T393 |
5 |
|
T105 |
3 |
|
T302 |
2 |
| auto[1] |
auto[1] |
13 |
1 |
|
|
T393 |
4 |
|
T105 |
6 |
|
T302 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
14 |
1 |
|
|
T393 |
4 |
|
T105 |
5 |
|
T302 |
5 |
| auto[0] |
auto[1] |
20 |
1 |
|
|
T393 |
8 |
|
T105 |
6 |
|
T302 |
6 |
| auto[1] |
auto[0] |
10 |
1 |
|
|
T393 |
5 |
|
T105 |
1 |
|
T302 |
4 |
| auto[1] |
auto[1] |
16 |
1 |
|
|
T393 |
3 |
|
T105 |
8 |
|
T302 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
12 |
1 |
|
|
T393 |
5 |
|
T105 |
6 |
|
T302 |
1 |
| auto[0] |
auto[1] |
15 |
1 |
|
|
T393 |
3 |
|
T105 |
3 |
|
T302 |
9 |
| auto[1] |
auto[0] |
14 |
1 |
|
|
T393 |
7 |
|
T105 |
2 |
|
T302 |
5 |
| auto[1] |
auto[1] |
19 |
1 |
|
|
T393 |
5 |
|
T105 |
9 |
|
T302 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
10 |
1 |
|
|
T393 |
3 |
|
T105 |
4 |
|
T302 |
3 |
| auto[0] |
auto[1] |
12 |
1 |
|
|
T393 |
5 |
|
T105 |
3 |
|
T302 |
4 |
| auto[1] |
auto[0] |
17 |
1 |
|
|
T393 |
5 |
|
T105 |
2 |
|
T302 |
10 |
| auto[1] |
auto[1] |
21 |
1 |
|
|
T393 |
7 |
|
T105 |
11 |
|
T302 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
16 |
1 |
|
|
T393 |
4 |
|
T105 |
6 |
|
T302 |
6 |
| auto[0] |
auto[1] |
14 |
1 |
|
|
T393 |
3 |
|
T105 |
6 |
|
T302 |
5 |
| auto[1] |
auto[0] |
13 |
1 |
|
|
T393 |
6 |
|
T105 |
3 |
|
T302 |
4 |
| auto[1] |
auto[1] |
17 |
1 |
|
|
T393 |
7 |
|
T105 |
5 |
|
T302 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
13 |
1 |
|
|
T393 |
2 |
|
T105 |
7 |
|
T302 |
4 |
| auto[0] |
auto[1] |
14 |
1 |
|
|
T393 |
3 |
|
T105 |
5 |
|
T302 |
6 |
| auto[1] |
auto[0] |
13 |
1 |
|
|
T393 |
6 |
|
T105 |
4 |
|
T302 |
3 |
| auto[1] |
auto[1] |
20 |
1 |
|
|
T393 |
9 |
|
T105 |
4 |
|
T302 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
17 |
1 |
|
|
T393 |
5 |
|
T105 |
4 |
|
T302 |
8 |
| auto[0] |
auto[1] |
16 |
1 |
|
|
T393 |
6 |
|
T105 |
7 |
|
T302 |
3 |
| auto[1] |
auto[0] |
14 |
1 |
|
|
T393 |
5 |
|
T105 |
5 |
|
T302 |
4 |
| auto[1] |
auto[1] |
13 |
1 |
|
|
T393 |
4 |
|
T105 |
4 |
|
T302 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
16 |
1 |
|
|
T393 |
4 |
|
T105 |
6 |
|
T302 |
6 |
| auto[0] |
auto[1] |
18 |
1 |
|
|
T393 |
5 |
|
T105 |
9 |
|
T302 |
4 |
| auto[1] |
auto[0] |
12 |
1 |
|
|
T393 |
6 |
|
T105 |
3 |
|
T302 |
3 |
| auto[1] |
auto[1] |
14 |
1 |
|
|
T393 |
5 |
|
T105 |
2 |
|
T302 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
11 |
1 |
|
|
T393 |
6 |
|
T105 |
3 |
|
T302 |
2 |
| auto[0] |
auto[1] |
23 |
1 |
|
|
T393 |
8 |
|
T105 |
6 |
|
T302 |
9 |
| auto[1] |
auto[0] |
13 |
1 |
|
|
T393 |
3 |
|
T105 |
6 |
|
T302 |
4 |
| auto[1] |
auto[1] |
13 |
1 |
|
|
T393 |
3 |
|
T105 |
5 |
|
T302 |
5 |