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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 47 1 T36 1 T58 1 T42 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 21 1 T56 1 T44 1 T133 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 42 1 T36 1 T118 1 T298 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 22 1 T41 1 T44 1 T135 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 53 1 T58 2 T42 1 T130 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 21 1 T42 1 T312 1 T133 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 48 1 T36 2 T57 1 T40 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 28 1 T56 1 T41 3 T43 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 42 1 T58 1 T45 1 T302 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 22 1 T56 2 T57 2 T41 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 45 1 T58 1 T114 1 T45 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 16 1 T41 1 T43 1 T133 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 52 1 T42 1 T130 3 T302 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 25 1 T41 1 T42 2 T130 5
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 45 1 T36 2 T40 2 T58 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 40 1 T56 1 T41 1 T43 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 63 1 T36 1 T58 1 T45 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 14 1 T132 1 T371 1 T370 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 64 1 T40 3 T42 2 T114 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 21 1 T57 1 T44 2 T132 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 36 1 T58 1 T302 1 T280 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 19 1 T56 1 T57 2 T43 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 27 1 T36 1 T45 1 T298 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 22 1 T56 1 T57 1 T44 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 51 1 T58 1 T114 4 T298 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 18 1 T36 4 T56 1 T43 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 48 1 T36 1 T45 1 T302 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 18 1 T56 1 T57 2 T44 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 29 1 T40 2 T114 1 T45 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 16 1 T56 1 T133 1 T371 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 67 1 T58 1 T114 1 T46 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 56 1 T36 4 T41 1 T43 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 51 1 T36 1 T58 1 T45 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 16 1 T56 2 T41 3 T133 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 48 1 T36 1 T40 2 T42 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 15 1 T44 1 T312 1 T371 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 48 1 T40 2 T41 1 T45 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 18 1 T56 1 T41 1 T43 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 50 1 T36 1 T58 1 T42 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 27 1 T57 1 T41 1 T42 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 38 1 T36 1 T114 1 T148 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 13 1 T56 2 T41 1 T133 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 42 1 T40 1 T58 1 T114 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 9 1 T56 1 T57 1 T43 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 52 1 T36 1 T40 1 T58 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 25 1 T43 2 T44 1 T133 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 61 1 T36 1 T40 2 T58 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 46 1 T36 2 T57 1 T41 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 38 1 T40 1 T42 4 T114 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 27 1 T56 1 T57 3 T41 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 61 1 T58 1 T42 1 T45 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 50 1 T56 2 T41 2 T371 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 38 1 T56 1 T42 1 T114 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 36 1 T43 1 T44 1 T312 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 72 1 T40 1 T58 1 T114 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 65 1 T43 2 T118 13 T44 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 32 1 T58 1 T42 1 T114 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 28 1 T57 2 T133 1 T135 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 61 1 T58 1 T133 1 T286 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 67 1 T43 1 T44 1 T312 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 55 1 T114 1 T45 1 T302 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 60 1 T42 3 T43 1 T44 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 95 1 T40 3 T58 1 T45 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 121 1 T56 1 T57 3 T41 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T386 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 19 1 T133 5 T375 4 T373 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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