Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.73 98.73 98.03 100.00 93.59 98.96 99.42 88.34


Total tests in report: 912
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.29 46.29 65.01 65.01 47.91 47.91 82.99 82.99 4.49 4.49 68.17 68.17 54.05 54.05 1.44 1.44 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3437977347
70.37 24.08 86.70 21.68 75.32 27.41 86.42 3.42 69.23 64.74 88.24 20.07 82.95 28.90 3.76 2.32 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1055816941
74.96 4.58 92.31 5.62 81.97 6.65 89.61 3.20 69.23 0.00 93.68 5.43 85.07 2.12 12.82 9.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2561375910
79.37 4.41 94.51 2.20 87.84 5.87 92.47 2.85 75.64 6.41 95.38 1.70 88.92 3.85 20.83 8.01 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1622662435
81.39 2.02 94.94 0.43 88.80 0.96 92.69 0.23 75.64 0.00 95.38 0.00 89.21 0.29 33.09 12.27 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.948117626
83.25 1.85 96.53 1.59 91.18 2.38 93.15 0.46 75.64 0.00 96.86 1.48 89.88 0.67 39.50 6.41 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.4191498261
84.98 1.73 96.81 0.28 91.45 0.28 93.15 0.00 78.21 2.56 97.19 0.33 92.97 3.08 45.08 5.58 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1690116339
86.67 1.69 97.13 0.32 92.09 0.63 93.38 0.23 81.41 3.21 97.49 0.30 94.03 1.06 51.16 6.08 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.878674893
88.00 1.34 97.16 0.04 93.40 1.31 94.06 0.68 81.41 0.00 97.60 0.11 94.22 0.19 58.18 7.02 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1516372708
88.84 0.84 97.41 0.24 93.75 0.35 94.06 0.00 81.41 0.00 97.60 0.00 94.22 0.00 63.43 5.25 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4093615704
89.56 0.72 97.65 0.24 94.34 0.58 94.06 0.00 83.97 2.56 97.82 0.22 95.66 1.45 63.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1281902400
90.27 0.71 97.70 0.06 94.41 0.08 97.26 3.20 83.97 0.00 97.82 0.00 96.53 0.87 64.20 0.77 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1756673713
90.92 0.64 97.91 0.21 94.61 0.20 97.26 0.00 83.97 0.00 97.89 0.07 96.53 0.00 68.23 4.03 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.490448793
91.31 0.39 98.00 0.09 94.87 0.25 97.72 0.46 85.26 1.28 98.08 0.18 97.01 0.48 68.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1996740245
91.69 0.39 98.02 0.02 95.47 0.61 97.95 0.23 85.26 0.00 98.15 0.07 97.01 0.00 70.00 1.77 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.165515562
92.07 0.38 98.04 0.02 95.50 0.03 97.95 0.00 85.26 0.00 98.15 0.00 97.11 0.10 72.49 2.49 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2638888248
92.37 0.30 98.06 0.02 95.52 0.03 97.95 0.00 85.26 0.00 98.19 0.04 97.11 0.00 74.48 1.99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2372251089
92.66 0.29 98.10 0.04 95.52 0.00 97.95 0.00 87.18 1.92 98.26 0.07 97.11 0.00 74.48 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1830954243
92.94 0.29 98.10 0.00 95.58 0.05 99.54 1.60 87.18 0.00 98.26 0.00 97.21 0.10 74.75 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2538445851
93.22 0.28 98.17 0.07 95.63 0.05 99.54 0.00 87.82 0.64 98.30 0.04 97.30 0.10 75.80 1.05 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1423401970
93.45 0.22 98.21 0.04 96.03 0.40 99.77 0.23 88.46 0.64 98.34 0.04 97.40 0.10 75.91 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4213383130
93.63 0.19 98.21 0.00 96.06 0.03 99.77 0.00 88.46 0.00 98.34 0.00 97.40 0.00 77.18 1.27 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1848319554
93.81 0.18 98.21 0.00 96.16 0.10 99.77 0.00 88.46 0.00 98.34 0.00 97.98 0.58 77.79 0.61 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4059275953
93.99 0.17 98.32 0.11 96.21 0.05 99.77 0.00 88.46 0.00 98.48 0.15 97.98 0.00 78.67 0.88 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.2663178712
94.15 0.17 98.36 0.04 96.38 0.18 99.77 0.00 89.10 0.64 98.52 0.04 98.27 0.29 78.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2925937220
94.32 0.16 98.40 0.04 97.22 0.83 99.77 0.00 89.10 0.00 98.52 0.00 98.27 0.00 78.95 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2295710900
94.47 0.15 98.40 0.00 97.22 0.00 99.77 0.00 89.10 0.00 98.52 0.00 98.27 0.00 80.00 1.05 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4168590857
94.62 0.15 98.43 0.04 97.29 0.08 99.77 0.00 89.74 0.64 98.56 0.04 98.46 0.19 80.06 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3377275597
94.76 0.14 98.43 0.00 97.29 0.00 99.77 0.00 89.74 0.00 98.56 0.00 98.46 0.00 81.05 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3394638943
94.90 0.14 98.43 0.00 97.29 0.00 99.77 0.00 89.74 0.00 98.56 0.00 98.46 0.00 82.04 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1334568846
95.03 0.13 98.45 0.02 97.29 0.00 99.77 0.00 89.74 0.00 98.56 0.00 98.46 0.00 82.93 0.88 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1221243607
95.16 0.13 98.51 0.06 97.32 0.03 99.77 0.00 90.38 0.64 98.63 0.07 98.55 0.10 82.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.310921724
95.28 0.12 98.54 0.04 97.35 0.03 99.77 0.00 91.03 0.64 98.67 0.04 98.65 0.10 82.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3969921983
95.40 0.12 98.58 0.04 97.37 0.03 99.77 0.00 91.67 0.64 98.71 0.04 98.75 0.10 82.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1221508844
95.50 0.11 98.60 0.02 97.37 0.00 99.77 0.00 92.31 0.64 98.74 0.04 98.75 0.00 82.98 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3717859983
95.60 0.10 98.62 0.02 97.37 0.00 99.77 0.00 92.95 0.64 98.78 0.04 98.75 0.00 82.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3151409541
95.70 0.10 98.64 0.02 97.37 0.00 99.77 0.00 93.59 0.64 98.82 0.04 98.75 0.00 82.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.843211267
95.77 0.07 98.64 0.00 97.37 0.00 99.77 0.00 93.59 0.00 98.82 0.00 98.75 0.00 83.48 0.50 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.225743770
95.84 0.07 98.68 0.04 97.37 0.00 99.77 0.00 93.59 0.00 98.82 0.00 98.75 0.00 83.92 0.44 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3099063833
95.91 0.07 98.68 0.00 97.40 0.03 99.77 0.00 93.59 0.00 98.82 0.00 98.75 0.00 84.36 0.44 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3558041275
95.98 0.07 98.68 0.00 97.45 0.05 99.77 0.00 93.59 0.00 98.82 0.00 98.94 0.19 84.59 0.22 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3162068338
96.04 0.07 98.71 0.04 97.60 0.15 99.77 0.00 93.59 0.00 98.89 0.07 99.13 0.19 84.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3798467473
96.10 0.06 98.71 0.00 97.60 0.00 99.77 0.00 93.59 0.00 98.89 0.00 99.13 0.00 84.97 0.39 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2196413532
96.15 0.05 98.71 0.00 97.65 0.05 99.77 0.00 93.59 0.00 98.93 0.04 99.13 0.00 85.25 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1361991809
96.19 0.05 98.73 0.02 97.83 0.18 99.77 0.00 93.59 0.00 98.96 0.04 99.23 0.10 85.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.271734249
96.24 0.04 98.73 0.00 97.90 0.08 100.00 0.23 93.59 0.00 98.96 0.00 99.23 0.00 85.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1054596900
96.28 0.04 98.73 0.00 97.90 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.23 0.00 85.52 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3152600962
96.32 0.04 98.73 0.00 97.90 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.23 0.00 85.80 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1752892005
96.35 0.03 98.73 0.00 97.90 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.23 0.00 86.02 0.22 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2086480638
96.37 0.03 98.73 0.00 97.93 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.10 86.08 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3572789490
96.40 0.02 98.73 0.00 97.93 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.24 0.17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2824178058
96.42 0.02 98.73 0.00 97.93 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.41 0.17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1117046316
96.44 0.02 98.73 0.00 97.93 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.57 0.17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2586872666
96.46 0.02 98.73 0.00 97.95 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.69 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3313096274
96.48 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.80 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.3087612818
96.50 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.91 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.540276543
96.51 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.02 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1833505100
96.53 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.13 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3026028374
96.54 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.24 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2017734201
96.56 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.35 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2106799040
96.57 0.01 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.10 87.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3470164920
96.58 0.01 98.73 0.00 97.98 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.40 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3158276033
96.59 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.46 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3337017000
96.60 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.51 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1227646339
96.61 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.57 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1125084797
96.62 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.62 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.258286452
96.62 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.68 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.420663928
96.63 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.73 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3477362434
96.64 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.79 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3359019764
96.65 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.85 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1709824234
96.66 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.90 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2893042205
96.66 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.96 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1830683420
96.67 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.01 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.95823558
96.68 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.07 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3232927721
96.69 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.12 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2345417865
96.69 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.18 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2907219543
96.70 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.23 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3352996387
96.71 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.29 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3917592691
96.72 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.34 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1753599352
96.72 0.01 98.73 0.00 98.00 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.160692489
96.73 0.01 98.73 0.00 98.03 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2576841851

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2529415851
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1967216161
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1805823061
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3443276159
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3392419987
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1311440565
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3878315028
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3410818374
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2001966145
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2323290178
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2510506381
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2866022951
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.433935279
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.907478490
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.14461682
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.837589219
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.424346563
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.760325465
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4152358393
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.206059339
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.129788948
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1897441314
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2934989876
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4223054870
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3387292095
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1243072774
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2672600917
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2008252656
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1296853165
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1687804767
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2387777684
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.397114768
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2633458374
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1615546299
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.78275955
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1295728688
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3154967150
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3236068063
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1218527077
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2597203446
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.248217422
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1029333948
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.99834113
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.928543018
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2398183588
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1752358837
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2768073287
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3937089506
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.156702577
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.748125255
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3810621362
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2433563441
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.80239549
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3926392543
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.736531783
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2001086122
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.147680071
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3997744582
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3293685828
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.674483027
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1618462994
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.179908276
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.563851363
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2464524056
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1911999223
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2145633421
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2352480451
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.4118280842
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734806392
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2923425452
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3165270141
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2124601183
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1766054307
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.241690893
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2345478250
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3793692071
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.523449018
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1248860712
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1611651051
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1635591488
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2726224242
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.137335272
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.417537173
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1833874936
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.565374884
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2833651233
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.663220301
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1708111613
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3301940316
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1054476045
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1783503770
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1779447982
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2139275888
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1729489231
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3920400791
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1454004452
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3652941113
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3696205547
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2376131572
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.69973452
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.221556473
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3166822515
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1320192669
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2459367769
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.887341167
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.39103755
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2204324045
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1513101632
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.976363761
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3241871927
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1600873040
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2963722153
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1977883522
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1477364788
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1683694017
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1112195103
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.868406849
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1226379010
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1296019754
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1030026044
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1997139799
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4130219105
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4201384062
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1231130256
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3262008818
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2651234997
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1745412130
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2270966551
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2296433208
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2391064664
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2448288818
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3860385680
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.477085599
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.582199564
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.4095874556
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.996559329
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.599524675
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3881742844
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.688798864
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1871224992
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2117339485
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4139696596
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4076490511
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1543746778
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1899710791
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1118933898
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.729083504
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2470159666
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2223149890
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3026407427
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.61426326
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2862979694
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.221515189
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.652336806
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2988559115
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3109227423
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.374543691
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3481700424
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1166373108
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3254859585
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.435119047
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4191922681
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2849195903
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4287622457
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.618345918
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3433397198
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4060980187
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1347809874
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3081333766
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.800331218
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2320645123
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3290813777
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1423469546
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1463111667
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.223893169
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3728291495
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.36608026
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1211610832
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.968104313
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1218843862
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3919290341
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2144263382
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3503533907
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3612701595
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2934286974
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3405837408
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3220871711
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3359220605
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1139597197
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3921551774
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.4189542573
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2075594132
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2404351489
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3577881377
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.4136025685
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2157923113
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.944681798
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1603878780
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2895023770
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.761320929
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2355698345
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.3640841404
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.935095580
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.34290319
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.17791894
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.505599266
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1286271223
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.794129114
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3946821782
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2478181120
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3944899590
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3141493637
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3955501819
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1164065183
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1337836452
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3542118145
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2475140135
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1426367169
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.548943265
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.4147985831
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.956723605
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.585071196
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.410724810
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.2237916099
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3493442166
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.239891379
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2473014895
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2874147665
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.839836132
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.838015131
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2280072947
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1621123015
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1534478255
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1683697097
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.236157248
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.716622818
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.3760230693
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3325977085
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2421175470
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.528017338
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.397112135
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3610021704
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2266199866
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.2367209438
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.4265500253
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3407017073
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1375337150
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.950350987
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.4133394389
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1105737341
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.941752258
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3092802212
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3428030704
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2156448742
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3718317388
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2263187098
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1859835138
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2699536167
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1036086766
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3806168486
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.4249791581
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3105259000
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.847150658
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1314083648
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3054249929
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.327697498
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1050575447
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1229148940
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.932051602
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.532681083
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1324063853
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2689432442
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3786931441
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.98457290
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.1648312703
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.4055343723
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3655211814
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.830249098
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.1221165950
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2130112195
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2629402642
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2315701212
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3131766129
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.3453374464
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1116784746
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.831819714
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.257958152
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2033948333
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1591711229
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3597751623
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2009913938
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.249068952
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.183986107
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3142373111
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2596307620
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1487560116
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2726237848
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3588246892
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3970357944
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1630674090
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2587596097
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3099420214
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3472114859
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1418608200
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.922874064
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2481672062
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.195968032
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.2228144156
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.388459878
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2278666291
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2701487716
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.705410888
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2521196192
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2460767147
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.886856429
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3207574570
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3538650441
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.253223126
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.4002058078
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.681664942
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3803990704
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.850030828
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.952260694
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3274158632
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2069154196
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3232930113
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.929789542
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3792086778
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3161979395
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1627692655
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2348133788
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1351413667
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4227027126
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3070722290
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3587078516
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2283254736
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.129584332
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3969012752
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.958402720
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3826468969
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.2211002750
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.3352107901
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.699443571
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1337407024
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1617933044
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3330017647
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.680578227
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1707231064
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1335230218
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1040673604
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3904995514
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1942851694
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3556909238
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.204686439
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.3754108008
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.2453251996
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.35257687
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3681736803
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.4280642014
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2625135884
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2916555775
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3571151138
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2985034953
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2957639095
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2487388273
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2451436569
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.526441369
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2316021059
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.918176163
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.706066826
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3608744622
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3420346671
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1056492547
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3673164634
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2604273842
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.241204515
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.2309327956
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2760674762
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1671164569
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2099389894
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3225603929
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1271396620
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2126893736
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2425636863
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2407238854
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2315251135
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1158546426
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3202440917
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.1015341061
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.771313117
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4050575025
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1322153875
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.144004944
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4124150060
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.664691643
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3341738329
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3461917068
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.4177807539
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2090532944
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2001056290
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1813565280
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1564132150
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1979273202
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3219708279
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2757868067
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.4059521932
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.178896592
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.3411544721
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2524537046
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1887557434
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2853834141
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.418719087
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3348205518
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1729134213
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2817279883
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.2548206675
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1802529269
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.1694297028
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3988063739
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.823607765
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2925095162
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.1296096476
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3144346906
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.925765306
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1814195308
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1952346946
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2781529585
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.272347238
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1616269505
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3909981711
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1276143500
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2648215679
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1079974520
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.99057817
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.300371274
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.248381750
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.932859361
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2831710953
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.717835063
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2363916914
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.3721294442
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.3008062243
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1023681414
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1241957884
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.303288423
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1611875460
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4276063635
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.653730031
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3434112353
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.766928438
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3682696469
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.913304635
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1224392163
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3785760037
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1127151114
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.3105162946
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1229018354
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4287520213
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.308430173
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.844696270
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.654095748
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.29279534
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1192975772
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1729692336
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1104758986
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.4115519650
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.2681447120
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1396962090
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1431928450
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.183894687
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3632079774
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3087390349
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.2612769152
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4274364048
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1210658820
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3292523549
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.352731175
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.2201337322
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1909554313
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.3575200848
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.72215383
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.3046505754
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.830282409
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1365609780
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1035812095
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2623579755
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1118795167
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1559028181
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2023169366
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.537122431
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1031194343
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.544349696
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.490822921
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2359489487
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.258582984
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.1920727262
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.912305844
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1540986968
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.829858019
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.609821425
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.2320126789
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.761547742
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.333977464
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.957767634
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.406065962
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3709589446
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.3433400888
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3196334287
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1582506274
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3007811740
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3966786571
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.1876151460
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2937847383
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.402736531
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3078893127
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2406703668
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2820384133
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.687757558
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.2160265015
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.3741642389
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3565887054
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3539630908
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.632203048
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1470722929
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.987597010
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2572426072
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2160470789
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.1915768724
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.334664350
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2814857579
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3066422793
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.26607606
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2328471205
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.833586397
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.1772236836
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3062502780
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1757068731
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2494046673
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3638742943
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2143080284
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2268774490
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1642772548
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1808786965
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1381482495
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2686494648
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2360513548
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1558318474
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.503288887
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1225855737
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3145173702
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2502399251
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.111353328
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3780989996
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.358366495
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1802410677
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1643770638
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3103256101
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2377096212
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.317955647
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2815429353
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3576258158
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3947245712
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3766991926
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3097334973
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3950748111
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3355855507
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.414539077
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3414043578
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.1378610222
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3339074567
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.522548147
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2748226024
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1938770133
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2651538966
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1672717461
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1309089429
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1166637491
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2413453240
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3567230328
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.4251673620
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.33816476
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.2981234590
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.1468283404
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1365116896
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.7769657
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.1782608853
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3708672837
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.385341799
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3763438469
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2357162365
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2088079904
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1300727558
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.959653577
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3567025182
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2329472209
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2097813187
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.210152358
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1697889865
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.250739212
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.2250524634
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3141195118
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.789622561
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3768889884
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4067709417
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.2951283786
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1998148339
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1583740619
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1830422428
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3128403206
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1167123245
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.1937145924
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2644380267
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.4280602032
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2491336841
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.430095404
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2890504250
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.956957015
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2800835321
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.3436013914
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2365249324
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1977229966
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.914545155
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1422216929
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.3638673175
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1557565757
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.2567478424
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.4150876047
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3720211134
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.444544056
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3057635012
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1005597226
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2589600997
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1320693974
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.679915358
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3971619997
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3575358627
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2403111933
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.4067624843
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1936197353
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.875609904
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.3932606320
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3873935703
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.772106607
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1780194121
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2481762944
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1072940771
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.2258558515
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.772144301
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3538083687
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.259402085
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.336094763
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.205180603
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2936958628
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1741984392
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1390013006
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1442002518
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3835138603
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3152460214
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.791500842
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3631805255
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3343447091
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.2089954416
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2348406303
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3731231980
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.415092707
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.537576938
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.667598426
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4138635306
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2306578987
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2081286058
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.179733996
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4186632863
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3403517108
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2075909516
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3958031720
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3573204070
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2012585678
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.1201576049
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2589003081
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.31692348
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1508738112
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1571133900
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.403515346
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2493083299
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.1324782322
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1478929392
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.55347090
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.484545044
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2354183925
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1961005533
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3559276711
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.636730877
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.889361158
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3047062672
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1528815195
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3478382186
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1009302241
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3483535788
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.4236507741
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2949135336
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.11863641
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.1849654231
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2771518493
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3354746273
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.380915748
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3297500159
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1417734246
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1518378200
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3578633241
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1745982978
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4021762244
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.80700086
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2648428582
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3215329896
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4105780675
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.2242594819
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3129212991
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.4260691770
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.584941444
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.200598765
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.506496925
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2979960435
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2449790412
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3252134910
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3782809754
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3496778890
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.2402566826
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1037349759
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2193423198
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2440863906
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.750891580
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.948600911
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.849080395
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1871595582
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.737518140
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3051544529
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.664470401
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3146730103
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2584061802
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.67787329
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1503111530
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3751234151
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.665597301
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3672008798
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2680473688
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2996919150
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1785532320
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3988217300
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2895275807
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.843960613
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.645454155
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3552744482
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3509818100
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.165840117
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1009870154
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.1020038553
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3234932167
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3834425045
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1325790009
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4168790551
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.498204394
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.307476373
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2923675224
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.709046377
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4252593827
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3245246915
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3563305269
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.445328165
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3028556891
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.819493892
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.985489025
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3185239757
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2889490371
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.533892958
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3619695015
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.4147928641
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2961386490
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.464950505
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2797206996
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1984766234
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4170700643
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1367722065
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2247212307
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1132396618
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3725250497
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.671136864
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2420691189
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.668256089
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2362683374
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.202328585
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3965808260
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1875391022
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2652104097
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.693370836
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2191718409
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.211974963
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1827819654
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1463055965
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2966313814
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1758251201
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.2632918180
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.840760360
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3894315377
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1542299415
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1906045753
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2383818526
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1314905606
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1501557169
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.466791431
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2787470864
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3688495343
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.576212970
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2737786134
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2698539680
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.615522574
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1780661601
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4266866364
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1656033757
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.863489275
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1012127198
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.4006288806
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.401345176
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3752973520
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2369179319
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2042683253
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.71535567
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.913834261
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.993917890
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3262012945
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3850245748
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.659823302



Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4287622457 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:11 PM UTC 24 2997161916 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4060980187 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:11 PM UTC 24 2150106416 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.2663178712 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:12 PM UTC 24 2155099100 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3433397198 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:12 PM UTC 24 2527767695 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.36608026 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:12 PM UTC 24 2092659988 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1054596900 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2033541933 ps
T1 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2576841851 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 4327777204 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3437977347 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2534763485 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3538650441 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2128597399 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2278666291 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2309615360 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3337017000 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 3631797622 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2481672062 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:14 PM UTC 24 2020774401 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2561375910 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:14 PM UTC 24 2534278586 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3290813777 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:14 PM UTC 24 2439147994 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3377275597 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:15 PM UTC 24 4153098041 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2144263382 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:15 PM UTC 24 5968257002 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.388459878 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:15 PM UTC 24 2158963156 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.223893169 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:16 PM UTC 24 2622073926 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4276063635 Aug 28 08:01:12 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2193002735 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1224392163 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2480448065 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3207574570 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:30 PM UTC 24 22072283103 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.913304635 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2643526491 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1334568846 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2548673499 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.705410888 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:17 PM UTC 24 3398046235 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4191922681 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2313414408 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.4191498261 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2471396968 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.968104313 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2110785334 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3081333766 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2854385214 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3785760037 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2042641485 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3728291495 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2459846103 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.800331218 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:19 PM UTC 24 2013177490 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4213383130 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:27 PM UTC 24 6599009036 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3682696469 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:19 PM UTC 24 3153197832 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.435119047 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2403867266 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3763438469 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:27 PM UTC 24 2019511842 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.618345918 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2611904769 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.3105162946 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2110312579 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.303288423 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:20 PM UTC 24 3040896504 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2460767147 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2436014312 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3254859585 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:20 PM UTC 24 3773506412 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.886856429 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2156073954 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1227646339 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2511067970 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.4002058078 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:21 PM UTC 24 2834587448 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1241957884 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2024471700 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2097813187 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2478145070 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2329472209 Aug 28 08:01:18 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2629466746 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.165515562 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2531950758 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.849080395 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:32 PM UTC 24 2017983326 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3567025182 Aug 28 08:01:18 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2584020026 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.653730031 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:23 PM UTC 24 2314968222 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3919290341 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:23 PM UTC 24 13000203084 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2088079904 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:23 PM UTC 24 2241742921 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.250739212 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:24 PM UTC 24 2113705657 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.308430173 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:24 PM UTC 24 3026110538 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1996740245 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:24 PM UTC 24 4054130169 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2521196192 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:25 PM UTC 24 2612133412 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3146730103 Aug 28 08:01:21 PM UTC 24 Aug 28 08:01:25 PM UTC 24 2473515330 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1463111667 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:25 PM UTC 24 4104598785 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2584061802 Aug 28 08:01:21 PM UTC 24 Aug 28 08:01:25 PM UTC 24 2136767085 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1622662435 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:26 PM UTC 24 20972096531 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1503111530 Aug 28 08:01:21 PM UTC 24 Aug 28 08:01:26 PM UTC 24 2117035916 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3141195118 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:26 PM UTC 24 8312867099 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3834425045 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:26 PM UTC 24 2181327562 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.664470401 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:27 PM UTC 24 2650393037 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4287520213 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:28 PM UTC 24 11891492554 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2538445851 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:28 PM UTC 24 22068690805 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.225743770 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:28 PM UTC 24 2528882984 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1300727558 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:29 PM UTC 24 2276151853 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.210152358 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:29 PM UTC 24 2245346259 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.1020038553 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:29 PM UTC 24 2469708481 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.665597301 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:30 PM UTC 24 4240487887 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.165840117 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:31 PM UTC 24 2966331453 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.498204394 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:30 PM UTC 24 5035543651 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2478181120 Aug 28 08:01:48 PM UTC 24 Aug 28 08:02:24 PM UTC 24 2125019608 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.17791894 Aug 28 08:01:59 PM UTC 24 Aug 28 08:02:24 PM UTC 24 3101904457 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.766928438 Aug 28 08:01:14 PM UTC 24 Aug 28 08:01:31 PM UTC 24 3591300643 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3552744482 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:31 PM UTC 24 3421992448 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.789622561 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:32 PM UTC 24 8318019301 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.4147928641 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:32 PM UTC 24 2494372324 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1211610832 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:33 PM UTC 24 42259571167 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3509818100 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:33 PM UTC 24 4020080181 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3234932167 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:33 PM UTC 24 2190427030 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1009870154 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:34 PM UTC 24 2618042756 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.761320929 Aug 28 08:01:44 PM UTC 24 Aug 28 08:02:24 PM UTC 24 2139587943 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.737518140 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:34 PM UTC 24 2526986367 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2797206996 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:35 PM UTC 24 2117001986 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.67787329 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:35 PM UTC 24 2511958591 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1463055965 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:35 PM UTC 24 2678419412 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.840760360 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:35 PM UTC 24 2166106096 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1871595582 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:36 PM UTC 24 3162997305 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3751234151 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:36 PM UTC 24 11763822119 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.645454155 Aug 28 08:01:27 PM UTC 24 Aug 28 08:01:36 PM UTC 24 2008805310 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.540276543 Aug 28 08:01:43 PM UTC 24 Aug 28 08:02:24 PM UTC 24 13310414005 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1127151114 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:36 PM UTC 24 22106831235 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2357162365 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:37 PM UTC 24 3668724721 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.2632918180 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:37 PM UTC 24 2525914874 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1218843862 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:38 PM UTC 24 17850637170 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.464950505 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:39 PM UTC 24 2509534960 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3434112353 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:39 PM UTC 24 26355673694 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1906045753 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:39 PM UTC 24 5884263819 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2961386490 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:39 PM UTC 24 2084471666 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3894315377 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:39 PM UTC 24 9306191480 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3051544529 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:39 PM UTC 24 4910008298 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.533892958 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:40 PM UTC 24 3202002955 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1875391022 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:40 PM UTC 24 2040542484 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3619695015 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:40 PM UTC 24 2612716922 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4170700643 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:40 PM UTC 24 2782397386 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1756673713 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:40 PM UTC 24 8251510013 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1229018354 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:41 PM UTC 24 7711385975 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1055816941 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:41 PM UTC 24 33405644056 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.819493892 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:41 PM UTC 24 2010396838 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1758251201 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:42 PM UTC 24 2033627429 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.4006288806 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:42 PM UTC 24 2536236652 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1656033757 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:42 PM UTC 24 2630669703 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1361991809 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:43 PM UTC 24 3432161049 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4168790551 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:43 PM UTC 24 10370372515 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2966313814 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:44 PM UTC 24 2466779960 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.863489275 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:44 PM UTC 24 2468764611 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.401345176 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:44 PM UTC 24 2112512603 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2737786134 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:44 PM UTC 24 3803087715 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1780661601 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:44 PM UTC 24 3054339229 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1984766234 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:45 PM UTC 24 12428685116 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4266866364 Aug 28 08:01:38 PM UTC 24 Aug 28 08:01:45 PM UTC 24 5416759179 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1012127198 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:46 PM UTC 24 2038495749 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2889490371 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:46 PM UTC 24 3473085766 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1827819654 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:47 PM UTC 24 3815997955 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1542299415 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:48 PM UTC 24 4312195979 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3752973520 Aug 28 08:01:39 PM UTC 24 Aug 28 08:01:48 PM UTC 24 2333616774 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2369179319 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:49 PM UTC 24 5792302388 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4093615704 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:52 PM UTC 24 94572154262 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.2250524634 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:54 PM UTC 24 14662044035 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.253223126 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:58 PM UTC 24 15257822140 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.490448793 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:59 PM UTC 24 63437019750 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2191718409 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:59 PM UTC 24 27090795204 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.271734249 Aug 28 08:01:09 PM UTC 24 Aug 28 08:02:01 PM UTC 24 33641615421 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1367722065 Aug 28 08:01:29 PM UTC 24 Aug 28 08:02:01 PM UTC 24 519563357495 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.959653577 Aug 28 08:01:20 PM UTC 24 Aug 28 08:02:03 PM UTC 24 26095495215 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1697889865 Aug 28 08:01:20 PM UTC 24 Aug 28 08:02:07 PM UTC 24 42053168289 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.693370836 Aug 28 08:01:34 PM UTC 24 Aug 28 08:02:08 PM UTC 24 48407043222 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2698539680 Aug 28 08:01:38 PM UTC 24 Aug 28 08:02:11 PM UTC 24 43096746502 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.195968032 Aug 28 08:01:10 PM UTC 24 Aug 28 08:02:16 PM UTC 24 131020728419 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3946821782 Aug 28 08:01:49 PM UTC 24 Aug 28 08:02:22 PM UTC 24 2603912419 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3503533907 Aug 28 08:01:43 PM UTC 24 Aug 28 08:02:23 PM UTC 24 2044013143 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3359220605 Aug 28 08:01:40 PM UTC 24 Aug 28 08:02:23 PM UTC 24 2553434687 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.505599266 Aug 28 08:01:50 PM UTC 24 Aug 28 08:02:23 PM UTC 24 2640243822 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.4189542573 Aug 28 08:01:48 PM UTC 24 Aug 28 08:02:24 PM UTC 24 2030587731 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.794129114 Aug 28 08:01:49 PM UTC 24 Aug 28 08:02:24 PM UTC 24 2182924926 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3405837408 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:25 PM UTC 24 2515025301 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1603878780 Aug 28 08:01:44 PM UTC 24 Aug 28 08:02:25 PM UTC 24 2170726243 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2895023770 Aug 28 08:01:45 PM UTC 24 Aug 28 08:02:26 PM UTC 24 2556176848 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3612701595 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:26 PM UTC 24 3171723550 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3577881377 Aug 28 08:01:45 PM UTC 24 Aug 28 08:02:26 PM UTC 24 2881191600 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3220871711 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:27 PM UTC 24 2614732554 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3921551774 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:27 PM UTC 24 2765145931 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2934286974 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:27 PM UTC 24 3306341129 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1286271223 Aug 28 08:01:49 PM UTC 24 Aug 28 08:02:28 PM UTC 24 2442477414 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2157923113 Aug 28 08:01:45 PM UTC 24 Aug 28 08:02:29 PM UTC 24 2618732142 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.4136025685 Aug 28 08:01:46 PM UTC 24 Aug 28 08:02:29 PM UTC 24 3564817824 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3955501819 Aug 28 08:01:55 PM UTC 24 Aug 28 08:02:31 PM UTC 24 8406085262 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.944681798 Aug 28 08:01:44 PM UTC 24 Aug 28 08:02:31 PM UTC 24 2477349439 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2355698345 Aug 28 08:01:48 PM UTC 24 Aug 28 08:02:31 PM UTC 24 7468904145 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.34290319 Aug 28 08:01:53 PM UTC 24 Aug 28 08:02:31 PM UTC 24 3616363401 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1139597197 Aug 28 08:01:42 PM UTC 24 Aug 28 08:02:32 PM UTC 24 6998495817 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3470164920 Aug 28 08:01:46 PM UTC 24 Aug 28 08:02:32 PM UTC 24 4252084611 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.878674893 Aug 28 08:01:47 PM UTC 24 Aug 28 08:02:32 PM UTC 24 30297902983 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2075594132 Aug 28 08:01:46 PM UTC 24 Aug 28 08:02:34 PM UTC 24 3381958680 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2701487716 Aug 28 08:01:10 PM UTC 24 Aug 28 08:02:43 PM UTC 24 33329127959 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3185239757 Aug 28 08:01:31 PM UTC 24 Aug 28 08:02:46 PM UTC 24 24834547016 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.3087612818 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:52 PM UTC 24 99221455071 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.615522574 Aug 28 08:01:39 PM UTC 24 Aug 28 08:02:59 PM UTC 24 26582259837 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2638888248 Aug 28 08:01:20 PM UTC 24 Aug 28 08:03:03 PM UTC 24 143721989856 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2652104097 Aug 28 08:01:34 PM UTC 24 Aug 28 08:03:20 PM UTC 24 224206771894 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.948117626 Aug 28 08:01:47 PM UTC 24 Aug 28 08:03:21 PM UTC 24 99567675763 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2849195903 Aug 28 08:01:09 PM UTC 24 Aug 28 08:03:27 PM UTC 24 48115249213 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3944899590 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:18 PM UTC 24 12786951904 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.2228144156 Aug 28 08:01:10 PM UTC 24 Aug 28 08:03:44 PM UTC 24 57831494178 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1611875460 Aug 28 08:01:15 PM UTC 24 Aug 28 08:04:09 PM UTC 24 65118153483 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1221243607 Aug 28 08:01:59 PM UTC 24 Aug 28 08:04:25 PM UTC 24 96403060066 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1423469546 Aug 28 08:01:09 PM UTC 24 Aug 28 08:04:37 PM UTC 24 81437740594 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.2237916099 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:10 PM UTC 24 2136573301 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2320645123 Aug 28 08:01:09 PM UTC 24 Aug 28 08:05:18 PM UTC 24 98411607474 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1164065183 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:12 PM UTC 24 2040910901 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.3760230693 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2541627010 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.4147985831 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2621364649 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3325977085 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2122009333 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2473014895 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2995075823 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1375337150 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:13 PM UTC 24 4517330427 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.3640841404 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2016752532 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.236157248 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2493426058 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1621123015 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2719598271 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.548943265 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 5258877474 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3092802212 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2137977268 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3407017073 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2966137403 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1534478255 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2678289729 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2130112195 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2124460029 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1105737341 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2196208925 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.585071196 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2141518828 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3806168486 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 3870592816 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.4133394389 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 2474110920 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1426367169 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:15 PM UTC 24 5213947528 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3105259000 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 2636962330 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.327697498 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 2119734918 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3718317388 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 4269792342 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1337836452 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:16 PM UTC 24 3769292714 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3054249929 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:16 PM UTC 24 2516253502 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.716622818 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:16 PM UTC 24 2081174644 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1859835138 Aug 28 08:05:11 PM UTC 24 Aug 28 08:05:17 PM UTC 24 3269834336 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.956723605 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:17 PM UTC 24 2443853554 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2009913938 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2124551287 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.950350987 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:17 PM UTC 24 2611661479 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3610021704 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:17 PM UTC 24 2016223274 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.528017338 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:18 PM UTC 24 6805413746 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.1221165950 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2564596646 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2874147665 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2012172020 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.98457290 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2779063926 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.410724810 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2514282915 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.830249098 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2268491264 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.847150658 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2489581261 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3141493637 Aug 28 08:05:07 PM UTC 24 Aug 28 08:05:19 PM UTC 24 7458587938 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.4055343723 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2642059785 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1314083648 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2195331403 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1683697097 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:20 PM UTC 24 2609309474 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4227027126 Aug 28 08:05:24 PM UTC 24 Aug 28 08:05:35 PM UTC 24 5759910670 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.932051602 Aug 28 08:05:11 PM UTC 24 Aug 28 08:05:20 PM UTC 24 4398343666 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2263187098 Aug 28 08:05:13 PM UTC 24 Aug 28 08:05:20 PM UTC 24 2014154565 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2156448742 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:20 PM UTC 24 3088053365 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.4249791581 Aug 28 08:05:11 PM UTC 24 Aug 28 08:05:20 PM UTC 24 3474187628 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3655211814 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:20 PM UTC 24 2465880938 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.257958152 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2800183227 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1591711229 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2082839417 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.941752258 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2510285683 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.532681083 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2023839785 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1116784746 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:22 PM UTC 24 2983814986 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2629402642 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:23 PM UTC 24 8089895416 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.839836132 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:23 PM UTC 24 3674410775 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2033948333 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2476993803 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1487560116 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:24 PM UTC 24 4857090826 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.1648312703 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2914066234 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3099420214 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2128216944 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.239891379 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:24 PM UTC 24 20943315060 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2587596097 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2524021440 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.831819714 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:25 PM UTC 24 4049252779 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1627692655 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2128973384 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3588246892 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2623614185 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3161979395 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2526724235 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2726237848 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 3248893406 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2316021059 Aug 28 08:05:31 PM UTC 24 Aug 28 08:05:35 PM UTC 24 2126034626 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.249068952 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2027711676 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2348133788 Aug 28 08:05:25 PM UTC 24 Aug 28 08:05:36 PM UTC 24 11422438176 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1690116339 Aug 28 08:05:19 PM UTC 24 Aug 28 08:05:26 PM UTC 24 22729922053 ps