Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.73 98.73 98.03 100.00 93.59 98.96 99.42 88.34


Total tests in report: 912
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.29 46.29 65.01 65.01 47.91 47.91 82.99 82.99 4.49 4.49 68.17 68.17 54.05 54.05 1.44 1.44 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3437977347
70.37 24.08 86.70 21.68 75.32 27.41 86.42 3.42 69.23 64.74 88.24 20.07 82.95 28.90 3.76 2.32 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1055816941
74.96 4.58 92.31 5.62 81.97 6.65 89.61 3.20 69.23 0.00 93.68 5.43 85.07 2.12 12.82 9.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2561375910
79.37 4.41 94.51 2.20 87.84 5.87 92.47 2.85 75.64 6.41 95.38 1.70 88.92 3.85 20.83 8.01 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1622662435
81.39 2.02 94.94 0.43 88.80 0.96 92.69 0.23 75.64 0.00 95.38 0.00 89.21 0.29 33.09 12.27 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.948117626
83.25 1.85 96.53 1.59 91.18 2.38 93.15 0.46 75.64 0.00 96.86 1.48 89.88 0.67 39.50 6.41 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.4191498261
84.98 1.73 96.81 0.28 91.45 0.28 93.15 0.00 78.21 2.56 97.19 0.33 92.97 3.08 45.08 5.58 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1690116339
86.67 1.69 97.13 0.32 92.09 0.63 93.38 0.23 81.41 3.21 97.49 0.30 94.03 1.06 51.16 6.08 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.878674893
88.00 1.34 97.16 0.04 93.40 1.31 94.06 0.68 81.41 0.00 97.60 0.11 94.22 0.19 58.18 7.02 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1516372708
88.84 0.84 97.41 0.24 93.75 0.35 94.06 0.00 81.41 0.00 97.60 0.00 94.22 0.00 63.43 5.25 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4093615704
89.56 0.72 97.65 0.24 94.34 0.58 94.06 0.00 83.97 2.56 97.82 0.22 95.66 1.45 63.43 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1281902400
90.27 0.71 97.70 0.06 94.41 0.08 97.26 3.20 83.97 0.00 97.82 0.00 96.53 0.87 64.20 0.77 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1756673713
90.92 0.64 97.91 0.21 94.61 0.20 97.26 0.00 83.97 0.00 97.89 0.07 96.53 0.00 68.23 4.03 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.490448793
91.31 0.39 98.00 0.09 94.87 0.25 97.72 0.46 85.26 1.28 98.08 0.18 97.01 0.48 68.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1996740245
91.69 0.39 98.02 0.02 95.47 0.61 97.95 0.23 85.26 0.00 98.15 0.07 97.01 0.00 70.00 1.77 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.165515562
92.07 0.38 98.04 0.02 95.50 0.03 97.95 0.00 85.26 0.00 98.15 0.00 97.11 0.10 72.49 2.49 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2638888248
92.37 0.30 98.06 0.02 95.52 0.03 97.95 0.00 85.26 0.00 98.19 0.04 97.11 0.00 74.48 1.99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2372251089
92.66 0.29 98.10 0.04 95.52 0.00 97.95 0.00 87.18 1.92 98.26 0.07 97.11 0.00 74.48 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1830954243
92.94 0.29 98.10 0.00 95.58 0.05 99.54 1.60 87.18 0.00 98.26 0.00 97.21 0.10 74.75 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2538445851
93.22 0.28 98.17 0.07 95.63 0.05 99.54 0.00 87.82 0.64 98.30 0.04 97.30 0.10 75.80 1.05 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1423401970
93.45 0.22 98.21 0.04 96.03 0.40 99.77 0.23 88.46 0.64 98.34 0.04 97.40 0.10 75.91 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4213383130
93.63 0.19 98.21 0.00 96.06 0.03 99.77 0.00 88.46 0.00 98.34 0.00 97.40 0.00 77.18 1.27 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1848319554
93.81 0.18 98.21 0.00 96.16 0.10 99.77 0.00 88.46 0.00 98.34 0.00 97.98 0.58 77.79 0.61 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4059275953
93.99 0.17 98.32 0.11 96.21 0.05 99.77 0.00 88.46 0.00 98.48 0.15 97.98 0.00 78.67 0.88 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.2663178712
94.15 0.17 98.36 0.04 96.38 0.18 99.77 0.00 89.10 0.64 98.52 0.04 98.27 0.29 78.67 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2925937220
94.32 0.16 98.40 0.04 97.22 0.83 99.77 0.00 89.10 0.00 98.52 0.00 98.27 0.00 78.95 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2295710900
94.47 0.15 98.40 0.00 97.22 0.00 99.77 0.00 89.10 0.00 98.52 0.00 98.27 0.00 80.00 1.05 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4168590857
94.62 0.15 98.43 0.04 97.29 0.08 99.77 0.00 89.74 0.64 98.56 0.04 98.46 0.19 80.06 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3377275597
94.76 0.14 98.43 0.00 97.29 0.00 99.77 0.00 89.74 0.00 98.56 0.00 98.46 0.00 81.05 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3394638943
94.90 0.14 98.43 0.00 97.29 0.00 99.77 0.00 89.74 0.00 98.56 0.00 98.46 0.00 82.04 0.99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1334568846
95.03 0.13 98.45 0.02 97.29 0.00 99.77 0.00 89.74 0.00 98.56 0.00 98.46 0.00 82.93 0.88 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1221243607
95.16 0.13 98.51 0.06 97.32 0.03 99.77 0.00 90.38 0.64 98.63 0.07 98.55 0.10 82.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.310921724
95.28 0.12 98.54 0.04 97.35 0.03 99.77 0.00 91.03 0.64 98.67 0.04 98.65 0.10 82.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3969921983
95.40 0.12 98.58 0.04 97.37 0.03 99.77 0.00 91.67 0.64 98.71 0.04 98.75 0.10 82.93 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1221508844
95.50 0.11 98.60 0.02 97.37 0.00 99.77 0.00 92.31 0.64 98.74 0.04 98.75 0.00 82.98 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3717859983
95.60 0.10 98.62 0.02 97.37 0.00 99.77 0.00 92.95 0.64 98.78 0.04 98.75 0.00 82.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3151409541
95.70 0.10 98.64 0.02 97.37 0.00 99.77 0.00 93.59 0.64 98.82 0.04 98.75 0.00 82.98 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.843211267
95.77 0.07 98.64 0.00 97.37 0.00 99.77 0.00 93.59 0.00 98.82 0.00 98.75 0.00 83.48 0.50 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.225743770
95.84 0.07 98.68 0.04 97.37 0.00 99.77 0.00 93.59 0.00 98.82 0.00 98.75 0.00 83.92 0.44 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3099063833
95.91 0.07 98.68 0.00 97.40 0.03 99.77 0.00 93.59 0.00 98.82 0.00 98.75 0.00 84.36 0.44 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3558041275
95.98 0.07 98.68 0.00 97.45 0.05 99.77 0.00 93.59 0.00 98.82 0.00 98.94 0.19 84.59 0.22 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3162068338
96.04 0.07 98.71 0.04 97.60 0.15 99.77 0.00 93.59 0.00 98.89 0.07 99.13 0.19 84.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3798467473
96.10 0.06 98.71 0.00 97.60 0.00 99.77 0.00 93.59 0.00 98.89 0.00 99.13 0.00 84.97 0.39 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2196413532
96.15 0.05 98.71 0.00 97.65 0.05 99.77 0.00 93.59 0.00 98.93 0.04 99.13 0.00 85.25 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1361991809
96.19 0.05 98.73 0.02 97.83 0.18 99.77 0.00 93.59 0.00 98.96 0.04 99.23 0.10 85.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.271734249
96.24 0.04 98.73 0.00 97.90 0.08 100.00 0.23 93.59 0.00 98.96 0.00 99.23 0.00 85.25 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1054596900
96.28 0.04 98.73 0.00 97.90 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.23 0.00 85.52 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3152600962
96.32 0.04 98.73 0.00 97.90 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.23 0.00 85.80 0.28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1752892005
96.35 0.03 98.73 0.00 97.90 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.23 0.00 86.02 0.22 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2086480638
96.37 0.03 98.73 0.00 97.93 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.10 86.08 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3572789490
96.40 0.02 98.73 0.00 97.93 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.24 0.17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2824178058
96.42 0.02 98.73 0.00 97.93 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.41 0.17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1117046316
96.44 0.02 98.73 0.00 97.93 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.57 0.17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2586872666
96.46 0.02 98.73 0.00 97.95 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.69 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3313096274
96.48 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.80 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.3087612818
96.50 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 86.91 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.540276543
96.51 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.02 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1833505100
96.53 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.13 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3026028374
96.54 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.24 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2017734201
96.56 0.02 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.33 0.00 87.35 0.11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2106799040
96.57 0.01 98.73 0.00 97.95 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.10 87.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3470164920
96.58 0.01 98.73 0.00 97.98 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.40 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3158276033
96.59 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.46 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3337017000
96.60 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.51 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1227646339
96.61 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.57 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1125084797
96.62 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.62 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.258286452
96.62 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.68 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.420663928
96.63 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.73 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3477362434
96.64 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.79 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3359019764
96.65 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.85 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1709824234
96.66 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.90 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2893042205
96.66 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 87.96 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1830683420
96.67 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.01 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.95823558
96.68 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.07 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3232927721
96.69 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.12 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2345417865
96.69 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.18 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2907219543
96.70 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.23 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3352996387
96.71 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.29 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3917592691
96.72 0.01 98.73 0.00 97.98 0.00 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.34 0.06 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1753599352
96.72 0.01 98.73 0.00 98.00 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.160692489
96.73 0.01 98.73 0.00 98.03 0.03 100.00 0.00 93.59 0.00 98.96 0.00 99.42 0.00 88.34 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2576841851

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2529415851
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1967216161
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1805823061
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3443276159
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3392419987
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1311440565
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3878315028
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3410818374
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2001966145
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2323290178
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2510506381
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2866022951
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.433935279
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.907478490
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.14461682
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.837589219
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.424346563
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.760325465
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4152358393
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.206059339
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.129788948
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1897441314
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2934989876
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4223054870
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3387292095
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1243072774
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2672600917
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2008252656
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1296853165
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1687804767
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2387777684
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.397114768
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2633458374
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1615546299
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.78275955
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1295728688
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3154967150
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3236068063
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1218527077
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2597203446
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.248217422
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1029333948
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.99834113
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.928543018
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2398183588
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1752358837
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2768073287
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3937089506
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.156702577
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.748125255
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3810621362
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2433563441
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.80239549
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3926392543
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.736531783
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2001086122
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.147680071
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3997744582
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3293685828
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.674483027
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1618462994
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.179908276
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.563851363
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2464524056
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1911999223
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2145633421
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2352480451
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.4118280842
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734806392
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2923425452
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3165270141
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2124601183
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1766054307
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.241690893
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2345478250
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3793692071
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.523449018
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1248860712
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1611651051
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1635591488
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2726224242
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.137335272
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.417537173
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1833874936
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.565374884
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2833651233
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.663220301
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1708111613
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3301940316
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1054476045
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1783503770
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1779447982
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2139275888
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1729489231
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3920400791
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1454004452
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2376131572
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.69973452
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.221556473
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1320192669
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.39103755
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2204324045
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1513101632
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.976363761
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3241871927
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Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4287622457 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:11 PM UTC 24 2997161916 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4060980187 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:11 PM UTC 24 2150106416 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.2663178712 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:12 PM UTC 24 2155099100 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3433397198 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:12 PM UTC 24 2527767695 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.36608026 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:12 PM UTC 24 2092659988 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1054596900 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2033541933 ps
T1 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2576841851 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 4327777204 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3437977347 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2534763485 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3538650441 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2128597399 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2278666291 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 2309615360 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3337017000 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:13 PM UTC 24 3631797622 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2481672062 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:14 PM UTC 24 2020774401 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2561375910 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:14 PM UTC 24 2534278586 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3290813777 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:14 PM UTC 24 2439147994 ps
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T8 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2144263382 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:15 PM UTC 24 5968257002 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.388459878 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:15 PM UTC 24 2158963156 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.223893169 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:16 PM UTC 24 2622073926 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4276063635 Aug 28 08:01:12 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2193002735 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1224392163 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2480448065 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3207574570 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:30 PM UTC 24 22072283103 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.913304635 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2643526491 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1334568846 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:17 PM UTC 24 2548673499 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.705410888 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:17 PM UTC 24 3398046235 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4191922681 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2313414408 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.4191498261 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2471396968 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.968104313 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2110785334 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3081333766 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2854385214 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3785760037 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2042641485 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3728291495 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:18 PM UTC 24 2459846103 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.800331218 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:19 PM UTC 24 2013177490 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4213383130 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:27 PM UTC 24 6599009036 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3682696469 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:19 PM UTC 24 3153197832 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.435119047 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2403867266 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3763438469 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:27 PM UTC 24 2019511842 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.618345918 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2611904769 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.3105162946 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2110312579 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.303288423 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:20 PM UTC 24 3040896504 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2460767147 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2436014312 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3254859585 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:20 PM UTC 24 3773506412 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.886856429 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2156073954 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1227646339 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:20 PM UTC 24 2511067970 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.4002058078 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:21 PM UTC 24 2834587448 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1241957884 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2024471700 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2097813187 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2478145070 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2329472209 Aug 28 08:01:18 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2629466746 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.165515562 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2531950758 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.849080395 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:32 PM UTC 24 2017983326 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3567025182 Aug 28 08:01:18 PM UTC 24 Aug 28 08:01:22 PM UTC 24 2584020026 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.653730031 Aug 28 08:01:13 PM UTC 24 Aug 28 08:01:23 PM UTC 24 2314968222 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3919290341 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:23 PM UTC 24 13000203084 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2088079904 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:23 PM UTC 24 2241742921 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.250739212 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:24 PM UTC 24 2113705657 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.308430173 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:24 PM UTC 24 3026110538 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1996740245 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:24 PM UTC 24 4054130169 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2521196192 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:25 PM UTC 24 2612133412 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3146730103 Aug 28 08:01:21 PM UTC 24 Aug 28 08:01:25 PM UTC 24 2473515330 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1463111667 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:25 PM UTC 24 4104598785 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2584061802 Aug 28 08:01:21 PM UTC 24 Aug 28 08:01:25 PM UTC 24 2136767085 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1622662435 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:26 PM UTC 24 20972096531 ps
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T262 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.664470401 Aug 28 08:01:23 PM UTC 24 Aug 28 08:01:27 PM UTC 24 2650393037 ps
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T337 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.225743770 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:28 PM UTC 24 2528882984 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1300727558 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:29 PM UTC 24 2276151853 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.210152358 Aug 28 08:01:17 PM UTC 24 Aug 28 08:01:29 PM UTC 24 2245346259 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.1020038553 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:29 PM UTC 24 2469708481 ps
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T268 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.766928438 Aug 28 08:01:14 PM UTC 24 Aug 28 08:01:31 PM UTC 24 3591300643 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3552744482 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:31 PM UTC 24 3421992448 ps
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T176 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3234932167 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:33 PM UTC 24 2190427030 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1009870154 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:34 PM UTC 24 2618042756 ps
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T449 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1463055965 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:35 PM UTC 24 2678419412 ps
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T72 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3894315377 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:39 PM UTC 24 9306191480 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3051544529 Aug 28 08:01:24 PM UTC 24 Aug 28 08:01:39 PM UTC 24 4910008298 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.533892958 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:40 PM UTC 24 3202002955 ps
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T74 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3619695015 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:40 PM UTC 24 2612716922 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4170700643 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:40 PM UTC 24 2782397386 ps
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T243 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1229018354 Aug 28 08:01:15 PM UTC 24 Aug 28 08:01:41 PM UTC 24 7711385975 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1055816941 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:41 PM UTC 24 33405644056 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.819493892 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:41 PM UTC 24 2010396838 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1758251201 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:42 PM UTC 24 2033627429 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.4006288806 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:42 PM UTC 24 2536236652 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1656033757 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:42 PM UTC 24 2630669703 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1361991809 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:43 PM UTC 24 3432161049 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4168790551 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:43 PM UTC 24 10370372515 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2966313814 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:44 PM UTC 24 2466779960 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.863489275 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:44 PM UTC 24 2468764611 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.401345176 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:44 PM UTC 24 2112512603 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2737786134 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:44 PM UTC 24 3803087715 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1780661601 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:44 PM UTC 24 3054339229 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1984766234 Aug 28 08:01:32 PM UTC 24 Aug 28 08:01:45 PM UTC 24 12428685116 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4266866364 Aug 28 08:01:38 PM UTC 24 Aug 28 08:01:45 PM UTC 24 5416759179 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1012127198 Aug 28 08:01:36 PM UTC 24 Aug 28 08:01:46 PM UTC 24 2038495749 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2889490371 Aug 28 08:01:29 PM UTC 24 Aug 28 08:01:46 PM UTC 24 3473085766 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1827819654 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:47 PM UTC 24 3815997955 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1542299415 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:48 PM UTC 24 4312195979 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3752973520 Aug 28 08:01:39 PM UTC 24 Aug 28 08:01:48 PM UTC 24 2333616774 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2369179319 Aug 28 08:01:37 PM UTC 24 Aug 28 08:01:49 PM UTC 24 5792302388 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4093615704 Aug 28 08:01:26 PM UTC 24 Aug 28 08:01:52 PM UTC 24 94572154262 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.2250524634 Aug 28 08:01:20 PM UTC 24 Aug 28 08:01:54 PM UTC 24 14662044035 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.253223126 Aug 28 08:01:10 PM UTC 24 Aug 28 08:01:58 PM UTC 24 15257822140 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.490448793 Aug 28 08:01:09 PM UTC 24 Aug 28 08:01:59 PM UTC 24 63437019750 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2191718409 Aug 28 08:01:34 PM UTC 24 Aug 28 08:01:59 PM UTC 24 27090795204 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.271734249 Aug 28 08:01:09 PM UTC 24 Aug 28 08:02:01 PM UTC 24 33641615421 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1367722065 Aug 28 08:01:29 PM UTC 24 Aug 28 08:02:01 PM UTC 24 519563357495 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.959653577 Aug 28 08:01:20 PM UTC 24 Aug 28 08:02:03 PM UTC 24 26095495215 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1697889865 Aug 28 08:01:20 PM UTC 24 Aug 28 08:02:07 PM UTC 24 42053168289 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.693370836 Aug 28 08:01:34 PM UTC 24 Aug 28 08:02:08 PM UTC 24 48407043222 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2698539680 Aug 28 08:01:38 PM UTC 24 Aug 28 08:02:11 PM UTC 24 43096746502 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.195968032 Aug 28 08:01:10 PM UTC 24 Aug 28 08:02:16 PM UTC 24 131020728419 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3946821782 Aug 28 08:01:49 PM UTC 24 Aug 28 08:02:22 PM UTC 24 2603912419 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3503533907 Aug 28 08:01:43 PM UTC 24 Aug 28 08:02:23 PM UTC 24 2044013143 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3359220605 Aug 28 08:01:40 PM UTC 24 Aug 28 08:02:23 PM UTC 24 2553434687 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.505599266 Aug 28 08:01:50 PM UTC 24 Aug 28 08:02:23 PM UTC 24 2640243822 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.4189542573 Aug 28 08:01:48 PM UTC 24 Aug 28 08:02:24 PM UTC 24 2030587731 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.794129114 Aug 28 08:01:49 PM UTC 24 Aug 28 08:02:24 PM UTC 24 2182924926 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3405837408 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:25 PM UTC 24 2515025301 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1603878780 Aug 28 08:01:44 PM UTC 24 Aug 28 08:02:25 PM UTC 24 2170726243 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2895023770 Aug 28 08:01:45 PM UTC 24 Aug 28 08:02:26 PM UTC 24 2556176848 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3612701595 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:26 PM UTC 24 3171723550 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3577881377 Aug 28 08:01:45 PM UTC 24 Aug 28 08:02:26 PM UTC 24 2881191600 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3220871711 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:27 PM UTC 24 2614732554 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3921551774 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:27 PM UTC 24 2765145931 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2934286974 Aug 28 08:01:41 PM UTC 24 Aug 28 08:02:27 PM UTC 24 3306341129 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1286271223 Aug 28 08:01:49 PM UTC 24 Aug 28 08:02:28 PM UTC 24 2442477414 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2157923113 Aug 28 08:01:45 PM UTC 24 Aug 28 08:02:29 PM UTC 24 2618732142 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.4136025685 Aug 28 08:01:46 PM UTC 24 Aug 28 08:02:29 PM UTC 24 3564817824 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3955501819 Aug 28 08:01:55 PM UTC 24 Aug 28 08:02:31 PM UTC 24 8406085262 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.944681798 Aug 28 08:01:44 PM UTC 24 Aug 28 08:02:31 PM UTC 24 2477349439 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2355698345 Aug 28 08:01:48 PM UTC 24 Aug 28 08:02:31 PM UTC 24 7468904145 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.34290319 Aug 28 08:01:53 PM UTC 24 Aug 28 08:02:31 PM UTC 24 3616363401 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1139597197 Aug 28 08:01:42 PM UTC 24 Aug 28 08:02:32 PM UTC 24 6998495817 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3470164920 Aug 28 08:01:46 PM UTC 24 Aug 28 08:02:32 PM UTC 24 4252084611 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.878674893 Aug 28 08:01:47 PM UTC 24 Aug 28 08:02:32 PM UTC 24 30297902983 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2075594132 Aug 28 08:01:46 PM UTC 24 Aug 28 08:02:34 PM UTC 24 3381958680 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2701487716 Aug 28 08:01:10 PM UTC 24 Aug 28 08:02:43 PM UTC 24 33329127959 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3185239757 Aug 28 08:01:31 PM UTC 24 Aug 28 08:02:46 PM UTC 24 24834547016 ps
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T105 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.615522574 Aug 28 08:01:39 PM UTC 24 Aug 28 08:02:59 PM UTC 24 26582259837 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2638888248 Aug 28 08:01:20 PM UTC 24 Aug 28 08:03:03 PM UTC 24 143721989856 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2652104097 Aug 28 08:01:34 PM UTC 24 Aug 28 08:03:20 PM UTC 24 224206771894 ps
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T463 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3944899590 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:18 PM UTC 24 12786951904 ps
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T118 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1423469546 Aug 28 08:01:09 PM UTC 24 Aug 28 08:04:37 PM UTC 24 81437740594 ps
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T303 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1164065183 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:12 PM UTC 24 2040910901 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.3760230693 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2541627010 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.4147985831 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:13 PM UTC 24 2621364649 ps
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T467 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3092802212 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2137977268 ps
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T469 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2130112195 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2124460029 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1105737341 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2196208925 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.585071196 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:14 PM UTC 24 2141518828 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3806168486 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 3870592816 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.4133394389 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 2474110920 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1426367169 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:15 PM UTC 24 5213947528 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3105259000 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 2636962330 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.327697498 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 2119734918 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3718317388 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:15 PM UTC 24 4269792342 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1337836452 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:16 PM UTC 24 3769292714 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3054249929 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:16 PM UTC 24 2516253502 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.716622818 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:16 PM UTC 24 2081174644 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1859835138 Aug 28 08:05:11 PM UTC 24 Aug 28 08:05:17 PM UTC 24 3269834336 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.956723605 Aug 28 08:05:08 PM UTC 24 Aug 28 08:05:17 PM UTC 24 2443853554 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2009913938 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2124551287 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.950350987 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:17 PM UTC 24 2611661479 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3610021704 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:17 PM UTC 24 2016223274 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.528017338 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:18 PM UTC 24 6805413746 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.1221165950 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2564596646 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2874147665 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2012172020 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.98457290 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2779063926 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.410724810 Aug 28 08:05:09 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2514282915 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.830249098 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:18 PM UTC 24 2268491264 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.847150658 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2489581261 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3141493637 Aug 28 08:05:07 PM UTC 24 Aug 28 08:05:19 PM UTC 24 7458587938 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.4055343723 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2642059785 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1314083648 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:19 PM UTC 24 2195331403 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1683697097 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:20 PM UTC 24 2609309474 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4227027126 Aug 28 08:05:24 PM UTC 24 Aug 28 08:05:35 PM UTC 24 5759910670 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.932051602 Aug 28 08:05:11 PM UTC 24 Aug 28 08:05:20 PM UTC 24 4398343666 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2263187098 Aug 28 08:05:13 PM UTC 24 Aug 28 08:05:20 PM UTC 24 2014154565 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2156448742 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:20 PM UTC 24 3088053365 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.4249791581 Aug 28 08:05:11 PM UTC 24 Aug 28 08:05:20 PM UTC 24 3474187628 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3655211814 Aug 28 08:05:15 PM UTC 24 Aug 28 08:05:20 PM UTC 24 2465880938 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.257958152 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2800183227 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1591711229 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2082839417 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.941752258 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2510285683 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.532681083 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:21 PM UTC 24 2023839785 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1116784746 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:22 PM UTC 24 2983814986 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2629402642 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:23 PM UTC 24 8089895416 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.839836132 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:23 PM UTC 24 3674410775 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2033948333 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2476993803 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1487560116 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:24 PM UTC 24 4857090826 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.1648312703 Aug 28 08:05:16 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2914066234 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3099420214 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2128216944 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.239891379 Aug 28 08:05:10 PM UTC 24 Aug 28 08:05:24 PM UTC 24 20943315060 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2587596097 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:24 PM UTC 24 2524021440 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.831819714 Aug 28 08:05:18 PM UTC 24 Aug 28 08:05:25 PM UTC 24 4049252779 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1627692655 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2128973384 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3588246892 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2623614185 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3161979395 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2526724235 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2726237848 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 3248893406 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2316021059 Aug 28 08:05:31 PM UTC 24 Aug 28 08:05:35 PM UTC 24 2126034626 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.249068952 Aug 28 08:05:21 PM UTC 24 Aug 28 08:05:25 PM UTC 24 2027711676 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2348133788 Aug 28 08:05:25 PM UTC 24 Aug 28 08:05:36 PM UTC 24 11422438176 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1690116339 Aug 28 08:05:19 PM UTC 24 Aug 28 08:05:26 PM UTC 24 22729922053 ps
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