Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1393

1

T35

21

T46

6

T59

6

auto[1]

1609

1

T46

16

T59

7

T49

1

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2526

1

T35

21

T46

20

T59

13

auto[1]

476

1

T46

2

T57

11

T103

2

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2869

1

T35

21

T46

22

T59

13

auto[1]

133

1

T43

1

T44

7

T45

4

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2829

1

T35

21

T46

20

T59

13

auto[1]

173

1

T46

2

T47

3

T48

1

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2841

1

T35

21

T46

22

T59

13

auto[1]

161

1

T49

1

T47

4

T48

3

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1816

1

T35

12

T46

3

T59

4

auto[1]

1186

1

T35

9

T46

19

T59

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1264

1

T35

10

T46

9

T59

9

auto[1]

1738

1

T35

11

T46

13

T59

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1211

1

T35

21

T46

7

T49

1

auto[1]

1791

1

T46

15

T59

13

T49

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T35

5

T46

11

T59

3

auto[1]

1810

1

T35

16

T46

11

T59

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1292

1

T35

9

T46

7

T59

2

auto[1]

1710

1

T35

12

T46

15

T59

11

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

58

1

T35

3

T58

2

T97

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T118

1

T234

2

T346

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T43

1

T245

1

T169

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T46

1

T233

2

T347

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T35

1

T58

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T57

1

T47

1

T233

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T48

1

T348

1

T251

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T118

1

T120

1

T233

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T35

4

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T57

2

T103

1

T120

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T97

1

T43

1

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T118

1

T233

1

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T35

2

T48

3

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T47

1

T48

1

T234

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

26

1

T48

1

T45

2

T121

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T47

1

T48

5

T233

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T59

1

T43

1

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T46

1

T57

1

T103

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T59

1

T119

1

T228

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T169

3

T349

3

T126

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T245

1

T45

1

T228

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T57

1

T346

2

T126

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T57

1

T245

1

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T46

2

T103

1

T120

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T119

1

T245

1

T169

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T103

1

T118

1

T169

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T119

1

T121

1

T123

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T46

1

T103

2

T118

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T46

1

T121

1

T169

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T59

1

T118

1

T120

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

64

1

T245

1

T169

1

T229

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

42

1

T46

2

T59

6

T47

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

39

1

T35

1

T44

1

T119

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T234

1

T252

1

T255

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T103

1

T97

1

T119

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T46

2

T57

1

T103

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T48

1

T43

1

T119

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T46

1

T169

1

T349

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T245

2

T169

1

T221

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T57

1

T103

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T35

1

T97

2

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T120

1

T349

1

T125

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T245

1

T169

2

T350

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T57

1

T120

1

T234

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T48

2

T119

2

T169

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

38

1

T35

9

T46

1

T57

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39

1

T43

1

T119

1

T45

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T46

1

T43

3

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T58

2

T43

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

27

1

T57

1

T103

1

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T48

2

T97

3

T221

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T46

1

T48

1

T118

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T59

1

T58

9

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T47

1

T125

1

T346

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T44

1

T45

8

T122

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T46

3

T103

1

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T43

1

T119

1

T245

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T57

1

T47

1

T118

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T118

1

T43

1

T119

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

60

1

T57

2

T118

2

T97

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

83

1

T59

1

T44

2

T119

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

80

1

T46

1

T59

2

T103

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

245

1

T46

2

T49

1

T47

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

24

1

T57

1

T103

1

T118

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T57

1

T118

1

T347

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T118

1

T351

1

T352

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T47

1

T233

1

T347

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

14

1

T47

1

T347

3

T346

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T47

1

T353

1

T354

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T46

1

T103

1

T43

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T233

1

T347

1

T232

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T48

2

T254

1

T355

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T347

1

T346

1

T351

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T57

1

T169

1

T353

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T47

1

T253

1

T356

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T347

1

T126

1

T254

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T233

1

T169

1

T347

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T233

1

T346

1

T351

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T356

1

T357

1

T358

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T118

1

T347

1

T356

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T346

1

T252

1

T351

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T347

2

T352

1

T359

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T47

1

T254

1

T353

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T57

1

T347

1

T351

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T360

3

T361

1

T362

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T233

1

T355

2

T363

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T169

1

T234

1

T351

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T47

1

T118

1

T233

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T347

1

T356

1

T363

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T57

1

T363

1

T364

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T57

1

T169

1

T126

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T234

1

T365

1

T254

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T365

1

T358

1

T352

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T346

1

T351

1

T364

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T46

1

T346

1

T351

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

107

1

T57

6

T103

1

T233

6

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T35

3

T58

2

T97

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T57

1

T118

2

T234

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T43

1

T245

1

T169

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T46

1

T118

1

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T35

1

T58

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T57

1

T47

2

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T48

1

T366

1

T348

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T47

1

T118

1

T120

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T35

4

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T57

2

T103

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T97

1

T43

1

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T46

1

T103

1

T118

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

43

1

T35

2

T48

3

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T47

1

T48

1

T233

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32

1

T48

1

T45

2

T121

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T47

1

T48

7

T233

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T59

1

T43

1

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T46

1

T57

1

T103

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

35

1

T59

1

T119

1

T228

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T57

1

T169

4

T349

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T44

1

T245

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T57

1

T47

1

T346

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T57

1

T44

1

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T46

2

T103

1

T120

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T119

1

T245

1

T169

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T103

1

T118

1

T233

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T119

1

T121

1

T350

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T46

1

T103

2

T118

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T46

1

T121

1

T169

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T59

1

T118

1

T120

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

70

1

T245

1

T169

1

T229

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T46

2

T59

6

T47

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

38

1

T35

1

T44

1

T119

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T234

1

T346

1

T252

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T103

1

T97

1

T119

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T46

2

T57

1

T103

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T48

1

T43

1

T119

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T46

1

T47

1

T169

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T245

2

T169

1

T221

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T57

2

T103

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T35

1

T97

2

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T120

1

T349

1

T125

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T245

1

T169

3

T350

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T57

1

T120

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T48

2

T119

2

T169

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

51

1

T35

9

T46

1

T57

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

35

1

T43

1

T44

2

T119

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T46

1

T47

1

T118

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T58

2

T43

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T57

1

T103

1

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T48

2

T97

3

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T46

1

T57

1

T48

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T59

1

T58

9

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T57

1

T47

1

T169

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T44

2

T45

8

T122

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T46

3

T103

1

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T43

1

T119

1

T245

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

64

1

T57

1

T47

1

T118

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

63

1

T118

1

T43

1

T119

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

65

1

T57

2

T118

2

T97

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

88

1

T59

1

T44

2

T119

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

88

1

T46

2

T59

2

T103

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

165

1

T46

2

T49

1

T47

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

122

1

T57

7

T103

2

T118

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2

1

T367

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T43

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T362

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T233

3

T347

2

T368

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	24	72	75.00	24
Automatically Generated Cross Bins	96	24	72	75.00	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[0]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T35

3

T58

2

T97

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T57

1

T118

2

T234

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T43

1

T245

1

T169

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T46

1

T118

1

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T35

1

T58

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T57

1

T47

2

T233

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T48

1

T366

1

T348

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T47

1

T118

1

T120

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T35

4

T49

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T57

2

T103

1

T47

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T97

1

T43

1

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T46

1

T103

1

T118

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T35

2

T48

3

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T47

1

T48

1

T233

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T48

1

T45

2

T121

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

47

1

T47

1

T48

7

T233

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T59

1

T43

1

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T46

1

T57

1

T103

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T59

1

T119

1

T228

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T57

1

T169

4

T349

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T44

1

T245

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T57

1

T47

1

T346

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T57

1

T44

1

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T46

2

T103

1

T120

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T119

1

T245

1

T169

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T103

1

T118

1

T233

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T119

1

T121

1

T350

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T46

1

T103

2

T118

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T46

1

T121

1

T169

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T59

1

T118

1

T120

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

68

1

T245

1

T169

1

T229

9

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

48

1

T46

2

T59

6

T47

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T35

1

T44

1

T119

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T234

1

T346

1

T252

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T103

1

T97

1

T119

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T46

2

T57

1

T103

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T48

1

T43

1

T119

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T46

1

T47

1

T169

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T245

2

T169

1

T221

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T57

2

T103

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T35

1

T97

2

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T120

1

T349

1

T125

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T245

1

T169

3

T350

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T57

1

T120

1

T233

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T48

2

T119

2

T169

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

50

1

T35

9

T46

1

T57

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

42

1

T44

2

T119

1

T45

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

58

1

T46

1

T47

1

T118

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T58

2

T43

1

T119

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T57

1

T103

1

T120

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T48

1

T97

3

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T46

1

T57

1

T48

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

69

1

T59

1

T58

9

T44

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T57

1

T47

1

T169

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T44

2

T45

8

T122

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T46

3

T103

1

T47

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T43

1

T119

1

T245

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

63

1

T57

1

T47

1

T118

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T118

1

T43

1

T119

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

65

1

T57

2

T118

2

T97

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

77

1

T59

1

T44

2

T119

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

88

1

T46

2

T59

2

T103

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

148

1

T49

1

T47

4

T118

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

119

1

T57

7

T103

2

T118

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T354

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T43

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T369

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T370

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T360

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T371

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T372

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T346

1

T351

1

T355

5

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded