Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.97 99.09 97.45 100.00 92.31 99.37 98.84 91.76


Total tests in report: 914
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.60 46.60 63.84 63.84 49.43 49.43 86.76 86.76 0.00 0.00 68.24 68.24 49.52 49.52 8.42 8.42 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2497922982
69.00 22.40 85.28 21.44 76.56 27.13 92.24 5.48 53.21 53.21 87.69 19.45 76.11 26.59 11.94 3.52 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1529982222
73.89 4.89 90.02 4.74 80.96 4.40 93.26 1.03 66.67 13.46 91.39 3.70 81.98 5.88 12.97 1.03 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2990889785
77.76 3.87 91.60 1.59 83.57 2.60 93.95 0.68 74.36 7.69 92.68 1.29 85.55 3.56 22.61 9.64 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1731587939
80.79 3.03 95.56 3.96 90.87 7.31 96.00 2.05 75.00 0.64 96.56 3.88 88.73 3.18 22.79 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2317464512
82.75 1.96 96.53 0.97 91.76 0.88 96.58 0.57 80.77 5.77 97.34 0.78 91.04 2.31 25.21 2.42 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1049627720
84.49 1.74 97.01 0.49 92.34 0.58 96.58 0.00 82.69 1.92 97.56 0.22 91.91 0.87 33.33 8.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.576102866
86.18 1.69 97.09 0.07 92.57 0.23 96.80 0.23 82.69 0.00 97.67 0.11 91.91 0.00 44.55 11.21 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3492680001
87.46 1.28 97.35 0.26 93.20 0.63 96.80 0.00 82.69 0.00 97.67 0.00 93.55 1.64 50.97 6.42 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3226965131
88.67 1.21 97.37 0.02 93.98 0.78 97.49 0.68 82.69 0.00 97.71 0.04 93.55 0.00 57.94 6.97 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1910522455
89.65 0.98 97.91 0.54 94.49 0.51 97.49 0.00 86.54 3.85 98.11 0.41 94.89 1.35 58.12 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.4062041519
90.45 0.80 97.91 0.00 94.49 0.00 97.49 0.00 86.54 0.00 98.11 0.00 94.89 0.00 63.70 5.58 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.4159536809
91.16 0.72 98.13 0.22 94.69 0.20 97.95 0.46 88.46 1.92 98.30 0.18 95.76 0.87 64.85 1.15 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4044066306
91.70 0.54 98.17 0.04 94.69 0.00 97.95 0.00 88.46 0.00 98.34 0.04 95.76 0.00 68.55 3.70 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1213741876
92.18 0.48 98.17 0.00 94.69 0.00 97.95 0.00 88.46 0.00 98.34 0.00 95.76 0.00 71.88 3.33 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.4170491344
92.60 0.42 98.30 0.13 94.87 0.18 97.95 0.00 88.46 0.00 98.34 0.00 95.76 0.00 74.55 2.67 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.991022364
92.96 0.35 98.30 0.00 94.87 0.00 97.95 0.00 88.46 0.00 98.34 0.00 95.76 0.00 77.03 2.48 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3328730293
93.29 0.34 98.40 0.09 95.25 0.38 97.95 0.00 89.74 1.28 98.45 0.11 96.24 0.48 77.03 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2118072513
93.60 0.31 98.41 0.02 95.27 0.03 97.95 0.00 89.74 0.00 98.48 0.04 96.34 0.10 79.03 2.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.320752235
93.91 0.30 98.41 0.00 95.32 0.05 99.54 1.60 89.74 0.00 98.48 0.00 96.44 0.10 79.39 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2795636286
94.18 0.27 98.41 0.00 95.42 0.10 99.54 0.00 89.74 0.00 98.52 0.04 97.59 1.16 80.00 0.61 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3037070532
94.44 0.26 98.47 0.06 95.93 0.51 99.54 0.00 89.74 0.00 98.60 0.07 98.17 0.58 80.61 0.61 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.139618887
94.67 0.23 98.51 0.04 95.93 0.00 99.54 0.00 89.74 0.00 98.60 0.00 98.17 0.00 82.18 1.58 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.357551294
94.86 0.19 98.53 0.02 95.98 0.05 99.77 0.23 89.74 0.00 98.60 0.00 98.17 0.00 83.21 1.03 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2419839136
95.02 0.16 98.66 0.13 96.01 0.03 99.77 0.00 90.38 0.64 98.82 0.22 98.27 0.10 83.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3826930936
95.17 0.16 98.66 0.00 96.03 0.03 99.77 0.00 90.38 0.00 98.82 0.00 98.36 0.10 84.18 0.97 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.297099620
95.31 0.14 98.69 0.04 96.03 0.00 99.77 0.00 90.38 0.00 98.82 0.00 98.36 0.00 85.09 0.91 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3967930800
95.44 0.13 98.73 0.04 96.06 0.03 99.77 0.00 91.03 0.64 98.85 0.04 98.46 0.10 85.15 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3670095962
95.56 0.13 98.77 0.04 96.08 0.03 99.77 0.00 91.67 0.64 98.89 0.04 98.55 0.10 85.21 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3607294567
95.68 0.12 98.81 0.04 96.11 0.03 99.77 0.00 92.31 0.64 98.93 0.04 98.65 0.10 85.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.4263280727
95.79 0.11 98.81 0.00 96.76 0.66 99.77 0.00 92.31 0.00 98.93 0.00 98.65 0.00 85.33 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2320018177
95.89 0.10 98.84 0.04 96.86 0.10 99.77 0.00 92.31 0.00 99.00 0.07 98.75 0.10 85.70 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3586877702
95.97 0.08 98.84 0.00 96.86 0.00 99.77 0.00 92.31 0.00 99.00 0.00 98.75 0.00 86.24 0.55 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3694545867
96.05 0.08 98.84 0.00 96.86 0.00 99.77 0.00 92.31 0.00 99.00 0.00 98.75 0.00 86.79 0.55 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.904106563
96.11 0.06 98.84 0.00 96.86 0.00 99.77 0.00 92.31 0.00 99.00 0.00 98.75 0.00 87.21 0.42 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1848455358
96.16 0.05 98.84 0.00 96.86 0.00 99.77 0.00 92.31 0.00 99.00 0.00 98.75 0.00 87.58 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.242435688
96.21 0.05 98.84 0.00 96.86 0.00 99.77 0.00 92.31 0.00 99.00 0.00 98.75 0.00 87.94 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.17737045
96.26 0.05 98.84 0.00 96.86 0.00 99.77 0.00 92.31 0.00 99.00 0.00 98.75 0.00 88.30 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.4206154928
96.31 0.05 98.90 0.06 96.94 0.08 100.00 0.23 92.31 0.00 99.00 0.00 98.75 0.00 88.30 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3655907376
96.37 0.05 98.92 0.02 96.94 0.00 100.00 0.00 92.31 0.00 99.04 0.04 98.75 0.00 88.61 0.30 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3226847189
96.41 0.04 98.92 0.00 97.24 0.30 100.00 0.00 92.31 0.00 99.04 0.00 98.75 0.00 88.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3767374912
96.45 0.04 98.92 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.75 0.00 88.91 0.30 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3839984669
96.50 0.04 98.92 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.75 0.00 89.21 0.30 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.298560840
96.53 0.03 98.92 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.04 0.00 98.75 0.00 89.45 0.24 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.3086488106
96.56 0.03 98.94 0.02 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.04 98.75 0.00 89.64 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.3448791674
96.59 0.03 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 89.82 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2636650217
96.62 0.03 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.00 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3453044873
96.64 0.03 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.18 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4200392607
96.66 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.30 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1635135397
96.68 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.42 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1355133278
96.69 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.55 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.802659576
96.71 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.67 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.375558762
96.73 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.79 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3941008443
96.75 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 90.91 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.144636051
96.76 0.02 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.75 0.00 91.03 0.12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1040579955
96.78 0.01 98.94 0.00 97.24 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.10 91.03 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.422284037
96.79 0.01 98.94 0.00 97.32 0.08 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.03 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.11535085
96.80 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.09 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1230675792
96.81 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.15 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3564574299
96.81 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.21 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2668340917
96.82 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.27 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.662523333
96.83 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.33 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4071149631
96.84 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.39 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2922334527
96.85 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.45 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3443922571
96.86 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.52 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.4132383745
96.87 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.58 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4294951485
96.87 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.64 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.445896340
96.88 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.70 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2559718301
96.89 0.01 98.94 0.00 97.32 0.00 100.00 0.00 92.31 0.00 99.08 0.00 98.84 0.00 91.76 0.06 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3270300826
96.90 0.01 98.96 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.11 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3577671458
96.91 0.01 98.97 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.15 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.3709734707
96.92 0.01 98.99 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.19 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3658461227
96.92 0.01 99.01 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.22 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1188846040
96.93 0.01 99.03 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.26 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2637326788
96.94 0.01 99.05 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.30 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.3125051555
96.95 0.01 99.07 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.33 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2010194837
96.96 0.01 99.09 0.02 97.32 0.00 100.00 0.00 92.31 0.00 99.37 0.04 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1052064694
96.96 0.01 99.09 0.00 97.37 0.05 100.00 0.00 92.31 0.00 99.37 0.00 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.204355765
96.97 0.01 99.09 0.00 97.42 0.05 100.00 0.00 92.31 0.00 99.37 0.00 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3179527061
96.97 0.01 99.09 0.00 97.45 0.03 100.00 0.00 92.31 0.00 99.37 0.00 98.84 0.00 91.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2363976234

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3165372247
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3906856971
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4022557622
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.235962511
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1414290865
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2787820088
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2613886524
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1844110794
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.185417804
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2496147234
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2668946752
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1786616469
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.200202957
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3226767588
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1846811340
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1028038954
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2732616933
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4132033860
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1898896358
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2343183638
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.388942964
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.979494092
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2140127258
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1167086697
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.247455776
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.370636726
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1542340489
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.249730616
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2558524185
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3455605303
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.34269475
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.441030774
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3571141605
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.325898603
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1707862553
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2768041623
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2779435509
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2304092016
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3459285212
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2940865093
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1327579631
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1374281973
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3718764099
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1901775412
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1930356483
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2075392738
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1845681913
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2766889338
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2373747580
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1750934829
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2438938636
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2228733141
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.492406863
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1549885364
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2483336853
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.384753208
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2026054958
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3581984209
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1842199565
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2800533853
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1916160102
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.990330620
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3937425821
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2624386103
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.63426676
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2634665774
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1653283084
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2088443670
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2876951275
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1002450567
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.189170376
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.131574951
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.144339327
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3519718352
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3772753873
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1879021744
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2382147368
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.381846820
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3553155279
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1262072291
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1732220862
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.457536448
/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3000924419
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/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1394446593
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/workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.785230439
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Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2497922982 Sep 01 09:03:47 AM UTC 24 Sep 01 09:03:54 AM UTC 24 2486966982 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.850878291 Sep 01 09:03:49 AM UTC 24 Sep 01 09:03:54 AM UTC 24 2078383410 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.850521665 Sep 01 09:03:47 AM UTC 24 Sep 01 09:03:55 AM UTC 24 2116285099 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.4220553572 Sep 01 09:03:51 AM UTC 24 Sep 01 09:03:56 AM UTC 24 3785543353 ps
T1 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.895143608 Sep 01 09:03:48 AM UTC 24 Sep 01 09:03:57 AM UTC 24 2547158031 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.3708454903 Sep 01 09:03:52 AM UTC 24 Sep 01 09:03:57 AM UTC 24 2124115409 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4027941339 Sep 01 09:03:47 AM UTC 24 Sep 01 09:03:57 AM UTC 24 2217267046 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2810895530 Sep 01 09:03:49 AM UTC 24 Sep 01 09:03:57 AM UTC 24 2511908177 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2990889785 Sep 01 09:03:50 AM UTC 24 Sep 01 09:03:58 AM UTC 24 3276966716 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2477370308 Sep 01 09:03:55 AM UTC 24 Sep 01 09:04:00 AM UTC 24 2377360387 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2817929378 Sep 01 09:03:49 AM UTC 24 Sep 01 09:04:00 AM UTC 24 2612397750 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.4222294685 Sep 01 09:03:54 AM UTC 24 Sep 01 09:04:00 AM UTC 24 2394706056 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1230675792 Sep 01 09:03:51 AM UTC 24 Sep 01 09:04:00 AM UTC 24 10805327833 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3655907376 Sep 01 09:03:52 AM UTC 24 Sep 01 09:04:01 AM UTC 24 2012252145 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.2674642946 Sep 01 09:03:52 AM UTC 24 Sep 01 09:04:01 AM UTC 24 2443528470 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.242435688 Sep 01 09:03:56 AM UTC 24 Sep 01 09:04:01 AM UTC 24 2622436148 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.4292895047 Sep 01 09:03:57 AM UTC 24 Sep 01 09:04:02 AM UTC 24 3556181830 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.4278775047 Sep 01 09:03:55 AM UTC 24 Sep 01 09:04:02 AM UTC 24 2033098725 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2983159066 Sep 01 09:04:00 AM UTC 24 Sep 01 09:04:03 AM UTC 24 2526863406 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.1048089304 Sep 01 09:04:19 AM UTC 24 Sep 01 09:04:22 AM UTC 24 2955007542 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2419839136 Sep 01 09:03:55 AM UTC 24 Sep 01 09:04:04 AM UTC 24 2515064396 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.1386634984 Sep 01 09:04:00 AM UTC 24 Sep 01 09:04:04 AM UTC 24 2021801027 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2579843514 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:05 AM UTC 24 2446600371 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.4185895754 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:05 AM UTC 24 2934310673 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.2773150311 Sep 01 09:04:00 AM UTC 24 Sep 01 09:04:06 AM UTC 24 2121893043 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2018460761 Sep 01 09:03:56 AM UTC 24 Sep 01 09:04:07 AM UTC 24 3023170974 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1534290631 Sep 01 09:03:56 AM UTC 24 Sep 01 09:04:08 AM UTC 24 3766491777 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.861196401 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:08 AM UTC 24 2610364892 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2317464512 Sep 01 09:03:58 AM UTC 24 Sep 01 09:04:08 AM UTC 24 7056388313 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2147274821 Sep 01 09:04:03 AM UTC 24 Sep 01 09:04:09 AM UTC 24 17611781520 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1279104550 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:10 AM UTC 24 2524768265 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.379369907 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:10 AM UTC 24 2197724797 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2039449507 Sep 01 09:04:04 AM UTC 24 Sep 01 09:04:10 AM UTC 24 2017857564 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.1374182267 Sep 01 09:04:06 AM UTC 24 Sep 01 09:04:11 AM UTC 24 2266090868 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1832977223 Sep 01 09:04:05 AM UTC 24 Sep 01 09:04:11 AM UTC 24 2478121422 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2616950382 Sep 01 09:03:57 AM UTC 24 Sep 01 09:04:11 AM UTC 24 100309685566 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3146308350 Sep 01 09:04:05 AM UTC 24 Sep 01 09:04:12 AM UTC 24 2211388571 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.58171578 Sep 01 09:03:58 AM UTC 24 Sep 01 09:04:13 AM UTC 24 3007172114 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3492680001 Sep 01 09:04:03 AM UTC 24 Sep 01 09:04:13 AM UTC 24 15323611120 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.4062041519 Sep 01 09:04:03 AM UTC 24 Sep 01 09:04:13 AM UTC 24 3135637793 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2758794989 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:15 AM UTC 24 2511348656 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2230303217 Sep 01 09:04:04 AM UTC 24 Sep 01 09:04:15 AM UTC 24 2112142934 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.384949228 Sep 01 09:04:11 AM UTC 24 Sep 01 09:04:15 AM UTC 24 2026251183 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.4263280727 Sep 01 09:04:09 AM UTC 24 Sep 01 09:04:15 AM UTC 24 3933656696 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2712463018 Sep 01 09:04:05 AM UTC 24 Sep 01 09:04:15 AM UTC 24 2517874109 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2405288573 Sep 01 09:04:12 AM UTC 24 Sep 01 09:04:16 AM UTC 24 2426849163 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2968842332 Sep 01 09:04:07 AM UTC 24 Sep 01 09:04:17 AM UTC 24 2610356108 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1245088515 Sep 01 09:04:10 AM UTC 24 Sep 01 09:04:17 AM UTC 24 7127492637 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.4139272812 Sep 01 09:04:12 AM UTC 24 Sep 01 09:04:17 AM UTC 24 2632166768 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3935104154 Sep 01 09:04:08 AM UTC 24 Sep 01 09:04:18 AM UTC 24 8160871270 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3238974506 Sep 01 09:04:08 AM UTC 24 Sep 01 09:04:18 AM UTC 24 3239973746 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.813871312 Sep 01 09:04:13 AM UTC 24 Sep 01 09:04:18 AM UTC 24 4238819159 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1121167458 Sep 01 09:04:12 AM UTC 24 Sep 01 09:04:19 AM UTC 24 4731373780 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3777845851 Sep 01 09:04:14 AM UTC 24 Sep 01 09:04:19 AM UTC 24 3282920564 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.4098176573 Sep 01 09:04:06 AM UTC 24 Sep 01 09:04:20 AM UTC 24 2511454856 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2141291186 Sep 01 09:04:11 AM UTC 24 Sep 01 09:04:20 AM UTC 24 2111467203 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.567799824 Sep 01 09:04:12 AM UTC 24 Sep 01 09:04:20 AM UTC 24 2163727563 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1201501614 Sep 01 09:04:13 AM UTC 24 Sep 01 09:04:20 AM UTC 24 3138783750 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.533220106 Sep 01 09:04:01 AM UTC 24 Sep 01 09:04:20 AM UTC 24 3132317668 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.1463951199 Sep 01 09:04:16 AM UTC 24 Sep 01 09:04:21 AM UTC 24 2043989144 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1430131996 Sep 01 09:04:12 AM UTC 24 Sep 01 09:04:22 AM UTC 24 2330466211 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1529982222 Sep 01 09:03:58 AM UTC 24 Sep 01 09:04:22 AM UTC 24 29533911759 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.3470001047 Sep 01 09:04:11 AM UTC 24 Sep 01 09:04:22 AM UTC 24 2462661954 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2475311495 Sep 01 09:04:18 AM UTC 24 Sep 01 09:04:22 AM UTC 24 2626248938 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.330551335 Sep 01 09:04:18 AM UTC 24 Sep 01 09:04:22 AM UTC 24 2204484670 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2722316418 Sep 01 09:04:19 AM UTC 24 Sep 01 09:04:23 AM UTC 24 7727629222 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1773268913 Sep 01 09:03:58 AM UTC 24 Sep 01 09:04:23 AM UTC 24 123737536270 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2869199196 Sep 01 09:04:18 AM UTC 24 Sep 01 09:04:24 AM UTC 24 2515893325 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.11535085 Sep 01 09:03:51 AM UTC 24 Sep 01 09:04:24 AM UTC 24 33852754251 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.904106563 Sep 01 09:04:22 AM UTC 24 Sep 01 09:04:24 AM UTC 24 2539832137 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.2126209996 Sep 01 09:04:21 AM UTC 24 Sep 01 09:04:25 AM UTC 24 2119395082 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.144636051 Sep 01 09:04:12 AM UTC 24 Sep 01 09:04:25 AM UTC 24 2511633621 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3188076872 Sep 01 09:04:17 AM UTC 24 Sep 01 09:04:25 AM UTC 24 2109015769 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2442771144 Sep 01 09:04:22 AM UTC 24 Sep 01 09:04:25 AM UTC 24 2457065551 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.2329745231 Sep 01 09:04:22 AM UTC 24 Sep 01 09:04:26 AM UTC 24 2269879242 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2032040815 Sep 01 09:04:23 AM UTC 24 Sep 01 09:04:26 AM UTC 24 3308499906 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.3381392465 Sep 01 09:04:26 AM UTC 24 Sep 01 09:04:29 AM UTC 24 2523726835 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.4281164810 Sep 01 09:04:26 AM UTC 24 Sep 01 09:04:29 AM UTC 24 2035354994 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4247924979 Sep 01 09:04:23 AM UTC 24 Sep 01 09:04:29 AM UTC 24 4480080959 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.239912946 Sep 01 09:04:23 AM UTC 24 Sep 01 09:04:29 AM UTC 24 2621004879 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.981132466 Sep 01 09:04:08 AM UTC 24 Sep 01 09:04:29 AM UTC 24 4453354267 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.1671057086 Sep 01 09:04:18 AM UTC 24 Sep 01 09:04:30 AM UTC 24 2449347112 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4122011910 Sep 01 09:04:15 AM UTC 24 Sep 01 09:04:30 AM UTC 24 30551138097 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3386316749 Sep 01 09:04:23 AM UTC 24 Sep 01 09:04:30 AM UTC 24 3516372071 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.923671265 Sep 01 09:04:20 AM UTC 24 Sep 01 09:04:30 AM UTC 24 10904635194 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.305918867 Sep 01 09:04:26 AM UTC 24 Sep 01 09:04:30 AM UTC 24 2538313650 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3668972846 Sep 01 09:04:26 AM UTC 24 Sep 01 09:04:30 AM UTC 24 3933613926 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1675170672 Sep 01 09:04:20 AM UTC 24 Sep 01 09:04:30 AM UTC 24 2015950990 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2674742319 Sep 01 09:04:26 AM UTC 24 Sep 01 09:04:33 AM UTC 24 3446094041 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2125925051 Sep 01 09:04:31 AM UTC 24 Sep 01 09:04:33 AM UTC 24 2689608001 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.192505778 Sep 01 09:04:19 AM UTC 24 Sep 01 09:04:33 AM UTC 24 2849034039 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4243460099 Sep 01 09:04:10 AM UTC 24 Sep 01 09:04:34 AM UTC 24 6291740786 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1696453259 Sep 01 09:04:31 AM UTC 24 Sep 01 09:04:35 AM UTC 24 2219239430 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.2696485002 Sep 01 09:04:30 AM UTC 24 Sep 01 09:04:35 AM UTC 24 2129395778 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.3636982952 Sep 01 09:04:31 AM UTC 24 Sep 01 09:04:35 AM UTC 24 2523532362 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.2340275335 Sep 01 09:04:24 AM UTC 24 Sep 01 09:04:36 AM UTC 24 2009861756 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.4094745011 Sep 01 09:04:30 AM UTC 24 Sep 01 09:04:37 AM UTC 24 2021993638 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1106839717 Sep 01 09:04:25 AM UTC 24 Sep 01 09:04:37 AM UTC 24 2111864590 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1937716598 Sep 01 09:04:29 AM UTC 24 Sep 01 09:04:38 AM UTC 24 14057366841 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1052064694 Sep 01 09:04:34 AM UTC 24 Sep 01 09:04:38 AM UTC 24 3651685545 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2795636286 Sep 01 09:04:04 AM UTC 24 Sep 01 09:04:38 AM UTC 24 22019931374 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3615734572 Sep 01 09:04:26 AM UTC 24 Sep 01 09:04:39 AM UTC 24 2610759753 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.356977639 Sep 01 09:04:36 AM UTC 24 Sep 01 09:04:39 AM UTC 24 2539016313 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.505284580 Sep 01 09:04:36 AM UTC 24 Sep 01 09:04:40 AM UTC 24 2037046612 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.2001162978 Sep 01 09:04:38 AM UTC 24 Sep 01 09:04:41 AM UTC 24 2291228812 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.976717804 Sep 01 09:04:31 AM UTC 24 Sep 01 09:04:42 AM UTC 24 2434860544 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.4056985267 Sep 01 09:04:32 AM UTC 24 Sep 01 09:04:43 AM UTC 24 4017191254 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1531426810 Sep 01 09:04:39 AM UTC 24 Sep 01 09:04:44 AM UTC 24 3400659299 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.872392082 Sep 01 09:04:10 AM UTC 24 Sep 01 09:04:44 AM UTC 24 42090013369 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2691937022 Sep 01 09:04:39 AM UTC 24 Sep 01 09:04:44 AM UTC 24 8708383729 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2816026847 Sep 01 09:03:57 AM UTC 24 Sep 01 09:04:45 AM UTC 24 121025994855 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4079168441 Sep 01 09:04:32 AM UTC 24 Sep 01 09:04:46 AM UTC 24 4087592091 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.2049432171 Sep 01 09:04:42 AM UTC 24 Sep 01 09:04:47 AM UTC 24 2134086349 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.4170491344 Sep 01 09:04:20 AM UTC 24 Sep 01 09:04:47 AM UTC 24 8627518108 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.2873260001 Sep 01 09:04:39 AM UTC 24 Sep 01 09:04:47 AM UTC 24 2516572331 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.1139925501 Sep 01 09:04:36 AM UTC 24 Sep 01 09:04:48 AM UTC 24 2107244557 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2071712724 Sep 01 09:04:45 AM UTC 24 Sep 01 09:04:48 AM UTC 24 2065763582 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3375766842 Sep 01 09:04:39 AM UTC 24 Sep 01 09:04:49 AM UTC 24 3686061108 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.896828309 Sep 01 09:04:40 AM UTC 24 Sep 01 09:04:51 AM UTC 24 4155896413 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.883668229 Sep 01 09:04:41 AM UTC 24 Sep 01 09:04:51 AM UTC 24 2014883482 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.942898239 Sep 01 09:04:29 AM UTC 24 Sep 01 09:04:51 AM UTC 24 8254920970 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3037070532 Sep 01 09:04:35 AM UTC 24 Sep 01 09:04:51 AM UTC 24 17088417945 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.439053837 Sep 01 09:04:45 AM UTC 24 Sep 01 09:04:52 AM UTC 24 2519221052 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1049627720 Sep 01 09:04:24 AM UTC 24 Sep 01 09:04:52 AM UTC 24 14746301804 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3615472004 Sep 01 09:04:47 AM UTC 24 Sep 01 09:04:52 AM UTC 24 3271491722 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.438112782 Sep 01 09:04:39 AM UTC 24 Sep 01 09:04:54 AM UTC 24 2614857626 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3750630210 Sep 01 09:04:48 AM UTC 24 Sep 01 09:04:54 AM UTC 24 3006415960 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.2696758041 Sep 01 09:04:40 AM UTC 24 Sep 01 09:04:55 AM UTC 24 6074709074 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1116054695 Sep 01 09:04:46 AM UTC 24 Sep 01 09:04:56 AM UTC 24 2613382043 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.1908985943 Sep 01 09:04:35 AM UTC 24 Sep 01 09:04:56 AM UTC 24 11807236136 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3577671458 Sep 01 09:04:47 AM UTC 24 Sep 01 09:04:56 AM UTC 24 8458264207 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3389871017 Sep 01 09:04:20 AM UTC 24 Sep 01 09:04:57 AM UTC 24 70388434957 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3028721969 Sep 01 09:04:53 AM UTC 24 Sep 01 09:04:57 AM UTC 24 2626471967 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.3086488106 Sep 01 09:04:49 AM UTC 24 Sep 01 09:04:57 AM UTC 24 10587985678 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.4042019879 Sep 01 09:04:51 AM UTC 24 Sep 01 09:04:58 AM UTC 24 2116357915 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.4216095756 Sep 01 09:04:53 AM UTC 24 Sep 01 09:04:58 AM UTC 24 2522233217 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.3330820998 Sep 01 09:04:44 AM UTC 24 Sep 01 09:04:58 AM UTC 24 2478441573 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.821742381 Sep 01 09:04:50 AM UTC 24 Sep 01 09:04:59 AM UTC 24 2015110841 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.2948729293 Sep 01 09:04:51 AM UTC 24 Sep 01 09:04:59 AM UTC 24 2452336806 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1731587939 Sep 01 09:04:49 AM UTC 24 Sep 01 09:05:02 AM UTC 24 40707663728 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.50432658 Sep 01 09:04:58 AM UTC 24 Sep 01 09:05:02 AM UTC 24 2039009847 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3226847189 Sep 01 09:03:50 AM UTC 24 Sep 01 09:05:03 AM UTC 24 91607092775 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4044066306 Sep 01 09:04:24 AM UTC 24 Sep 01 09:05:03 AM UTC 24 2609034399810 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3056604447 Sep 01 09:05:00 AM UTC 24 Sep 01 09:05:03 AM UTC 24 2639338537 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.285642205 Sep 01 09:04:54 AM UTC 24 Sep 01 09:05:03 AM UTC 24 3197664163 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.375880965 Sep 01 09:04:58 AM UTC 24 Sep 01 09:05:09 AM UTC 24 2110821460 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.230093637 Sep 01 09:04:55 AM UTC 24 Sep 01 09:05:03 AM UTC 24 3112563937 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.684120876 Sep 01 09:05:01 AM UTC 24 Sep 01 09:05:04 AM UTC 24 3306373767 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1980697862 Sep 01 09:04:52 AM UTC 24 Sep 01 09:05:04 AM UTC 24 2101159599 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.2717261444 Sep 01 09:04:58 AM UTC 24 Sep 01 09:05:05 AM UTC 24 2220432949 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1402911606 Sep 01 09:04:58 AM UTC 24 Sep 01 09:05:06 AM UTC 24 2478045830 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3099620982 Sep 01 09:05:41 AM UTC 24 Sep 01 09:05:52 AM UTC 24 3885316505 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.1052981468 Sep 01 09:04:59 AM UTC 24 Sep 01 09:05:06 AM UTC 24 2518593913 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1298412840 Sep 01 09:05:00 AM UTC 24 Sep 01 09:05:06 AM UTC 24 3848022131 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2698667132 Sep 01 09:04:19 AM UTC 24 Sep 01 09:05:09 AM UTC 24 30228123376 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1718252177 Sep 01 09:05:04 AM UTC 24 Sep 01 09:05:09 AM UTC 24 2017691654 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.344708481 Sep 01 09:05:05 AM UTC 24 Sep 01 09:05:10 AM UTC 24 2122299986 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3922651736 Sep 01 09:05:07 AM UTC 24 Sep 01 09:05:10 AM UTC 24 4672899438 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2721841074 Sep 01 09:04:46 AM UTC 24 Sep 01 09:05:10 AM UTC 24 4646792508 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3253034482 Sep 01 09:05:07 AM UTC 24 Sep 01 09:05:11 AM UTC 24 2627645096 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.3709734707 Sep 01 09:04:56 AM UTC 24 Sep 01 09:05:12 AM UTC 24 2753639869 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2968345242 Sep 01 09:05:07 AM UTC 24 Sep 01 09:05:12 AM UTC 24 2525815984 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.4206154928 Sep 01 09:04:41 AM UTC 24 Sep 01 09:05:16 AM UTC 24 6526085365 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1188846040 Sep 01 09:05:11 AM UTC 24 Sep 01 09:05:16 AM UTC 24 3841018907 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1476153394 Sep 01 09:05:12 AM UTC 24 Sep 01 09:05:17 AM UTC 24 2050840836 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.4172962309 Sep 01 09:05:13 AM UTC 24 Sep 01 09:05:17 AM UTC 24 2152113588 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.479579816 Sep 01 09:04:57 AM UTC 24 Sep 01 09:05:17 AM UTC 24 5318887527 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1508135902 Sep 01 09:05:04 AM UTC 24 Sep 01 09:05:18 AM UTC 24 5992162186 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.2329144636 Sep 01 09:05:05 AM UTC 24 Sep 01 09:05:19 AM UTC 24 2464629845 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2761032480 Sep 01 09:04:00 AM UTC 24 Sep 01 09:05:19 AM UTC 24 22009225615 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.458962153 Sep 01 09:05:07 AM UTC 24 Sep 01 09:05:19 AM UTC 24 2020492807 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2773750806 Sep 01 09:04:14 AM UTC 24 Sep 01 09:05:20 AM UTC 24 29082207963 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.1492528909 Sep 01 09:05:14 AM UTC 24 Sep 01 09:05:20 AM UTC 24 2489506448 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.2529283349 Sep 01 09:05:17 AM UTC 24 Sep 01 09:05:21 AM UTC 24 2274800052 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2602210131 Sep 01 09:05:12 AM UTC 24 Sep 01 09:05:21 AM UTC 24 8350586714 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.469114277 Sep 01 09:05:18 AM UTC 24 Sep 01 09:05:22 AM UTC 24 6440479019 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.3651185422 Sep 01 09:05:20 AM UTC 24 Sep 01 09:05:24 AM UTC 24 2037280937 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.22324854 Sep 01 09:05:10 AM UTC 24 Sep 01 09:05:24 AM UTC 24 2921288350 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.4174405286 Sep 01 09:04:16 AM UTC 24 Sep 01 09:05:24 AM UTC 24 42021990368 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.774522899 Sep 01 09:05:17 AM UTC 24 Sep 01 09:05:25 AM UTC 24 2519822263 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.495127610 Sep 01 09:05:20 AM UTC 24 Sep 01 09:05:25 AM UTC 24 6938336365 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1350477754 Sep 01 09:05:32 AM UTC 24 Sep 01 09:05:52 AM UTC 24 25193162935 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.3661010765 Sep 01 09:05:22 AM UTC 24 Sep 01 09:05:25 AM UTC 24 2484651945 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2737861743 Sep 01 09:05:22 AM UTC 24 Sep 01 09:05:26 AM UTC 24 2129904472 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3658461227 Sep 01 09:05:04 AM UTC 24 Sep 01 09:05:27 AM UTC 24 14745846664 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.926824462 Sep 01 09:03:51 AM UTC 24 Sep 01 09:05:27 AM UTC 24 22010308371 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.866365049 Sep 01 09:05:19 AM UTC 24 Sep 01 09:05:27 AM UTC 24 3805839153 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.4199645506 Sep 01 09:05:23 AM UTC 24 Sep 01 09:05:27 AM UTC 24 2266939815 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1554817013 Sep 01 09:05:04 AM UTC 24 Sep 01 09:05:27 AM UTC 24 7773200872 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2374645966 Sep 01 09:05:20 AM UTC 24 Sep 01 09:05:29 AM UTC 24 3109583220 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3403333051 Sep 01 09:05:18 AM UTC 24 Sep 01 09:05:30 AM UTC 24 2995042422 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3996489149 Sep 01 09:05:18 AM UTC 24 Sep 01 09:05:30 AM UTC 24 2715876072 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1764416239 Sep 01 09:05:10 AM UTC 24 Sep 01 09:05:31 AM UTC 24 682472100214 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.586674562 Sep 01 09:05:18 AM UTC 24 Sep 01 09:05:31 AM UTC 24 2611616528 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2118072513 Sep 01 09:05:26 AM UTC 24 Sep 01 09:05:31 AM UTC 24 6991568989 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1366668568 Sep 01 09:05:29 AM UTC 24 Sep 01 09:05:32 AM UTC 24 2124740992 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.603753166 Sep 01 09:05:26 AM UTC 24 Sep 01 09:05:33 AM UTC 24 3097240403 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1112184521 Sep 01 09:05:30 AM UTC 24 Sep 01 09:05:35 AM UTC 24 2124101976 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.234262790 Sep 01 09:05:25 AM UTC 24 Sep 01 09:05:36 AM UTC 24 2509965441 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2680668342 Sep 01 09:05:25 AM UTC 24 Sep 01 09:05:36 AM UTC 24 2883474156 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1017920693 Sep 01 09:05:26 AM UTC 24 Sep 01 09:05:37 AM UTC 24 2369063036 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2872999951 Sep 01 09:05:29 AM UTC 24 Sep 01 09:05:38 AM UTC 24 2462642147 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.544661895 Sep 01 09:05:31 AM UTC 24 Sep 01 09:05:38 AM UTC 24 2513126225 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1583983314 Sep 01 09:05:32 AM UTC 24 Sep 01 09:05:39 AM UTC 24 3879712664 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1054240059 Sep 01 09:04:40 AM UTC 24 Sep 01 09:05:39 AM UTC 24 66457281800 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.2151381414 Sep 01 09:05:29 AM UTC 24 Sep 01 09:05:40 AM UTC 24 2008443467 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1231586507 Sep 01 09:05:25 AM UTC 24 Sep 01 09:05:40 AM UTC 24 2613383844 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1811042608 Sep 01 09:05:31 AM UTC 24 Sep 01 09:05:41 AM UTC 24 2608942015 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1340090844 Sep 01 09:05:27 AM UTC 24 Sep 01 09:05:41 AM UTC 24 9811663188 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.3380347724 Sep 01 09:05:38 AM UTC 24 Sep 01 09:05:42 AM UTC 24 2124155069 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3881622740 Sep 01 09:05:40 AM UTC 24 Sep 01 09:05:44 AM UTC 24 2136854144 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.470410278 Sep 01 09:05:37 AM UTC 24 Sep 01 09:05:45 AM UTC 24 2014562574 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3902850158 Sep 01 09:05:32 AM UTC 24 Sep 01 09:05:45 AM UTC 24 3431025491 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2338706466 Sep 01 09:05:41 AM UTC 24 Sep 01 09:05:45 AM UTC 24 3371073336 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2428279476 Sep 01 09:05:41 AM UTC 24 Sep 01 09:05:46 AM UTC 24 4498732377 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.991022364 Sep 01 09:04:34 AM UTC 24 Sep 01 09:05:47 AM UTC 24 112506290046 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3210649203 Sep 01 09:05:33 AM UTC 24 Sep 01 09:05:48 AM UTC 24 2378029752 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3797701787 Sep 01 09:05:47 AM UTC 24 Sep 01 09:05:51 AM UTC 24 2127725296 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3935041795 Sep 01 09:05:49 AM UTC 24 Sep 01 09:05:52 AM UTC 24 2145181709 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.32561075 Sep 01 09:05:40 AM UTC 24 Sep 01 09:05:53 AM UTC 24 2512268159 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1177014714 Sep 01 09:05:40 AM UTC 24 Sep 01 09:05:53 AM UTC 24 2613187953 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.2564388428 Sep 01 09:05:39 AM UTC 24 Sep 01 09:05:54 AM UTC 24 2469344478 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2247503688 Sep 01 09:05:45 AM UTC 24 Sep 01 09:05:54 AM UTC 24 8136366789 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4058595631 Sep 01 09:05:53 AM UTC 24 Sep 01 09:05:56 AM UTC 24 3469471694 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.3383498736 Sep 01 09:05:48 AM UTC 24 Sep 01 09:05:56 AM UTC 24 2471906405 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.4257566112 Sep 01 09:05:47 AM UTC 24 Sep 01 09:05:57 AM UTC 24 2012037102 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2793957515 Sep 01 09:05:53 AM UTC 24 Sep 01 09:05:58 AM UTC 24 3961915400 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3635710214 Sep 01 09:05:53 AM UTC 24 Sep 01 09:05:58 AM UTC 24 2631116197 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.3194266014 Sep 01 09:04:27 AM UTC 24 Sep 01 09:05:58 AM UTC 24 75332695829 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.3574452286 Sep 01 09:05:43 AM UTC 24 Sep 01 09:05:58 AM UTC 24 3086936640 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1854524795 Sep 01 09:05:54 AM UTC 24 Sep 01 09:06:00 AM UTC 24 6951987522 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1950686041 Sep 01 09:05:55 AM UTC 24 Sep 01 09:06:00 AM UTC 24 2948460854 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.3048492100 Sep 01 09:05:58 AM UTC 24 Sep 01 09:06:02 AM UTC 24 2038978918 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3185849083 Sep 01 09:05:59 AM UTC 24 Sep 01 09:06:04 AM UTC 24 2491052076 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1685109955 Sep 01 09:06:17 AM UTC 24 Sep 01 09:06:44 AM UTC 24 9638886610 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.849163917 Sep 01 09:05:35 AM UTC 24 Sep 01 09:06:04 AM UTC 24 9967115742 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.365464452 Sep 01 09:05:52 AM UTC 24 Sep 01 09:06:05 AM UTC 24 2511925763 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3364991186 Sep 01 09:05:59 AM UTC 24 Sep 01 09:06:05 AM UTC 24 2061185725 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2548130074 Sep 01 09:04:10 AM UTC 24 Sep 01 09:06:05 AM UTC 24 102229132695 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3670095962 Sep 01 09:05:32 AM UTC 24 Sep 01 09:06:06 AM UTC 24 179704155098 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1757421858 Sep 01 09:06:01 AM UTC 24 Sep 01 09:06:07 AM UTC 24 2624247951 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3226341288 Sep 01 09:05:28 AM UTC 24 Sep 01 09:06:07 AM UTC 24 8309777115 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3740185429 Sep 01 09:06:03 AM UTC 24 Sep 01 09:06:08 AM UTC 24 3692479311 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.15471888 Sep 01 09:06:07 AM UTC 24 Sep 01 09:06:10 AM UTC 24 2145924339 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3085833646 Sep 01 09:05:59 AM UTC 24 Sep 01 09:06:10 AM UTC 24 2113110038 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3899314504 Sep 01 09:06:08 AM UTC 24 Sep 01 09:06:11 AM UTC 24 2196939455 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2694640855 Sep 01 09:05:59 AM UTC 24 Sep 01 09:06:12 AM UTC 24 2511485752 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3449517609 Sep 01 09:06:04 AM UTC 24 Sep 01 09:06:13 AM UTC 24 5617899268 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.900376332 Sep 01 09:06:01 AM UTC 24 Sep 01 09:06:13 AM UTC 24 2537438280 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_31/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2860654175 Sep 01 09:06:09 AM UTC 24 Sep 01 09:06:14 AM UTC 24 2525678367 ps
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