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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 62 1 T35 3 T58 2 T97 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T57 1 T118 2 T234 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 47 1 T43 1 T245 1 T169 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 20 1 T46 1 T118 1 T233 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 44 1 T35 1 T58 1 T48 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 30 1 T57 1 T47 2 T233 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 33 1 T48 1 T366 1 T348 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 38 1 T47 1 T118 1 T120 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 61 1 T35 4 T49 1 T47 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 29 1 T57 2 T103 1 T47 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 43 1 T97 1 T43 1 T44 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 25 1 T46 1 T103 1 T118 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 42 1 T35 2 T48 1 T43 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 15 1 T47 1 T48 1 T233 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 33 1 T48 1 T45 2 T121 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 47 1 T47 1 T48 7 T233 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 53 1 T59 1 T43 1 T44 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 34 1 T46 1 T57 1 T103 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 35 1 T59 1 T119 1 T228 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 27 1 T57 1 T169 4 T349 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 41 1 T44 1 T245 1 T45 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 20 1 T57 1 T47 1 T346 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 44 1 T57 1 T44 1 T245 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 36 1 T46 2 T103 1 T120 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 40 1 T119 1 T245 1 T169 3
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 23 1 T103 1 T118 1 T233 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 55 1 T119 1 T121 1 T350 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 31 1 T46 1 T103 2 T118 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 53 1 T46 1 T121 1 T169 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 41 1 T59 1 T118 1 T120 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 60 1 T245 1 T169 1 T229 9
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 48 1 T46 2 T59 6 T47 4
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 39 1 T35 1 T44 1 T119 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 20 1 T234 1 T346 1 T252 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 50 1 T103 1 T97 1 T119 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 16 1 T46 2 T57 1 T103 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 59 1 T48 1 T43 1 T119 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 21 1 T46 1 T47 1 T169 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 40 1 T245 2 T169 1 T221 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 20 1 T57 2 T103 1 T233 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 55 1 T35 1 T97 2 T44 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 26 1 T120 1 T349 1 T125 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 46 1 T245 1 T169 3 T350 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 25 1 T57 1 T120 1 T233 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 38 1 T48 1 T119 2 T169 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 51 1 T35 9 T46 1 T57 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 43 1 T43 1 T44 2 T119 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 58 1 T46 1 T47 1 T118 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 44 1 T58 2 T43 1 T119 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 33 1 T57 1 T103 1 T120 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 57 1 T48 2 T97 3 T44 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 35 1 T46 1 T57 1 T48 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 70 1 T59 1 T58 9 T44 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 19 1 T57 1 T47 1 T169 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 41 1 T44 2 T45 8 T122 9
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 30 1 T46 3 T103 1 T47 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 40 1 T43 1 T119 1 T245 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 64 1 T57 1 T47 1 T118 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 61 1 T118 1 T119 2 T245 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 65 1 T57 2 T118 2 T97 7
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 91 1 T59 1 T44 2 T119 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 88 1 T46 2 T59 2 T103 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 153 1 T46 2 T47 3 T44 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 114 1 T57 7 T103 2 T118 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 1 1 T43 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 17 1 T233 1 T347 5 T346 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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