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ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

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ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered80.78
Success102099.22
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091591500
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001194891410373675800
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001194890855558900
tb.dut.tlul_assert_device.gen_device.contigMask_M 0011948914101992433400
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00119489141017364800
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001194890855590900
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0011948914102207127100
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00119489141049868800
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0011948914102207127100
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00119489141049868800
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00119489141049868800
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00119489141049868800
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001194890855356200
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001194890855339500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091591500
tb.dut.u_reg.en2addrHit 00119489085524905200
tb.dut.u_reg.reAfterRv 00119489085524905200
tb.dut.u_reg.rePulse 00119489085513207300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 001194890855117490900
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001194890855119600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855119600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881119600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881112900
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855120500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 001194890855112636000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001194890855112000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855112000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881112000
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881105500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855112900
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091591500
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001194890855178037300
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001194890855187000
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855187000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881187000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881180900
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855187800
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001194890855165295000
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001194890855179300
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855179300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881179300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881173000
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855180000
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001194890855169817300
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001194890855180900
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855180900
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881180900
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881174300
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855181500
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001194890855165704400
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001194890855179400
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855179400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881179400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881173100
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855180000
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001194890855172995000
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001194890855184300
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855184300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881184300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881177800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855185100
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001194890855170566600
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001194890855182200
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855182200
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881182200
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881175500
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855182800
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001194890855168010100
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001194890855180700
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855180700
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881180700
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881174300
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855181500
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001194890855171401200
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001194890855184700
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855184700
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881184700
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881178100
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855185500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001194890855127013000
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001194890855130400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855130400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881130400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881123900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855131100
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001194890855123503100
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001194890855126400
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855126400
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881126400
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881119800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855127300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 001194890855122796900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001194890855126500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855126500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881126500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881120500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855127400
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 001194890855122688900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001194890855130700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855130700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881130700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881124200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855131400
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001194890855654775900
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001194890855734800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855734800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881734800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881728600
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855735700
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001194890855660170700
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001194890855739900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855739900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881739900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881733500
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855740500
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001194890855650526500
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001194890855735400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855735400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881735400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881728900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855736200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001194890855627399100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001194890855723100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855723100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881723100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881716600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855723900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001194890855703007100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001194890855785900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855785900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881785900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881779700
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855786700
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001194890855717494700
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001194890855797600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855797600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881797600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881791000
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855798400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001194890855701643700
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001194890855788400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855788400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881788400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881781800
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855789200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001194890855674661900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001194890855775500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855775500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881775500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881769100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855776100
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001194890855170152100
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 006093881546312800
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001194890855186700
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001194890855119446813000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001194890855186700
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006093881186700
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 006093881180400
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001194890855187500
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A 001194890855107853400
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A 006093881546312800
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