Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.46 98.71 97.93 100.00 94.23 99.00 99.23 93.11


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
42.68 42.68 66.34 66.34 47.13 47.13 55.14 55.14 4.49 4.49 69.98 69.98 54.05 54.05 1.66 1.66 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.558654212
61.58 18.90 79.81 13.47 61.77 14.64 56.51 1.37 71.15 66.67 81.15 11.16 76.69 22.64 4.02 2.35 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.4127630511
69.67 8.08 82.65 2.84 70.27 8.50 84.93 28.42 78.85 7.69 83.59 2.44 81.98 5.30 5.40 1.38 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1674764404
75.88 6.22 88.04 5.39 78.81 8.55 87.67 2.74 78.85 0.00 88.32 4.73 89.11 7.13 20.38 14.98 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.490027011
80.48 4.60 92.41 4.37 85.16 6.35 94.86 7.19 78.85 0.00 91.98 3.66 90.85 1.73 29.28 8.90 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2383394516
82.39 1.91 93.97 1.57 87.53 2.38 95.09 0.23 78.85 0.00 93.46 1.48 91.43 0.58 36.39 7.12 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3528233796
83.96 1.57 95.82 1.85 91.15 3.62 95.55 0.46 79.49 0.64 96.23 2.77 92.87 1.45 36.62 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3509799591
85.43 1.47 97.31 1.49 93.43 2.28 96.58 1.03 79.49 0.00 97.60 1.37 94.32 1.45 39.32 2.70 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3679981955
86.78 1.35 97.33 0.02 94.56 1.14 97.26 0.68 79.49 0.00 97.63 0.04 94.41 0.10 46.79 7.46 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.741919038
87.77 0.99 97.44 0.11 94.79 0.23 97.72 0.46 82.05 2.56 97.86 0.22 94.89 0.48 49.66 2.87 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1128574318
88.72 0.95 97.48 0.04 94.79 0.00 97.72 0.00 83.33 1.28 97.93 0.07 94.89 0.00 54.88 5.22 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3070226194
89.62 0.90 97.50 0.02 94.92 0.13 97.72 0.00 83.97 0.64 97.97 0.04 95.09 0.19 60.16 5.28 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3376853738
90.45 0.83 97.67 0.17 95.15 0.23 97.72 0.00 83.97 0.00 98.00 0.04 95.18 0.10 65.44 5.28 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3978077463
91.25 0.80 97.67 0.00 95.52 0.38 98.17 0.46 83.97 0.00 98.04 0.04 96.63 1.45 68.71 3.27 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3936376147
91.83 0.58 97.69 0.02 95.55 0.03 98.17 0.00 83.97 0.00 98.04 0.00 96.63 0.00 72.73 4.02 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2032200737
92.28 0.45 97.87 0.19 95.70 0.15 98.17 0.00 85.90 1.92 98.19 0.15 97.30 0.67 72.79 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4269792235
92.71 0.43 97.95 0.07 95.73 0.03 98.17 0.00 85.90 0.00 98.19 0.00 97.30 0.00 75.72 2.93 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1040697372
93.01 0.30 98.00 0.06 95.73 0.00 98.17 0.00 87.82 1.92 98.30 0.11 97.30 0.00 75.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1231217555
93.30 0.29 98.00 0.00 95.78 0.05 99.77 1.60 87.82 0.00 98.30 0.00 97.40 0.10 76.00 0.29 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2944511846
93.58 0.28 98.08 0.07 95.88 0.10 99.77 0.00 87.82 0.00 98.34 0.04 97.50 0.10 77.67 1.66 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3419147377
93.84 0.27 98.10 0.02 95.88 0.00 99.77 0.00 87.82 0.00 98.34 0.00 97.50 0.00 79.51 1.84 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.428816323
94.10 0.25 98.15 0.06 95.98 0.10 99.77 0.00 89.10 1.28 98.41 0.07 97.69 0.19 79.56 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.328624639
94.29 0.19 98.19 0.04 96.69 0.71 99.77 0.00 89.10 0.00 98.41 0.00 97.78 0.10 80.08 0.52 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.25425653
94.48 0.19 98.23 0.04 96.84 0.15 99.77 0.00 89.74 0.64 98.48 0.07 97.98 0.19 80.31 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1274437426
94.66 0.18 98.25 0.02 96.84 0.00 99.77 0.00 90.38 0.64 98.52 0.04 97.98 0.00 80.88 0.57 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.911929460
94.84 0.18 98.25 0.00 96.84 0.00 99.77 0.00 90.38 0.00 98.52 0.00 97.98 0.00 82.15 1.26 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2067485096
95.02 0.18 98.30 0.06 96.84 0.00 99.77 0.00 90.38 0.00 98.52 0.00 97.98 0.00 83.35 1.21 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.373042047
95.20 0.18 98.30 0.00 96.94 0.10 99.77 0.00 90.38 0.00 98.52 0.00 98.55 0.58 83.93 0.57 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1646864059
95.36 0.16 98.30 0.00 96.94 0.00 99.77 0.00 90.38 0.00 98.52 0.00 98.55 0.00 85.07 1.15 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.804466718
95.53 0.16 98.34 0.04 97.07 0.13 99.77 0.00 91.03 0.64 98.56 0.04 98.84 0.29 85.07 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.1361162717
95.67 0.14 98.34 0.00 97.07 0.00 99.77 0.00 91.03 0.00 98.56 0.00 98.84 0.00 86.05 0.98 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.51974649
95.79 0.12 98.36 0.02 97.07 0.00 99.77 0.00 91.67 0.64 98.60 0.04 98.84 0.00 86.22 0.17 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.899706296
95.91 0.12 98.40 0.04 97.12 0.05 99.77 0.00 92.31 0.64 98.63 0.04 98.94 0.10 86.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.453009744
96.03 0.12 98.43 0.04 97.14 0.03 99.77 0.00 92.95 0.64 98.67 0.04 99.04 0.10 86.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4130898885
96.14 0.11 98.43 0.00 97.14 0.00 99.77 0.00 92.95 0.00 98.67 0.00 99.04 0.00 86.97 0.75 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3973706608
96.24 0.10 98.45 0.02 97.14 0.00 99.77 0.00 93.59 0.64 98.71 0.04 99.04 0.00 86.97 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2835014367
96.34 0.10 98.47 0.02 97.14 0.00 99.77 0.00 94.23 0.64 98.74 0.04 99.04 0.00 86.97 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.1702032031
96.44 0.10 98.47 0.00 97.14 0.00 99.77 0.00 94.23 0.00 98.74 0.00 99.04 0.00 87.66 0.69 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.80690343
96.53 0.09 98.53 0.06 97.40 0.25 99.77 0.00 94.23 0.00 98.89 0.15 99.23 0.19 87.66 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1100115652
96.60 0.07 98.53 0.00 97.42 0.03 99.77 0.00 94.23 0.00 98.89 0.00 99.23 0.00 88.12 0.46 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.464841805
96.66 0.07 98.53 0.00 97.42 0.00 99.77 0.00 94.23 0.00 98.89 0.00 99.23 0.00 88.58 0.46 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.891000620
96.72 0.06 98.54 0.02 97.42 0.00 99.77 0.00 94.23 0.00 98.89 0.00 99.23 0.00 88.98 0.40 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.232302008
96.78 0.06 98.54 0.00 97.42 0.00 99.77 0.00 94.23 0.00 98.89 0.00 99.23 0.00 89.38 0.40 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1370891212
96.84 0.06 98.60 0.06 97.47 0.05 100.00 0.23 94.23 0.00 98.89 0.00 99.23 0.00 89.44 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3023123000
96.89 0.05 98.60 0.00 97.47 0.00 100.00 0.00 94.23 0.00 98.89 0.00 99.23 0.00 89.78 0.34 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1570642321
96.93 0.04 98.62 0.02 97.47 0.00 100.00 0.00 94.23 0.00 98.89 0.00 99.23 0.00 90.07 0.29 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1915197595
96.97 0.04 98.62 0.00 97.47 0.00 100.00 0.00 94.23 0.00 98.89 0.00 99.23 0.00 90.36 0.29 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.4160386988
97.01 0.04 98.62 0.00 97.75 0.28 100.00 0.00 94.23 0.00 98.89 0.00 99.23 0.00 90.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.393638684
97.05 0.04 98.64 0.02 97.77 0.03 100.00 0.00 94.23 0.00 98.93 0.04 99.23 0.00 90.53 0.17 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1662908657
97.08 0.04 98.66 0.02 97.77 0.00 100.00 0.00 94.23 0.00 98.93 0.00 99.23 0.00 90.76 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2504430699
97.12 0.03 98.66 0.00 97.77 0.00 100.00 0.00 94.23 0.00 98.93 0.00 99.23 0.00 90.99 0.23 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.4262545853
97.14 0.02 98.66 0.00 97.77 0.00 100.00 0.00 94.23 0.00 98.93 0.00 99.23 0.00 91.16 0.17 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3064189143
97.16 0.02 98.66 0.00 97.77 0.00 100.00 0.00 94.23 0.00 98.93 0.00 99.23 0.00 91.33 0.17 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.164629266
97.18 0.02 98.69 0.04 97.83 0.05 100.00 0.00 94.23 0.00 98.96 0.04 99.23 0.00 91.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.881888780
97.20 0.02 98.69 0.00 97.83 0.00 100.00 0.00 94.23 0.00 98.96 0.00 99.23 0.00 91.45 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4089152173
97.22 0.02 98.69 0.00 97.83 0.00 100.00 0.00 94.23 0.00 98.96 0.00 99.23 0.00 91.56 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1551252899
97.23 0.02 98.69 0.00 97.83 0.00 100.00 0.00 94.23 0.00 98.96 0.00 99.23 0.00 91.68 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.408924200
97.25 0.02 98.69 0.00 97.83 0.00 100.00 0.00 94.23 0.00 98.96 0.00 99.23 0.00 91.79 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3238389784
97.26 0.02 98.69 0.00 97.83 0.00 100.00 0.00 94.23 0.00 98.96 0.00 99.23 0.00 91.91 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3036150960
97.28 0.02 98.69 0.00 97.83 0.00 100.00 0.00 94.23 0.00 98.96 0.00 99.23 0.00 92.02 0.11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.734995200
97.30 0.02 98.71 0.02 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.04 99.23 0.00 92.08 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2284202886
97.31 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.14 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.3493825298
97.31 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.19 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.4294240272
97.32 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.25 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1712009633
97.33 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.31 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3271221664
97.34 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.37 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.760661730
97.35 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.42 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.1964914873
97.35 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.48 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3424477886
97.36 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.54 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1982689176
97.37 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.59 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.302371780
97.38 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.65 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3428254959
97.39 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.71 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2233833953
97.40 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.77 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1818956905
97.40 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.82 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2885866189
97.41 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.88 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1634231527
97.42 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 92.94 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1015101026
97.43 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.00 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1534155698
97.44 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.05 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1810078022
97.44 0.01 98.71 0.00 97.83 0.00 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.11 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3028993503
97.45 0.01 98.71 0.00 97.85 0.03 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1112824482
97.45 0.01 98.71 0.00 97.88 0.03 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1841118168
97.46 0.01 98.71 0.00 97.90 0.03 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1104628761
97.46 0.01 98.71 0.00 97.93 0.03 100.00 0.00 94.23 0.00 99.00 0.00 99.23 0.00 93.11 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.563940514

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2147733919
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2268376630
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3763100424
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3395562328
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3759505829
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4134644911
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1059994646
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2634977352
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2174881800
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.497550950
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3854413978
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2024649388
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1811141891
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2805765595
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2566269286
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.522539850
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.108269899
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3830812756
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3180964365
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1340114956
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3202588005
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1990971766
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2085547263
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.618474703
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.815005175
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.501992602
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1527772059
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3320240592
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3163602133
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3758178769
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.122314984
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.638355352
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2139889658
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.919906693
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3544322505
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3791086559
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1297409742
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.422548914
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.426061852
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.633902657
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2222560919
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3144756506
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.700140280
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2578058042
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2161459167
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4100346231
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2405003753
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1629496028
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2564014241
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1937380955
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.895453991
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2374753961
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2487758618
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1020109382
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3747723169
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3273610021
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4230026163
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3629509294
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2671045721
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.355186199
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2300395695
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3875660319
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.191832060
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3918513596
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.357917805
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.195029604
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3429483431
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.353080783
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2520549151
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2402635384
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2137670732
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1476771499
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.457568820
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1586975309
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1959421757
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.640347066
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.4143523530
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1667627233
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3389207070
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1830744273
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2322317777
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.445128203
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1563494599
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1973740877
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1765967962
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3287682780
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.815570355
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3226994284
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1815256472
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2373311825
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1950577358
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.724832320
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.493273340
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2391898408
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.4154908072
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1268373086
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1210287137
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2236314272
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1389744199
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.4056094132
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3938515727
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.656521044
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2482272694
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4069510648
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.555965102
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1444932003
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2590503832
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1299027732
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3678730720
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3903710930
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.180577952
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2820585107
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3724617450
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.308327137
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.444127980
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2687718964
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3320090743
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2525000561
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.172316639
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Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4177425828 Sep 04 02:13:00 AM UTC 24 Sep 04 02:13:04 AM UTC 24 2446912543 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1018500351 Sep 04 02:13:02 AM UTC 24 Sep 04 02:13:05 AM UTC 24 2104759008 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1790063359 Sep 04 02:13:00 AM UTC 24 Sep 04 02:13:05 AM UTC 24 2358813410 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.425889114 Sep 04 02:12:59 AM UTC 24 Sep 04 02:13:08 AM UTC 24 2113662400 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2490582313 Sep 04 02:13:06 AM UTC 24 Sep 04 02:13:09 AM UTC 24 6930345672 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2935546100 Sep 04 02:12:59 AM UTC 24 Sep 04 02:13:10 AM UTC 24 2483775168 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2097816577 Sep 04 02:13:06 AM UTC 24 Sep 04 02:13:10 AM UTC 24 5464644399 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1824141713 Sep 04 02:13:05 AM UTC 24 Sep 04 02:13:11 AM UTC 24 2617801528 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.558654212 Sep 04 02:13:11 AM UTC 24 Sep 04 02:13:13 AM UTC 24 2561136955 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4214554477 Sep 04 02:13:06 AM UTC 24 Sep 04 02:13:13 AM UTC 24 3339998566 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2383394516 Sep 04 02:13:11 AM UTC 24 Sep 04 02:13:14 AM UTC 24 2542298669 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3679981955 Sep 04 02:13:08 AM UTC 24 Sep 04 02:13:14 AM UTC 24 7528227021 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.671201577 Sep 04 02:13:10 AM UTC 24 Sep 04 02:13:15 AM UTC 24 2133430639 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3973706608 Sep 04 02:13:04 AM UTC 24 Sep 04 02:13:15 AM UTC 24 2511004745 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2360525789 Sep 04 02:13:11 AM UTC 24 Sep 04 02:13:15 AM UTC 24 2423889455 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3598775148 Sep 04 02:13:11 AM UTC 24 Sep 04 02:13:15 AM UTC 24 2483503096 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1841118168 Sep 04 02:13:09 AM UTC 24 Sep 04 02:13:15 AM UTC 24 2019480514 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.212427987 Sep 04 02:13:12 AM UTC 24 Sep 04 02:13:17 AM UTC 24 3626438051 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.158306610 Sep 04 02:13:11 AM UTC 24 Sep 04 02:13:17 AM UTC 24 2174180779 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1828061610 Sep 04 02:13:05 AM UTC 24 Sep 04 02:13:18 AM UTC 24 2530953069 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3361366924 Sep 04 02:13:08 AM UTC 24 Sep 04 02:13:19 AM UTC 24 13901374186 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.122914870 Sep 04 02:13:16 AM UTC 24 Sep 04 02:13:19 AM UTC 24 2049107659 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1707569171 Sep 04 02:13:11 AM UTC 24 Sep 04 02:13:19 AM UTC 24 2612285794 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2084621075 Sep 04 02:13:17 AM UTC 24 Sep 04 02:13:21 AM UTC 24 2499237178 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1104628761 Sep 04 02:13:14 AM UTC 24 Sep 04 02:13:23 AM UTC 24 4026801872 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4128409484 Sep 04 02:13:17 AM UTC 24 Sep 04 02:13:23 AM UTC 24 2169182635 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.349031090 Sep 04 02:13:20 AM UTC 24 Sep 04 02:13:24 AM UTC 24 2831543784 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2067485096 Sep 04 02:13:19 AM UTC 24 Sep 04 02:13:24 AM UTC 24 2530632560 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.1439900961 Sep 04 02:13:17 AM UTC 24 Sep 04 02:13:24 AM UTC 24 2118697547 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3956696770 Sep 04 02:13:18 AM UTC 24 Sep 04 02:13:28 AM UTC 24 2057020234 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3936376147 Sep 04 02:13:15 AM UTC 24 Sep 04 02:13:28 AM UTC 24 12739826142 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2803376299 Sep 04 02:13:12 AM UTC 24 Sep 04 02:13:30 AM UTC 24 4566392789 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2793609787 Sep 04 02:13:20 AM UTC 24 Sep 04 02:13:31 AM UTC 24 2614165813 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.829658405 Sep 04 02:13:18 AM UTC 24 Sep 04 02:13:31 AM UTC 24 2277835559 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.245589857 Sep 04 02:13:29 AM UTC 24 Sep 04 02:13:33 AM UTC 24 2488013279 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.716118751 Sep 04 02:13:29 AM UTC 24 Sep 04 02:13:33 AM UTC 24 2131087256 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1674764404 Sep 04 02:13:20 AM UTC 24 Sep 04 02:13:34 AM UTC 24 3447802161 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1030647724 Sep 04 02:13:20 AM UTC 24 Sep 04 02:13:34 AM UTC 24 3183464303 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.1610258516 Sep 04 02:13:25 AM UTC 24 Sep 04 02:13:34 AM UTC 24 3708090125 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2786759731 Sep 04 02:13:31 AM UTC 24 Sep 04 02:13:35 AM UTC 24 2104530654 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2944511846 Sep 04 02:13:15 AM UTC 24 Sep 04 02:13:35 AM UTC 24 22052277530 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4074593749 Sep 04 02:13:31 AM UTC 24 Sep 04 02:13:38 AM UTC 24 2552680250 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.1283411606 Sep 04 02:13:28 AM UTC 24 Sep 04 02:13:38 AM UTC 24 2015427709 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2398441322 Sep 04 02:13:34 AM UTC 24 Sep 04 02:13:39 AM UTC 24 3251410054 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3501061652 Sep 04 02:13:30 AM UTC 24 Sep 04 02:13:41 AM UTC 24 2160094455 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3926970620 Sep 04 02:13:31 AM UTC 24 Sep 04 02:13:41 AM UTC 24 2514626888 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.274286118 Sep 04 02:13:25 AM UTC 24 Sep 04 02:13:42 AM UTC 24 17559034299 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2839188768 Sep 04 02:13:35 AM UTC 24 Sep 04 02:13:42 AM UTC 24 3395572457 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1475473972 Sep 04 02:13:34 AM UTC 24 Sep 04 02:13:43 AM UTC 24 2614970648 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1988321428 Sep 04 02:13:35 AM UTC 24 Sep 04 02:13:45 AM UTC 24 37893574286 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3922640366 Sep 04 02:13:41 AM UTC 24 Sep 04 02:13:46 AM UTC 24 2525916463 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3528233796 Sep 04 02:13:37 AM UTC 24 Sep 04 02:13:46 AM UTC 24 6713884529 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3798806499 Sep 04 02:13:41 AM UTC 24 Sep 04 02:13:46 AM UTC 24 2117542251 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2312975330 Sep 04 02:13:43 AM UTC 24 Sep 04 02:13:47 AM UTC 24 2562020156 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2874638864 Sep 04 02:13:39 AM UTC 24 Sep 04 02:13:47 AM UTC 24 2107516759 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1512715465 Sep 04 02:13:40 AM UTC 24 Sep 04 02:13:48 AM UTC 24 2460770496 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2672149938 Sep 04 02:13:43 AM UTC 24 Sep 04 02:13:48 AM UTC 24 2627612532 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3023123000 Sep 04 02:13:38 AM UTC 24 Sep 04 02:13:48 AM UTC 24 2012605274 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3915809763 Sep 04 02:13:44 AM UTC 24 Sep 04 02:13:50 AM UTC 24 7648461154 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4267162575 Sep 04 02:13:44 AM UTC 24 Sep 04 02:13:52 AM UTC 24 3123355297 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.4161219031 Sep 04 02:13:47 AM UTC 24 Sep 04 02:13:54 AM UTC 24 4807757904 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3476997835 Sep 04 02:13:36 AM UTC 24 Sep 04 02:13:55 AM UTC 24 9114642732 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4269792235 Sep 04 02:13:35 AM UTC 24 Sep 04 02:13:55 AM UTC 24 841267830693 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.1948578295 Sep 04 02:13:25 AM UTC 24 Sep 04 02:13:56 AM UTC 24 22030660209 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.490027011 Sep 04 02:13:14 AM UTC 24 Sep 04 02:13:57 AM UTC 24 81475326352 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.425533925 Sep 04 02:13:48 AM UTC 24 Sep 04 02:13:57 AM UTC 24 2015381011 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1551252899 Sep 04 02:13:15 AM UTC 24 Sep 04 02:14:00 AM UTC 24 14459711784 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1982832558 Sep 04 02:13:53 AM UTC 24 Sep 04 02:13:58 AM UTC 24 2623886644 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.656928178 Sep 04 02:13:48 AM UTC 24 Sep 04 02:13:58 AM UTC 24 2112248559 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1692104858 Sep 04 02:13:47 AM UTC 24 Sep 04 02:13:58 AM UTC 24 2782762738 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.779048022 Sep 04 02:13:51 AM UTC 24 Sep 04 02:13:59 AM UTC 24 2521498058 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.520798023 Sep 04 02:13:50 AM UTC 24 Sep 04 02:13:59 AM UTC 24 2203788578 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1494377503 Sep 04 02:13:44 AM UTC 24 Sep 04 02:14:00 AM UTC 24 2931755157 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1662908657 Sep 04 02:13:55 AM UTC 24 Sep 04 02:14:00 AM UTC 24 7425509696 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.2722203192 Sep 04 02:13:56 AM UTC 24 Sep 04 02:14:01 AM UTC 24 3216626797 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1566083148 Sep 04 02:13:54 AM UTC 24 Sep 04 02:14:02 AM UTC 24 2631300542 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3991984102 Sep 04 02:13:56 AM UTC 24 Sep 04 02:14:03 AM UTC 24 6597567605 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.4207173525 Sep 04 02:13:50 AM UTC 24 Sep 04 02:14:03 AM UTC 24 2449301439 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.326208089 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:03 AM UTC 24 2266822473 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1915197595 Sep 04 02:13:15 AM UTC 24 Sep 04 02:14:03 AM UTC 24 61097947035 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.2639638114 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:04 AM UTC 24 2514756984 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3439814888 Sep 04 02:13:47 AM UTC 24 Sep 04 02:14:04 AM UTC 24 7062090473 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.970931664 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:04 AM UTC 24 2628945981 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2436134928 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:04 AM UTC 24 2481767156 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4167256561 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:04 AM UTC 24 4360248164 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.809962559 Sep 04 02:14:04 AM UTC 24 Sep 04 02:14:06 AM UTC 24 2559352017 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3892055111 Sep 04 02:14:01 AM UTC 24 Sep 04 02:14:07 AM UTC 24 12760147861 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.4224638332 Sep 04 02:14:03 AM UTC 24 Sep 04 02:14:07 AM UTC 24 2034012328 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.580385801 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:07 AM UTC 24 2011826981 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.83347828 Sep 04 02:13:59 AM UTC 24 Sep 04 02:14:07 AM UTC 24 2115181127 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1370891212 Sep 04 02:13:55 AM UTC 24 Sep 04 02:14:07 AM UTC 24 2931809183 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3083443906 Sep 04 02:14:02 AM UTC 24 Sep 04 02:14:07 AM UTC 24 11925338178 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.275179281 Sep 04 02:13:36 AM UTC 24 Sep 04 02:14:08 AM UTC 24 35819054156 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3409546297 Sep 04 02:14:04 AM UTC 24 Sep 04 02:14:08 AM UTC 24 2216622858 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3597382393 Sep 04 02:14:05 AM UTC 24 Sep 04 02:14:09 AM UTC 24 2890304727 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1915611887 Sep 04 02:14:05 AM UTC 24 Sep 04 02:14:09 AM UTC 24 4326401236 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.492591035 Sep 04 02:14:00 AM UTC 24 Sep 04 02:14:10 AM UTC 24 3502651376 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3509799591 Sep 04 02:13:57 AM UTC 24 Sep 04 02:14:11 AM UTC 24 12805415124 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.4199041951 Sep 04 02:14:08 AM UTC 24 Sep 04 02:14:11 AM UTC 24 2133233794 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.1457372925 Sep 04 02:14:04 AM UTC 24 Sep 04 02:14:11 AM UTC 24 2515713646 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.211605455 Sep 04 02:14:08 AM UTC 24 Sep 04 02:14:11 AM UTC 24 2034451505 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2223129110 Sep 04 02:14:04 AM UTC 24 Sep 04 02:14:12 AM UTC 24 2110610241 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3004678582 Sep 04 02:14:00 AM UTC 24 Sep 04 02:14:13 AM UTC 24 7562251482 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3226073681 Sep 04 02:14:09 AM UTC 24 Sep 04 02:14:14 AM UTC 24 2041668034 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.627896236 Sep 04 02:14:09 AM UTC 24 Sep 04 02:14:14 AM UTC 24 3595684662 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2094730555 Sep 04 02:14:09 AM UTC 24 Sep 04 02:14:14 AM UTC 24 2618505243 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1815315920 Sep 04 02:14:01 AM UTC 24 Sep 04 02:14:15 AM UTC 24 4653634845 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.840735967 Sep 04 02:14:07 AM UTC 24 Sep 04 02:14:15 AM UTC 24 4816926832 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.468349555 Sep 04 02:14:05 AM UTC 24 Sep 04 02:14:15 AM UTC 24 3214780609 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.2157673422 Sep 04 02:14:09 AM UTC 24 Sep 04 02:14:15 AM UTC 24 2514402276 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1000360865 Sep 04 02:14:08 AM UTC 24 Sep 04 02:14:16 AM UTC 24 9413764765 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3529841981 Sep 04 02:14:05 AM UTC 24 Sep 04 02:14:17 AM UTC 24 2612435681 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2702667035 Sep 04 02:14:13 AM UTC 24 Sep 04 02:14:18 AM UTC 24 2015263898 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.1340666808 Sep 04 02:14:09 AM UTC 24 Sep 04 02:14:18 AM UTC 24 2435769420 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.162189456 Sep 04 02:14:14 AM UTC 24 Sep 04 02:14:18 AM UTC 24 2493076794 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1225114567 Sep 04 02:14:15 AM UTC 24 Sep 04 02:14:18 AM UTC 24 2091830809 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.1221302164 Sep 04 02:14:13 AM UTC 24 Sep 04 02:14:19 AM UTC 24 2111289152 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.935160089 Sep 04 02:14:15 AM UTC 24 Sep 04 02:14:19 AM UTC 24 2622706049 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3020480325 Sep 04 02:14:10 AM UTC 24 Sep 04 02:14:19 AM UTC 24 3321670541 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2708756864 Sep 04 02:14:15 AM UTC 24 Sep 04 02:14:20 AM UTC 24 3056063693 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2135017570 Sep 04 02:14:11 AM UTC 24 Sep 04 02:14:20 AM UTC 24 32882732148 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2633497985 Sep 04 02:14:08 AM UTC 24 Sep 04 02:14:21 AM UTC 24 9874176909 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1773086131 Sep 04 02:14:15 AM UTC 24 Sep 04 02:14:21 AM UTC 24 2516198984 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3064189143 Sep 04 02:14:19 AM UTC 24 Sep 04 02:14:21 AM UTC 24 2576880043 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3013963198 Sep 04 02:14:16 AM UTC 24 Sep 04 02:14:21 AM UTC 24 3311809406 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.221415656 Sep 04 02:14:16 AM UTC 24 Sep 04 02:14:24 AM UTC 24 2932280884 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.1650919379 Sep 04 02:13:21 AM UTC 24 Sep 04 02:14:24 AM UTC 24 97199099889 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.874967430 Sep 04 02:14:20 AM UTC 24 Sep 04 02:14:24 AM UTC 24 2635326925 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1630156831 Sep 04 02:14:19 AM UTC 24 Sep 04 02:14:25 AM UTC 24 2477564267 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1621629420 Sep 04 02:14:20 AM UTC 24 Sep 04 02:14:25 AM UTC 24 3595587226 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.713880093 Sep 04 02:14:21 AM UTC 24 Sep 04 02:14:25 AM UTC 24 4333220529 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.2482523149 Sep 04 02:14:19 AM UTC 24 Sep 04 02:14:26 AM UTC 24 2113298567 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2821220163 Sep 04 02:14:20 AM UTC 24 Sep 04 02:14:28 AM UTC 24 2781307415 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1244851960 Sep 04 02:14:18 AM UTC 24 Sep 04 02:14:29 AM UTC 24 2011310508 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2719868230 Sep 04 02:14:26 AM UTC 24 Sep 04 02:14:29 AM UTC 24 2548114838 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3177051848 Sep 04 02:14:26 AM UTC 24 Sep 04 02:14:30 AM UTC 24 2044605349 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.328624639 Sep 04 02:14:21 AM UTC 24 Sep 04 02:14:31 AM UTC 24 4338540901 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2567921021 Sep 04 02:14:19 AM UTC 24 Sep 04 02:14:31 AM UTC 24 2167698878 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2225122959 Sep 04 02:14:27 AM UTC 24 Sep 04 02:14:31 AM UTC 24 3700307451 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3507873536 Sep 04 02:14:12 AM UTC 24 Sep 04 02:14:31 AM UTC 24 4072150380 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.1540551410 Sep 04 02:14:26 AM UTC 24 Sep 04 02:14:33 AM UTC 24 2468364144 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3501301282 Sep 04 02:14:26 AM UTC 24 Sep 04 02:14:34 AM UTC 24 2112868616 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2926839897 Sep 04 02:14:25 AM UTC 24 Sep 04 02:14:34 AM UTC 24 2013444579 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2198908345 Sep 04 02:14:32 AM UTC 24 Sep 04 02:14:35 AM UTC 24 2046826642 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.2010406417 Sep 04 02:14:10 AM UTC 24 Sep 04 02:14:35 AM UTC 24 49536261454 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1574117040 Sep 04 02:14:27 AM UTC 24 Sep 04 02:14:37 AM UTC 24 2608876258 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.2528432426 Sep 04 02:14:30 AM UTC 24 Sep 04 02:14:36 AM UTC 24 5070008255 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2567634295 Sep 04 02:14:33 AM UTC 24 Sep 04 02:14:39 AM UTC 24 2458449270 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1173905824 Sep 04 02:14:22 AM UTC 24 Sep 04 02:14:39 AM UTC 24 3226435325 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1719544659 Sep 04 02:14:33 AM UTC 24 Sep 04 02:14:39 AM UTC 24 2116000787 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1477151633 Sep 04 02:14:36 AM UTC 24 Sep 04 02:14:40 AM UTC 24 3224001962 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3100280485 Sep 04 02:14:35 AM UTC 24 Sep 04 02:14:42 AM UTC 24 2516204439 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3660066277 Sep 04 02:13:38 AM UTC 24 Sep 04 02:14:42 AM UTC 24 42184813611 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.108117720 Sep 04 02:14:12 AM UTC 24 Sep 04 02:14:42 AM UTC 24 9200134670 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.336866557 Sep 04 02:14:36 AM UTC 24 Sep 04 02:14:43 AM UTC 24 3373791589 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2698636469 Sep 04 02:14:17 AM UTC 24 Sep 04 02:14:44 AM UTC 24 9247548178 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3023462483 Sep 04 02:14:37 AM UTC 24 Sep 04 02:14:44 AM UTC 24 3238465278 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.493232513 Sep 04 02:14:41 AM UTC 24 Sep 04 02:14:44 AM UTC 24 2122498899 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.2560279301 Sep 04 02:14:21 AM UTC 24 Sep 04 02:14:45 AM UTC 24 27159784923 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.247392510 Sep 04 02:14:05 AM UTC 24 Sep 04 02:14:46 AM UTC 24 174733613382 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1878370060 Sep 04 02:14:08 AM UTC 24 Sep 04 02:14:46 AM UTC 24 59542829264 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1045788069 Sep 04 02:14:41 AM UTC 24 Sep 04 02:14:47 AM UTC 24 2015948092 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.3278282885 Sep 04 02:14:43 AM UTC 24 Sep 04 02:14:47 AM UTC 24 2158037677 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2031107038 Sep 04 02:14:28 AM UTC 24 Sep 04 02:14:47 AM UTC 24 3139637535 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.3782780341 Sep 04 02:14:34 AM UTC 24 Sep 04 02:14:47 AM UTC 24 2232346779 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3065069397 Sep 04 02:14:32 AM UTC 24 Sep 04 02:14:48 AM UTC 24 4226392873 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.4127630511 Sep 04 02:13:07 AM UTC 24 Sep 04 02:14:48 AM UTC 24 41296505570 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.750880804 Sep 04 02:14:43 AM UTC 24 Sep 04 02:14:48 AM UTC 24 2477333459 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.18943077 Sep 04 02:14:35 AM UTC 24 Sep 04 02:14:49 AM UTC 24 2611811526 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3792126753 Sep 04 02:14:45 AM UTC 24 Sep 04 02:14:50 AM UTC 24 3209618304 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.3036121273 Sep 04 02:14:49 AM UTC 24 Sep 04 02:14:51 AM UTC 24 2134367894 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3503251539 Sep 04 02:14:49 AM UTC 24 Sep 04 02:14:52 AM UTC 24 2761056857 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1189492916 Sep 04 02:14:48 AM UTC 24 Sep 04 02:14:52 AM UTC 24 2131757029 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1363688209 Sep 04 02:13:48 AM UTC 24 Sep 04 02:14:52 AM UTC 24 22011243915 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.214802712 Sep 04 02:14:45 AM UTC 24 Sep 04 02:14:52 AM UTC 24 4628676366 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3479066998 Sep 04 02:14:40 AM UTC 24 Sep 04 02:14:53 AM UTC 24 5179456417 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3376129758 Sep 04 02:14:44 AM UTC 24 Sep 04 02:14:54 AM UTC 24 2610626074 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.436925419 Sep 04 02:14:49 AM UTC 24 Sep 04 02:14:54 AM UTC 24 2530631511 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.271739535 Sep 04 02:14:22 AM UTC 24 Sep 04 02:14:54 AM UTC 24 11402246938 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3978077463 Sep 04 02:14:16 AM UTC 24 Sep 04 02:14:54 AM UTC 24 56632226346 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.232302008 Sep 04 02:14:16 AM UTC 24 Sep 04 02:14:54 AM UTC 24 50776933407 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1428371816 Sep 04 02:14:52 AM UTC 24 Sep 04 02:14:55 AM UTC 24 7236390303 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.1284849467 Sep 04 02:14:32 AM UTC 24 Sep 04 02:14:55 AM UTC 24 7072555840 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.976642404 Sep 04 02:14:51 AM UTC 24 Sep 04 02:14:56 AM UTC 24 3466941689 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.237509783 Sep 04 02:14:30 AM UTC 24 Sep 04 02:14:56 AM UTC 24 21095748168 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.173121611 Sep 04 02:14:43 AM UTC 24 Sep 04 02:14:56 AM UTC 24 2512027826 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1532103472 Sep 04 02:14:46 AM UTC 24 Sep 04 02:14:57 AM UTC 24 3135297772 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3393623739 Sep 04 02:14:45 AM UTC 24 Sep 04 02:14:58 AM UTC 24 3027790986 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.625901689 Sep 04 02:14:52 AM UTC 24 Sep 04 02:14:58 AM UTC 24 3274077603 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.4059131652 Sep 04 02:14:11 AM UTC 24 Sep 04 02:14:58 AM UTC 24 92057936219 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3986417405 Sep 04 02:14:48 AM UTC 24 Sep 04 02:14:59 AM UTC 24 2976165413 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1246011837 Sep 04 02:14:48 AM UTC 24 Sep 04 02:14:59 AM UTC 24 2013978311 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2586745153 Sep 04 02:14:55 AM UTC 24 Sep 04 02:15:00 AM UTC 24 2524532021 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2451943174 Sep 04 02:14:55 AM UTC 24 Sep 04 02:15:00 AM UTC 24 2619375462 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3271420638 Sep 04 02:14:50 AM UTC 24 Sep 04 02:15:00 AM UTC 24 2718726257 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.1233309025 Sep 04 02:14:49 AM UTC 24 Sep 04 02:15:01 AM UTC 24 2447865893 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.3461106466 Sep 04 02:14:54 AM UTC 24 Sep 04 02:15:02 AM UTC 24 2021426993 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2635350757 Sep 04 02:14:57 AM UTC 24 Sep 04 02:15:02 AM UTC 24 4832513654 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2807863361 Sep 04 02:14:55 AM UTC 24 Sep 04 02:15:02 AM UTC 24 2114347443 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1743231022 Sep 04 02:14:59 AM UTC 24 Sep 04 02:15:03 AM UTC 24 2029499584 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1149306302 Sep 04 02:14:55 AM UTC 24 Sep 04 02:15:03 AM UTC 24 2443245358 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3521205145 Sep 04 02:15:00 AM UTC 24 Sep 04 02:15:03 AM UTC 24 2045964303 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2750241459 Sep 04 02:15:01 AM UTC 24 Sep 04 02:15:04 AM UTC 24 2534535160 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.857942733 Sep 04 02:13:09 AM UTC 24 Sep 04 02:15:04 AM UTC 24 42012484596 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1069435403 Sep 04 02:14:57 AM UTC 24 Sep 04 02:15:05 AM UTC 24 4318192662 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1813267617 Sep 04 02:14:55 AM UTC 24 Sep 04 02:15:05 AM UTC 24 2187094608 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2032200737 Sep 04 02:13:06 AM UTC 24 Sep 04 02:15:05 AM UTC 24 154607082887 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.4126961837 Sep 04 02:15:00 AM UTC 24 Sep 04 02:15:05 AM UTC 24 2477412317 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.453009744 Sep 04 02:15:03 AM UTC 24 Sep 04 02:15:06 AM UTC 24 2705827297 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1270758651 Sep 04 02:15:00 AM UTC 24 Sep 04 02:15:06 AM UTC 24 2115822372 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3616582191 Sep 04 02:14:48 AM UTC 24 Sep 04 02:15:07 AM UTC 24 64867392088 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3149133412 Sep 04 02:15:02 AM UTC 24 Sep 04 02:15:07 AM UTC 24 8995871103 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.408924200 Sep 04 02:14:57 AM UTC 24 Sep 04 02:15:08 AM UTC 24 52277626929 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1469541470 Sep 04 02:15:05 AM UTC 24 Sep 04 02:15:09 AM UTC 24 2135268412 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3057160289 Sep 04 02:15:05 AM UTC 24 Sep 04 02:15:09 AM UTC 24 2472567147 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1658487736 Sep 04 02:14:56 AM UTC 24 Sep 04 02:15:09 AM UTC 24 3395051564 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2198594532 Sep 04 02:15:05 AM UTC 24 Sep 04 02:15:13 AM UTC 24 2009331553 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1373487493 Sep 04 02:14:54 AM UTC 24 Sep 04 02:15:10 AM UTC 24 9725890061 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3491437246 Sep 04 02:15:06 AM UTC 24 Sep 04 02:15:10 AM UTC 24 2062600652 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2644013689 Sep 04 02:14:56 AM UTC 24 Sep 04 02:15:11 AM UTC 24 3713993728 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.290027958 Sep 04 02:15:06 AM UTC 24 Sep 04 02:15:11 AM UTC 24 2636091557 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2517992792 Sep 04 02:15:01 AM UTC 24 Sep 04 02:15:12 AM UTC 24 2610789347 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1274437426 Sep 04 02:15:02 AM UTC 24 Sep 04 02:15:13 AM UTC 24 3429413989 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.4019490027 Sep 04 02:15:06 AM UTC 24 Sep 04 02:15:14 AM UTC 24 2512445645 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3559663839 Sep 04 02:15:11 AM UTC 24 Sep 04 02:15:14 AM UTC 24 2335194564 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.1953287576 Sep 04 02:15:08 AM UTC 24 Sep 04 02:15:15 AM UTC 24 5112559976 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.881888780 Sep 04 02:13:15 AM UTC 24 Sep 04 02:15:16 AM UTC 24 41559164374 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.376204556 Sep 04 02:14:59 AM UTC 24 Sep 04 02:15:16 AM UTC 24 11206961028 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4165246309 Sep 04 02:15:06 AM UTC 24 Sep 04 02:15:17 AM UTC 24 3609126686 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.264503766 Sep 04 02:15:10 AM UTC 24 Sep 04 02:15:17 AM UTC 24 2113646854 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2646238934 Sep 04 02:15:05 AM UTC 24 Sep 04 02:15:17 AM UTC 24 7466434688 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4130853406 Sep 04 02:15:13 AM UTC 24 Sep 04 02:15:17 AM UTC 24 3515233980 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.4132222917 Sep 04 02:15:13 AM UTC 24 Sep 04 02:15:18 AM UTC 24 8268514594 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2226609478 Sep 04 02:15:14 AM UTC 24 Sep 04 02:15:18 AM UTC 24 3723595204 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.8634676 Sep 04 02:15:12 AM UTC 24 Sep 04 02:15:18 AM UTC 24 2625755145 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.4017105525 Sep 04 02:15:10 AM UTC 24 Sep 04 02:15:19 AM UTC 24 2014409424 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3085704991 Sep 04 02:15:06 AM UTC 24 Sep 04 02:15:19 AM UTC 24 3672193716 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2897824247 Sep 04 02:15:17 AM UTC 24 Sep 04 02:15:20 AM UTC 24 2087275315 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1953093110 Sep 04 02:15:12 AM UTC 24 Sep 04 02:15:20 AM UTC 24 4665332614 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.1317442797 Sep 04 02:15:17 AM UTC 24 Sep 04 02:15:20 AM UTC 24 2135734753 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.4178135593 Sep 04 02:15:15 AM UTC 24 Sep 04 02:15:21 AM UTC 24 23750109325 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1565750209 Sep 04 02:15:18 AM UTC 24 Sep 04 02:15:22 AM UTC 24 2243954587 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1734925933 Sep 04 02:15:11 AM UTC 24 Sep 04 02:15:22 AM UTC 24 2510407714 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3696693438 Sep 04 02:15:18 AM UTC 24 Sep 04 02:15:22 AM UTC 24 2526685907 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2804949408 Sep 04 02:15:11 AM UTC 24 Sep 04 02:15:22 AM UTC 24 2477955094 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1522641770 Sep 04 02:15:10 AM UTC 24 Sep 04 02:15:22 AM UTC 24 13332134878 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1231217555 Sep 04 02:15:20 AM UTC 24 Sep 04 02:15:23 AM UTC 24 2878810965 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1773085315 Sep 04 02:14:21 AM UTC 24 Sep 04 02:15:24 AM UTC 24 83460901190 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.838907044 Sep 04 02:15:18 AM UTC 24 Sep 04 02:15:25 AM UTC 24 4118000267 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.227488335 Sep 04 02:15:22 AM UTC 24 Sep 04 02:15:27 AM UTC 24 2207867937 ps
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