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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 28 68 70.83 28
Automatically Generated Cross Bins 96 28 68 70.83 28
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * * [auto[1]] -- -- 16
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 72 1 T30 2 T31 1 T40 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 28 1 T33 1 T268 3 T377 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 51 1 T40 1 T289 1 T97 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 28 1 T32 1 T294 2 T218 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 47 1 T30 1 T42 1 T268 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 20 1 T33 1 T55 1 T103 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 45 1 T41 2 T289 1 T290 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 16 1 T32 1 T33 1 T287 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 45 1 T30 1 T96 2 T273 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 31 1 T103 1 T268 2 T287 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 40 1 T40 1 T42 1 T289 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 33 1 T33 1 T103 3 T287 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 50 1 T40 1 T289 1 T124 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 31 1 T32 1 T33 1 T55 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 34 1 T42 1 T41 1 T124 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 27 1 T33 1 T41 1 T268 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 55 1 T272 1 T315 1 T278 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 30 1 T32 3 T55 2 T103 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 55 1 T32 1 T42 1 T289 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 31 1 T33 1 T55 1 T294 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 56 1 T30 1 T271 1 T273 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 18 1 T32 1 T55 1 T268 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 74 1 T42 1 T271 1 T122 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 44 1 T33 1 T55 1 T103 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 57 1 T30 1 T42 1 T289 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 24 1 T32 1 T103 2 T294 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 30 1 T289 4 T272 1 T124 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 25 1 T55 2 T268 2 T218 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 60 1 T40 2 T289 1 T379 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 58 1 T33 2 T30 6 T55 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 79 1 T42 1 T289 1 T294 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 73 1 T32 1 T33 1 T103 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 48 1 T40 1 T42 1 T124 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 20 1 T33 2 T103 1 T268 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 70 1 T40 1 T42 1 T289 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 34 1 T32 2 T33 2 T55 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 40 1 T40 4 T56 1 T97 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 27 1 T103 1 T268 1 T288 3
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 38 1 T40 1 T42 2 T97 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 38 1 T32 1 T97 9 T294 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 42 1 T40 1 T42 1 T124 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 24 1 T32 1 T33 1 T55 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 22 1 T41 2 T124 1 T315 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 20 1 T55 1 T294 1 T287 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 26 1 T40 1 T289 1 T273 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 17 1 T55 1 T268 1 T218 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 64 1 T55 1 T56 1 T315 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 39 1 T103 2 T56 6 T287 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 39 1 T42 3 T289 1 T279 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 21 1 T32 2 T268 1 T294 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 48 1 T42 2 T271 1 T122 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 43 1 T32 1 T55 1 T103 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 34 1 T289 1 T124 1 T315 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 18 1 T32 1 T33 1 T55 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 63 1 T103 1 T42 1 T278 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 65 1 T32 1 T33 1 T55 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 32 1 T42 1 T289 2 T56 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 34 1 T103 1 T268 1 T377 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 80 1 T40 1 T127 3 T290 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 83 1 T32 1 T33 1 T41 8
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 41 1 T31 10 T40 1 T289 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 24 1 T268 1 T288 2 T383 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 166 1 T33 3 T40 10 T42 10
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 127 1 T55 4 T103 1 T294 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 2 1 T398 2 - - - -
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 1 1 T398 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T399 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 27 1 T268 6 T302 1 T383 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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