Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T178 |
11 |
| auto[1] |
9 |
1 |
|
|
T178 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T178 |
8 |
| auto[1] |
12 |
1 |
|
|
T178 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T178 |
14 |
| auto[1] |
6 |
1 |
|
|
T178 |
6 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T178 |
13 |
| auto[1] |
7 |
1 |
|
|
T178 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T178 |
14 |
| auto[1] |
6 |
1 |
|
|
T178 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T178 |
10 |
| auto[1] |
10 |
1 |
|
|
T178 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
6 |
1 |
|
|
T178 |
6 |
| auto[1] |
14 |
1 |
|
|
T178 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T178 |
11 |
| auto[1] |
9 |
1 |
|
|
T178 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T178 |
13 |
| auto[1] |
7 |
1 |
|
|
T178 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T178 |
12 |
| auto[1] |
8 |
1 |
|
|
T178 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T178 |
7 |
| auto[1] |
13 |
1 |
|
|
T178 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T178 |
11 |
| auto[1] |
9 |
1 |
|
|
T178 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T178 |
8 |
| auto[1] |
12 |
1 |
|
|
T178 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
11 |
1 |
|
|
T178 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T178 |
11 |
| auto[1] |
9 |
1 |
|
|
T178 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T178 |
12 |
| auto[1] |
8 |
1 |
|
|
T178 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
1 |
1 |
|
|
T178 |
1 |
| auto[0] |
auto[1] |
8 |
1 |
|
|
T178 |
8 |
| auto[1] |
auto[0] |
7 |
1 |
|
|
T178 |
7 |
| auto[1] |
auto[1] |
4 |
1 |
|
|
T178 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
3 |
1 |
|
|
T178 |
3 |
| auto[0] |
auto[1] |
4 |
1 |
|
|
T178 |
4 |
| auto[1] |
auto[0] |
11 |
1 |
|
|
T178 |
11 |
| auto[1] |
auto[1] |
2 |
1 |
|
|
T178 |
2 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T178 |
5 |
| auto[0] |
auto[1] |
4 |
1 |
|
|
T178 |
4 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T178 |
4 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T178 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
7 |
1 |
|
|
T178 |
7 |
| auto[0] |
auto[1] |
2 |
1 |
|
|
T178 |
2 |
| auto[1] |
auto[0] |
6 |
1 |
|
|
T178 |
6 |
| auto[1] |
auto[1] |
5 |
1 |
|
|
T178 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for key2_inXval
Uncovered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[0]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T178 |
5 |
| auto[1] |
auto[1] |
6 |
1 |
|
|
T178 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T178 |
8 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T178 |
3 |
| auto[1] |
auto[0] |
2 |
1 |
|
|
T178 |
2 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T178 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
4 |
1 |
|
|
T178 |
4 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T178 |
5 |
| auto[1] |
auto[0] |
7 |
1 |
|
|
T178 |
7 |
| auto[1] |
auto[1] |
4 |
1 |
|
|
T178 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
6 |
1 |
|
|
T178 |
6 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T178 |
5 |
| auto[1] |
auto[0] |
7 |
1 |
|
|
T178 |
7 |
| auto[1] |
auto[1] |
2 |
1 |
|
|
T178 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
6 |
1 |
|
|
T178 |
6 |
| auto[0] |
auto[1] |
3 |
1 |
|
|
T178 |
3 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T178 |
5 |
| auto[1] |
auto[1] |
6 |
1 |
|
|
T178 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
9 |
1 |
|
|
T178 |
9 |
| auto[1] |
auto[1] |
11 |
1 |
|
|
T178 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
2 |
1 |
|
|
T178 |
2 |
| auto[0] |
auto[1] |
6 |
1 |
|
|
T178 |
6 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T178 |
4 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T178 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
12 |
1 |
|
|
T178 |
12 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T178 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
721 |
1 |
|
|
T14 |
9 |
|
T22 |
10 |
|
T23 |
14 |
| auto[1] |
679 |
1 |
|
|
T14 |
11 |
|
T22 |
10 |
|
T23 |
6 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
734 |
1 |
|
|
T14 |
9 |
|
T22 |
11 |
|
T23 |
10 |
| auto[1] |
666 |
1 |
|
|
T14 |
11 |
|
T22 |
9 |
|
T23 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
687 |
1 |
|
|
T14 |
8 |
|
T22 |
10 |
|
T23 |
9 |
| auto[1] |
713 |
1 |
|
|
T14 |
12 |
|
T22 |
10 |
|
T23 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
710 |
1 |
|
|
T14 |
14 |
|
T22 |
10 |
|
T23 |
9 |
| auto[1] |
690 |
1 |
|
|
T14 |
6 |
|
T22 |
10 |
|
T23 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
703 |
1 |
|
|
T14 |
12 |
|
T22 |
9 |
|
T23 |
12 |
| auto[1] |
697 |
1 |
|
|
T14 |
8 |
|
T22 |
11 |
|
T23 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
727 |
1 |
|
|
T14 |
8 |
|
T22 |
11 |
|
T23 |
8 |
| auto[1] |
673 |
1 |
|
|
T14 |
12 |
|
T22 |
9 |
|
T23 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
692 |
1 |
|
|
T14 |
8 |
|
T22 |
12 |
|
T23 |
11 |
| auto[1] |
708 |
1 |
|
|
T14 |
12 |
|
T22 |
8 |
|
T23 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
700 |
1 |
|
|
T14 |
11 |
|
T22 |
12 |
|
T23 |
9 |
| auto[1] |
700 |
1 |
|
|
T14 |
9 |
|
T22 |
8 |
|
T23 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
695 |
1 |
|
|
T14 |
10 |
|
T22 |
13 |
|
T23 |
11 |
| auto[1] |
705 |
1 |
|
|
T14 |
10 |
|
T22 |
7 |
|
T23 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
680 |
1 |
|
|
T14 |
13 |
|
T22 |
9 |
|
T23 |
8 |
| auto[1] |
720 |
1 |
|
|
T14 |
7 |
|
T22 |
11 |
|
T23 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
732 |
1 |
|
|
T14 |
10 |
|
T22 |
8 |
|
T23 |
12 |
| auto[1] |
668 |
1 |
|
|
T14 |
10 |
|
T22 |
12 |
|
T23 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
705 |
1 |
|
|
T14 |
9 |
|
T22 |
10 |
|
T23 |
11 |
| auto[1] |
695 |
1 |
|
|
T14 |
11 |
|
T22 |
10 |
|
T23 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
725 |
1 |
|
|
T14 |
11 |
|
T22 |
9 |
|
T23 |
9 |
| auto[1] |
675 |
1 |
|
|
T14 |
9 |
|
T22 |
11 |
|
T23 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
734 |
1 |
|
|
T14 |
9 |
|
T22 |
11 |
|
T23 |
10 |
| auto[1] |
666 |
1 |
|
|
T14 |
11 |
|
T22 |
9 |
|
T23 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
698 |
1 |
|
|
T14 |
7 |
|
T22 |
10 |
|
T23 |
8 |
| auto[1] |
702 |
1 |
|
|
T14 |
13 |
|
T22 |
10 |
|
T23 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
719 |
1 |
|
|
T14 |
13 |
|
T22 |
6 |
|
T23 |
12 |
| auto[1] |
681 |
1 |
|
|
T14 |
7 |
|
T22 |
14 |
|
T23 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
696 |
1 |
|
|
T14 |
12 |
|
T22 |
10 |
|
T23 |
6 |
| auto[1] |
704 |
1 |
|
|
T14 |
8 |
|
T22 |
10 |
|
T23 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
684 |
1 |
|
|
T14 |
8 |
|
T22 |
10 |
|
T23 |
12 |
| auto[1] |
716 |
1 |
|
|
T14 |
12 |
|
T22 |
10 |
|
T23 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
728 |
1 |
|
|
T14 |
8 |
|
T22 |
10 |
|
T23 |
11 |
| auto[1] |
672 |
1 |
|
|
T14 |
12 |
|
T22 |
10 |
|
T23 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
714 |
1 |
|
|
T14 |
11 |
|
T22 |
10 |
|
T23 |
7 |
| auto[1] |
686 |
1 |
|
|
T14 |
9 |
|
T22 |
10 |
|
T23 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
689 |
1 |
|
|
T14 |
9 |
|
T22 |
10 |
|
T23 |
13 |
| auto[1] |
711 |
1 |
|
|
T14 |
11 |
|
T22 |
10 |
|
T23 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
719 |
1 |
|
|
T14 |
9 |
|
T22 |
9 |
|
T23 |
13 |
| auto[1] |
681 |
1 |
|
|
T14 |
11 |
|
T22 |
11 |
|
T23 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
721 |
1 |
|
|
T14 |
10 |
|
T22 |
12 |
|
T23 |
9 |
| auto[1] |
679 |
1 |
|
|
T14 |
10 |
|
T22 |
8 |
|
T23 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
705 |
1 |
|
|
T14 |
9 |
|
T22 |
10 |
|
T23 |
11 |
| auto[1] |
695 |
1 |
|
|
T14 |
11 |
|
T22 |
10 |
|
T23 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
334 |
1 |
|
|
T14 |
5 |
|
T22 |
4 |
|
T23 |
3 |
| auto[0] |
auto[1] |
364 |
1 |
|
|
T14 |
2 |
|
T22 |
6 |
|
T23 |
5 |
| auto[1] |
auto[0] |
353 |
1 |
|
|
T14 |
3 |
|
T22 |
6 |
|
T23 |
6 |
| auto[1] |
auto[1] |
349 |
1 |
|
|
T14 |
10 |
|
T22 |
4 |
|
T23 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
356 |
1 |
|
|
T14 |
11 |
|
T22 |
2 |
|
T23 |
5 |
| auto[0] |
auto[1] |
363 |
1 |
|
|
T14 |
2 |
|
T22 |
4 |
|
T23 |
7 |
| auto[1] |
auto[0] |
354 |
1 |
|
|
T14 |
3 |
|
T22 |
8 |
|
T23 |
4 |
| auto[1] |
auto[1] |
327 |
1 |
|
|
T14 |
4 |
|
T22 |
6 |
|
T23 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
334 |
1 |
|
|
T14 |
6 |
|
T22 |
5 |
|
T23 |
4 |
| auto[0] |
auto[1] |
362 |
1 |
|
|
T14 |
6 |
|
T22 |
5 |
|
T23 |
2 |
| auto[1] |
auto[0] |
369 |
1 |
|
|
T14 |
6 |
|
T22 |
4 |
|
T23 |
8 |
| auto[1] |
auto[1] |
335 |
1 |
|
|
T14 |
2 |
|
T22 |
6 |
|
T23 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
340 |
1 |
|
|
T14 |
2 |
|
T22 |
6 |
|
T23 |
5 |
| auto[0] |
auto[1] |
344 |
1 |
|
|
T14 |
6 |
|
T22 |
4 |
|
T23 |
7 |
| auto[1] |
auto[0] |
387 |
1 |
|
|
T14 |
6 |
|
T22 |
5 |
|
T23 |
3 |
| auto[1] |
auto[1] |
329 |
1 |
|
|
T14 |
6 |
|
T22 |
5 |
|
T23 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
373 |
1 |
|
|
T14 |
3 |
|
T22 |
8 |
|
T23 |
9 |
| auto[0] |
auto[1] |
355 |
1 |
|
|
T14 |
5 |
|
T22 |
2 |
|
T23 |
2 |
| auto[1] |
auto[0] |
319 |
1 |
|
|
T14 |
5 |
|
T22 |
4 |
|
T23 |
2 |
| auto[1] |
auto[1] |
353 |
1 |
|
|
T14 |
7 |
|
T22 |
6 |
|
T23 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
370 |
1 |
|
|
T14 |
6 |
|
T22 |
8 |
|
T23 |
6 |
| auto[0] |
auto[1] |
344 |
1 |
|
|
T14 |
5 |
|
T22 |
2 |
|
T23 |
1 |
| auto[1] |
auto[0] |
330 |
1 |
|
|
T14 |
5 |
|
T22 |
4 |
|
T23 |
3 |
| auto[1] |
auto[1] |
356 |
1 |
|
|
T14 |
4 |
|
T22 |
6 |
|
T23 |
10 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
347 |
1 |
|
|
T14 |
8 |
|
T22 |
5 |
|
T23 |
5 |
| auto[0] |
auto[1] |
372 |
1 |
|
|
T14 |
1 |
|
T22 |
4 |
|
T23 |
8 |
| auto[1] |
auto[0] |
333 |
1 |
|
|
T14 |
5 |
|
T22 |
4 |
|
T23 |
3 |
| auto[1] |
auto[1] |
348 |
1 |
|
|
T14 |
6 |
|
T22 |
7 |
|
T23 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
374 |
1 |
|
|
T14 |
7 |
|
T22 |
6 |
|
T23 |
5 |
| auto[0] |
auto[1] |
347 |
1 |
|
|
T14 |
3 |
|
T22 |
6 |
|
T23 |
4 |
| auto[1] |
auto[0] |
358 |
1 |
|
|
T14 |
3 |
|
T22 |
2 |
|
T23 |
7 |
| auto[1] |
auto[1] |
321 |
1 |
|
|
T14 |
7 |
|
T22 |
6 |
|
T23 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
370 |
1 |
|
|
T14 |
5 |
|
T22 |
4 |
|
T23 |
6 |
| auto[0] |
auto[1] |
355 |
1 |
|
|
T14 |
6 |
|
T22 |
5 |
|
T23 |
3 |
| auto[1] |
auto[0] |
351 |
1 |
|
|
T14 |
4 |
|
T22 |
6 |
|
T23 |
8 |
| auto[1] |
auto[1] |
324 |
1 |
|
|
T14 |
5 |
|
T22 |
5 |
|
T23 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
734 |
1 |
|
|
T14 |
9 |
|
T22 |
11 |
|
T23 |
10 |
| auto[1] |
auto[1] |
666 |
1 |
|
|
T14 |
11 |
|
T22 |
9 |
|
T23 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
355 |
1 |
|
|
T14 |
5 |
|
T22 |
7 |
|
T23 |
7 |
| auto[0] |
auto[1] |
334 |
1 |
|
|
T14 |
4 |
|
T22 |
3 |
|
T23 |
6 |
| auto[1] |
auto[0] |
340 |
1 |
|
|
T14 |
5 |
|
T22 |
6 |
|
T23 |
4 |
| auto[1] |
auto[1] |
371 |
1 |
|
|
T14 |
6 |
|
T22 |
4 |
|
T23 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
705 |
1 |
|
|
T14 |
9 |
|
T22 |
10 |
|
T23 |
11 |
| auto[1] |
auto[1] |
695 |
1 |
|
|
T14 |
11 |
|
T22 |
10 |
|
T23 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T194 |
8 |
| auto[1] |
12 |
1 |
|
|
T194 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T194 |
8 |
| auto[1] |
12 |
1 |
|
|
T194 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T194 |
10 |
| auto[1] |
10 |
1 |
|
|
T194 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T194 |
11 |
| auto[1] |
9 |
1 |
|
|
T194 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T194 |
12 |
| auto[1] |
8 |
1 |
|
|
T194 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
6 |
1 |
|
|
T194 |
6 |
| auto[1] |
14 |
1 |
|
|
T194 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T194 |
9 |
| auto[1] |
11 |
1 |
|
|
T194 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T194 |
9 |
| auto[1] |
11 |
1 |
|
|
T194 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T194 |
10 |
| auto[1] |
10 |
1 |
|
|
T194 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T194 |
12 |
| auto[1] |
8 |
1 |
|
|
T194 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T194 |
11 |
| auto[1] |
9 |
1 |
|
|
T194 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T194 |
9 |
| auto[1] |
11 |
1 |
|
|
T194 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
4 |
1 |
|
|
T194 |
4 |
| auto[1] |
16 |
1 |
|
|
T194 |
16 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T194 |
8 |
| auto[1] |
12 |
1 |
|
|
T194 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T194 |
11 |
| auto[1] |
9 |
1 |
|
|
T194 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T194 |
8 |
| auto[1] |
12 |
1 |
|
|
T194 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T194 |
7 |
| auto[1] |
13 |
1 |
|
|
T194 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T194 |
9 |
| auto[1] |
11 |
1 |
|
|
T194 |
11 |