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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	920	920	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	1214224016	3291389	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	1214223444	5763	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	1214224016	10516611	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	1214224016	189195	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	1214223444	5953	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	1214224016	12468079	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	1214224016	578367	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	1214224016	12468079	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	1214224016	578367	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	1214224016	578367	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	1214224016	578367	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	1214223444	3667	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	1214223444	3443	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	920	920	0	0
tb.dut.u_reg.en2addrHit	0	0	1214223444	245811	0	0
tb.dut.u_reg.reAfterRv	0	0	1214223444	245811	0	0
tb.dut.u_reg.rePulse	0	0	1214223444	130815	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A	0	0	1214223444	961937	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A	0	0	1214223444	1099	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1099	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1099	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1043	0	0
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1107	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A	0	0	1214223444	865742	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A	0	0	1214223444	982	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	982	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	982	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	924	0	0
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	992	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	920	920	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A	0	0	1214223444	1646561	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A	0	0	1214223444	1757	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1757	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1757	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1701	0	0
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1766	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A	0	0	1214223444	1643886	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A	0	0	1214223444	1739	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1739	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1739	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1683	0	0
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1749	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A	0	0	1214223444	1643192	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A	0	0	1214223444	1756	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1756	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1756	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1698	0	0
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1764	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A	0	0	1214223444	1614043	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A	0	0	1214223444	1737	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1737	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1737	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1679	0	0
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1745	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A	0	0	1214223444	1682878	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A	0	0	1214223444	1794	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1794	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1794	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1737	0	0
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1804	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A	0	0	1214223444	1603851	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A	0	0	1214223444	1729	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1729	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1729	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1676	0	0
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1739	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A	0	0	1214223444	1625882	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A	0	0	1214223444	1759	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1759	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1759	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1704	0	0
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1768	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A	0	0	1214223444	1580380	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A	0	0	1214223444	1728	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1728	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1728	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1673	0	0
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1736	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A	0	0	1214223444	1108857	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A	0	0	1214223444	1174	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1174	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1174	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1116	0	0
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1185	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A	0	0	1214223444	1072110	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A	0	0	1214223444	1164	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1164	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1164	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1108	0	0
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1173	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A	0	0	1214223444	1069078	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A	0	0	1214223444	1150	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1150	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1150	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1091	0	0
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1161	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A	0	0	1214223444	1099603	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A	0	0	1214223444	1169	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1169	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1169	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1111	0	0
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1177	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A	0	0	1214223444	7196039	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A	0	0	1214223444	7357	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7357	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7357	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7298	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7365	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A	0	0	1214223444	6871612	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A	0	0	1214223444	7149	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7149	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7149	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7091	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7158	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A	0	0	1214223444	6710434	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A	0	0	1214223444	7085	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7085	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7085	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7025	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7093	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A	0	0	1214223444	6781178	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A	0	0	1214223444	7179	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7179	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7179	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7116	0	0
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7187	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A	0	0	1214223444	7801740	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A	0	0	1214223444	7977	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7977	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7977	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7919	0	0
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7986	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A	0	0	1214223444	7465676	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A	0	0	1214223444	7695	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7695	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7695	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7632	0	0
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7705	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A	0	0	1214223444	7324390	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A	0	0	1214223444	7682	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7682	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7682	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7623	0	0
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7694	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A	0	0	1214223444	7353616	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A	0	0	1214223444	7742	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	7742	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	7742	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	7685	0	0
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	7753	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A	0	0	1214223444	1719073	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A	0	0	1214223444	1862	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	1214223444	1862	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	6609339	1862	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	6609339	1806	0	0
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	1214223444	1873	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A	0	0	1214223444	877292	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A	0	0	6609339	5936348	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A	0	0	1214223444	942	0	0
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A	0	0	1214223444	1213769184	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1028	0	10
Category 0	1028	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1028	0	10
Severity 0	1028	0	10

	NUMBER	PERCENT
Total Number	1028	100.00
Uncovered	6	0.58
Success	1022	99.42
Failure	0	0.00
Incomplete	1	0.10
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	0	0.00
All Matches	10	100.00
First Matches	10	100.00