Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.22 98.71 97.98 100.00 93.59 98.93 99.42 91.88


Total tests in report: 920
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.10 46.10 63.63 63.63 45.11 45.11 83.79 83.79 7.69 7.69 67.02 67.02 52.02 52.02 3.44 3.44 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.993879304
70.81 24.71 85.71 22.08 73.02 27.91 89.27 5.48 71.15 63.46 86.06 19.04 83.82 31.79 6.64 3.20 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.130077016
75.78 4.97 91.62 5.92 80.46 7.43 91.32 2.05 71.15 0.00 92.42 6.36 85.74 1.93 17.77 11.13 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.4064798530
79.42 3.63 93.26 1.64 83.16 2.71 92.01 0.68 71.15 0.00 93.94 1.52 89.79 4.05 32.60 14.82 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4233866354
81.58 2.16 95.75 2.48 88.24 5.08 93.49 1.48 71.79 0.64 96.64 2.70 92.49 2.70 32.66 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.602655471
83.69 2.11 96.27 0.52 89.03 0.78 93.72 0.23 71.79 0.00 96.64 0.00 92.58 0.10 45.82 13.16 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3440097481
85.35 1.66 97.13 0.86 90.04 1.01 94.75 1.03 77.56 5.77 97.30 0.67 94.61 2.02 46.06 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.435867992
86.43 1.08 97.13 0.00 90.09 0.05 94.75 0.00 77.56 0.00 97.30 0.00 94.80 0.19 53.38 7.32 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2432445165
87.40 0.97 97.13 0.00 90.95 0.86 94.75 0.00 77.56 0.00 97.30 0.00 95.28 0.48 58.86 5.47 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2524311590
88.35 0.94 97.26 0.13 91.40 0.46 94.75 0.00 77.56 0.00 97.34 0.04 95.47 0.19 64.64 5.78 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1436141868
89.21 0.86 97.52 0.26 92.19 0.78 94.75 0.00 79.49 1.92 97.63 0.30 96.53 1.06 66.36 1.72 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.555177582
89.82 0.61 97.52 0.00 94.03 1.85 96.58 1.83 79.49 0.00 97.67 0.04 96.53 0.00 66.91 0.55 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2194084681
90.34 0.53 97.63 0.11 94.08 0.05 96.58 0.00 79.49 0.00 97.71 0.04 96.63 0.10 70.30 3.38 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3931661666
90.81 0.46 97.70 0.07 94.26 0.18 96.58 0.00 82.05 2.56 97.86 0.15 96.92 0.29 70.30 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1872045643
91.24 0.44 97.72 0.02 94.34 0.08 99.09 2.51 82.05 0.00 97.89 0.04 97.01 0.10 70.60 0.31 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.76425790
91.58 0.34 97.89 0.17 94.51 0.18 99.09 0.00 82.05 0.00 97.97 0.07 97.01 0.00 72.57 1.97 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1890360694
91.88 0.30 97.91 0.02 94.54 0.03 99.09 0.00 82.05 0.00 97.97 0.00 97.01 0.00 74.60 2.03 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3725438993
92.17 0.29 97.91 0.00 95.70 1.16 99.09 0.00 82.05 0.00 97.97 0.00 97.01 0.00 75.46 0.86 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1393530114
92.44 0.27 98.02 0.11 95.78 0.08 99.09 0.00 83.33 1.28 98.11 0.15 97.21 0.19 75.52 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3469685165
92.69 0.25 98.06 0.04 95.95 0.18 99.09 0.00 84.62 1.28 98.19 0.07 97.40 0.19 75.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2198650120
92.94 0.25 98.10 0.04 95.95 0.00 99.09 0.00 84.62 0.00 98.19 0.00 97.40 0.00 77.24 1.72 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.4011785227
93.19 0.25 98.13 0.04 96.06 0.10 99.09 0.00 84.62 0.00 98.26 0.07 97.40 0.00 78.78 1.54 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3783032278
93.43 0.24 98.21 0.07 96.13 0.08 99.09 0.00 85.90 1.28 98.34 0.07 97.59 0.19 78.78 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.230738414
93.67 0.24 98.28 0.07 96.18 0.05 99.09 0.00 87.18 1.28 98.41 0.07 97.78 0.19 78.78 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3295773016
93.90 0.23 98.28 0.00 96.81 0.63 99.32 0.23 87.18 0.00 98.45 0.04 97.88 0.10 79.40 0.62 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1927712477
94.12 0.22 98.34 0.06 96.84 0.03 99.32 0.00 88.46 1.28 98.52 0.07 97.98 0.10 79.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3592308271
94.32 0.20 98.34 0.00 96.84 0.00 99.32 0.00 88.46 0.00 98.52 0.00 97.98 0.00 80.81 1.41 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.3853052388
94.52 0.19 98.36 0.02 96.84 0.00 99.32 0.00 88.46 0.00 98.56 0.04 97.98 0.00 82.10 1.29 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2556510738
94.70 0.18 98.36 0.00 96.92 0.08 99.77 0.46 88.46 0.00 98.56 0.00 98.36 0.39 82.47 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2359821612
94.86 0.16 98.36 0.00 96.92 0.00 99.77 0.00 88.46 0.00 98.56 0.00 98.36 0.00 83.58 1.11 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.697594900
95.00 0.15 98.40 0.04 96.94 0.03 99.77 0.00 89.10 0.64 98.60 0.04 98.46 0.10 83.76 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.754194580
95.14 0.14 98.45 0.06 96.99 0.05 99.77 0.00 89.74 0.64 98.67 0.07 98.55 0.10 83.83 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.97581640
95.28 0.13 98.45 0.00 97.07 0.08 99.77 0.00 90.38 0.64 98.67 0.00 98.65 0.10 83.95 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1662491936
95.40 0.12 98.47 0.02 97.22 0.15 99.77 0.00 90.38 0.00 98.74 0.07 98.84 0.19 84.38 0.43 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1013605880
95.52 0.12 98.51 0.04 97.24 0.03 99.77 0.00 91.03 0.64 98.78 0.04 98.94 0.10 84.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.2656725073
95.64 0.12 98.54 0.04 97.27 0.03 99.77 0.00 91.67 0.64 98.82 0.04 99.04 0.10 84.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.1772212666
95.76 0.12 98.58 0.04 97.29 0.03 99.77 0.00 92.31 0.64 98.85 0.04 99.13 0.10 84.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1141426305
95.87 0.11 98.58 0.00 97.29 0.00 99.77 0.00 92.31 0.00 98.85 0.00 99.13 0.00 85.18 0.80 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2936815757
95.98 0.11 98.58 0.00 97.29 0.00 99.77 0.00 92.31 0.00 98.85 0.00 99.13 0.00 85.92 0.74 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2040362654
96.08 0.10 98.60 0.02 97.29 0.00 99.77 0.00 92.95 0.64 98.89 0.04 99.13 0.00 85.92 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3199279638
96.18 0.10 98.62 0.02 97.29 0.00 99.77 0.00 93.59 0.64 98.93 0.04 99.13 0.00 85.92 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2037031377
96.28 0.10 98.62 0.00 97.29 0.00 99.77 0.00 93.59 0.00 98.93 0.00 99.13 0.00 86.59 0.68 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.251074076
96.36 0.08 98.62 0.00 97.37 0.08 99.77 0.00 93.59 0.00 98.93 0.00 99.13 0.00 87.08 0.49 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.858290860
96.42 0.07 98.68 0.06 97.50 0.13 100.00 0.23 93.59 0.00 98.93 0.00 99.13 0.00 87.15 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1258658730
96.49 0.06 98.68 0.00 97.50 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.13 0.00 87.58 0.43 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3201828909
96.54 0.06 98.68 0.00 97.52 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.13 0.00 87.95 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1173247825
96.59 0.05 98.68 0.00 97.52 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.13 0.00 88.31 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.2345186472
96.65 0.05 98.68 0.00 97.52 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.13 0.00 88.68 0.37 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2836073096
96.69 0.04 98.68 0.00 97.52 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.13 0.00 88.99 0.31 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.74981856
96.74 0.04 98.68 0.00 97.55 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.23 0.10 89.18 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3540063768
96.77 0.04 98.71 0.04 97.55 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.33 0.10 89.30 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3596813107
96.81 0.04 98.71 0.00 97.55 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.33 0.00 89.54 0.25 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.548444521
96.84 0.03 98.71 0.00 97.65 0.10 100.00 0.00 93.59 0.00 98.93 0.00 99.33 0.00 89.67 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2538329874
96.87 0.03 98.71 0.00 97.65 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.33 0.00 89.85 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.2444608703
96.89 0.03 98.71 0.00 97.65 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.33 0.00 90.04 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2375921495
96.92 0.03 98.71 0.00 97.65 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.33 0.00 90.22 0.18 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.480832877
96.94 0.02 98.71 0.00 97.70 0.05 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.10 90.22 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3737882821
96.96 0.02 98.71 0.00 97.70 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.34 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1948700553
96.97 0.02 98.71 0.00 97.70 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.47 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1806165888
96.99 0.02 98.71 0.00 97.70 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.59 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4017072257
97.01 0.02 98.71 0.00 97.70 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.71 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1630819565
97.03 0.02 98.71 0.00 97.70 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.84 0.12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3592232718
97.04 0.01 98.71 0.00 97.80 0.10 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.84 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.1434208609
97.05 0.01 98.71 0.00 97.83 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.90 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2749752367
97.07 0.01 98.71 0.00 97.85 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 90.96 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3272204131
97.07 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.02 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2113510809
97.08 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.08 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2812729038
97.09 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.14 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.250001859
97.10 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.21 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1609436404
97.11 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.27 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.268611251
97.12 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.33 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.814479637
97.13 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.39 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.160787089
97.14 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.45 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.524171759
97.15 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.51 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3731470405
97.15 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.57 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3433462787
97.16 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.64 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2024962742
97.17 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.70 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3145455163
97.18 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.76 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.881125776
97.19 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.82 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1518407305
97.20 0.01 98.71 0.00 97.85 0.00 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.88 0.06 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.139200823
97.21 0.01 98.71 0.00 97.90 0.05 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3219480284
97.21 0.01 98.71 0.00 97.93 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.320995012
97.21 0.01 98.71 0.00 97.95 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1005498967
97.22 0.01 98.71 0.00 97.98 0.03 100.00 0.00 93.59 0.00 98.93 0.00 99.42 0.00 91.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1461517083

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.713362689
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.795837906
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2735581650
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1786555303
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2567283655
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.25554265
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2723943617
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2033031541
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.970585074
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1909476793
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2084865082
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2129294210
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2015108898
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3146159825
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1362874399
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3647485513
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3192297423
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1471376065
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3204941871
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.867500763
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1076214677
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1775616339
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.234964822
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2296490783
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3433101871
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3899360973
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.81265389
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2971258914
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.793876773
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2677848342
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3658271050
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2175837404
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3728815491
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.66458088
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1919119361
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2408752274
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2711470158
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3110386134
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3953477727
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.10285238
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.4001685240
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1080306189
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1866908021
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2485236157
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1622246104
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2952019319
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.966389743
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3147093967
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2474948993
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1025477279
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1333228359
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1748715969
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2100167856
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2294167306
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2625238869
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2270993271
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.664754420
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2830103714
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.4139903957
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.384858703
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2021076687
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3590741850
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1921946824
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.751941933
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.384952201
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1580227848
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.675469820
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.490159073
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3645325542
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.4144615882
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2451210296
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.146465319
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2740771434
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4221382711
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.425669663
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.4094866257
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2745345870
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2902856897
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3930711040
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1267465918
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3983091651
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1990906611
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2131971832
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1649622666
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2142620643
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.4049303262
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2684146698
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.4185303685
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3694442611
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.696524650
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2741934425
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1961291935
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1389281130
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.84905136
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.981311615
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3691864483
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.749793993
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3304409592
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2033430270
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1716048840
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1709637956
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.4278814457
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3560272057
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2139659805
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.715528795
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3230996599
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3530417151
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2620253271
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.786527471
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1509952446
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.76938020
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2768133993
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3626635043
/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2626902651
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/workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3093876316



Total test records in report: 920
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1032843169 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:28 AM UTC 24 2237983966 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2784670782 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:29 AM UTC 24 2469204181 ps
T1 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1728687382 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:29 AM UTC 24 2425602441 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.602655471 Sep 09 07:09:27 AM UTC 24 Sep 09 07:09:31 AM UTC 24 2430317825 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.871137787 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:31 AM UTC 24 4114147721 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.2680547728 Sep 09 07:09:27 AM UTC 24 Sep 09 07:09:31 AM UTC 24 2472595915 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.993879304 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:31 AM UTC 24 3362053603 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4114558304 Sep 09 07:09:23 AM UTC 24 Sep 09 07:09:32 AM UTC 24 2111275892 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.4064798530 Sep 09 07:09:28 AM UTC 24 Sep 09 07:09:32 AM UTC 24 2523594712 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3798272898 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:32 AM UTC 24 2539478007 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2638891580 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:32 AM UTC 24 3325509456 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3445307982 Sep 09 07:09:29 AM UTC 24 Sep 09 07:09:33 AM UTC 24 3588467895 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2040362654 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:33 AM UTC 24 2515896891 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3352726019 Sep 09 07:09:26 AM UTC 24 Sep 09 07:09:33 AM UTC 24 6156040554 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1258658730 Sep 09 07:09:26 AM UTC 24 Sep 09 07:09:34 AM UTC 24 2011307028 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.200008984 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:34 AM UTC 24 2609184846 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.2576843193 Sep 09 07:09:27 AM UTC 24 Sep 09 07:09:35 AM UTC 24 2111889618 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3055445813 Sep 09 07:09:32 AM UTC 24 Sep 09 07:09:35 AM UTC 24 2136874396 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.2293252839 Sep 09 07:09:27 AM UTC 24 Sep 09 07:09:36 AM UTC 24 2154666111 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1495368704 Sep 09 07:09:27 AM UTC 24 Sep 09 07:09:37 AM UTC 24 2530834023 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1973643091 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:37 AM UTC 24 4717155806 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.80277388 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:37 AM UTC 24 2441553436 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.849350397 Sep 09 07:09:28 AM UTC 24 Sep 09 07:09:38 AM UTC 24 2610594781 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.3920595206 Sep 09 07:09:35 AM UTC 24 Sep 09 07:09:39 AM UTC 24 2024987861 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.147310949 Sep 09 07:09:35 AM UTC 24 Sep 09 07:09:39 AM UTC 24 2139196262 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.2937927614 Sep 09 07:09:32 AM UTC 24 Sep 09 07:09:39 AM UTC 24 2011448768 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.636753569 Sep 09 07:09:35 AM UTC 24 Sep 09 07:09:39 AM UTC 24 2483839862 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3925538750 Sep 09 07:09:28 AM UTC 24 Sep 09 07:09:39 AM UTC 24 3517137882 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1862007399 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:39 AM UTC 24 2630050058 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.1977223311 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:40 AM UTC 24 2518272083 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.1609436404 Sep 09 07:09:25 AM UTC 24 Sep 09 07:09:40 AM UTC 24 5123993153 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2348960574 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:41 AM UTC 24 2503616450 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3643952916 Sep 09 07:09:36 AM UTC 24 Sep 09 07:09:42 AM UTC 24 2436927397 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2298120265 Sep 09 07:09:33 AM UTC 24 Sep 09 07:09:42 AM UTC 24 2465921852 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3199279638 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:43 AM UTC 24 3090199171 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3651981346 Sep 09 07:09:32 AM UTC 24 Sep 09 07:09:43 AM UTC 24 22157771744 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3085890021 Sep 09 07:09:40 AM UTC 24 Sep 09 07:09:43 AM UTC 24 2028923329 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.4057968137 Sep 09 07:09:30 AM UTC 24 Sep 09 07:09:44 AM UTC 24 4309864822 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1296181060 Sep 09 07:09:38 AM UTC 24 Sep 09 07:09:44 AM UTC 24 3625198534 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.372867061 Sep 09 07:09:36 AM UTC 24 Sep 09 07:09:44 AM UTC 24 2124197212 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1927712477 Sep 09 07:09:36 AM UTC 24 Sep 09 07:09:44 AM UTC 24 2515246779 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3496439456 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:45 AM UTC 24 2170078665 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.610863786 Sep 09 07:09:36 AM UTC 24 Sep 09 07:09:45 AM UTC 24 2503565193 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1161968714 Sep 09 07:09:41 AM UTC 24 Sep 09 07:09:46 AM UTC 24 2406794704 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3258765852 Sep 09 07:09:28 AM UTC 24 Sep 09 07:09:47 AM UTC 24 4611601197 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2071892718 Sep 09 07:09:40 AM UTC 24 Sep 09 07:09:47 AM UTC 24 2112908772 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4275932978 Sep 09 07:09:41 AM UTC 24 Sep 09 07:09:47 AM UTC 24 2465075602 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3251641438 Sep 09 07:09:36 AM UTC 24 Sep 09 07:09:48 AM UTC 24 2608014372 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.379572069 Sep 09 07:09:38 AM UTC 24 Sep 09 07:09:48 AM UTC 24 6063221435 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1055892008 Sep 09 07:09:43 AM UTC 24 Sep 09 07:09:49 AM UTC 24 3320401605 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2343601247 Sep 09 07:09:38 AM UTC 24 Sep 09 07:09:49 AM UTC 24 3993524725 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.4153969117 Sep 09 07:09:30 AM UTC 24 Sep 09 07:09:49 AM UTC 24 13961214616 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2538329874 Sep 09 07:09:43 AM UTC 24 Sep 09 07:09:49 AM UTC 24 2535714975 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1501746648 Sep 09 07:09:41 AM UTC 24 Sep 09 07:09:49 AM UTC 24 2309454290 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2278034883 Sep 09 07:09:44 AM UTC 24 Sep 09 07:09:50 AM UTC 24 6516655659 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2194084681 Sep 09 07:09:39 AM UTC 24 Sep 09 07:09:50 AM UTC 24 6258347816 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.114768316 Sep 09 07:09:46 AM UTC 24 Sep 09 07:09:50 AM UTC 24 2049792438 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3539502794 Sep 09 07:09:42 AM UTC 24 Sep 09 07:09:50 AM UTC 24 2063042038 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2811274827 Sep 09 07:09:43 AM UTC 24 Sep 09 07:09:50 AM UTC 24 2620373055 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2708069229 Sep 09 07:09:36 AM UTC 24 Sep 09 07:09:50 AM UTC 24 4695401191 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.697594900 Sep 09 07:09:48 AM UTC 24 Sep 09 07:09:51 AM UTC 24 2192975648 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.452772288 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:52 AM UTC 24 3701739392 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.158500678 Sep 09 07:09:40 AM UTC 24 Sep 09 07:09:57 AM UTC 24 22141895505 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.904052231 Sep 09 07:09:50 AM UTC 24 Sep 09 07:09:53 AM UTC 24 3615648179 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3540063768 Sep 09 07:09:29 AM UTC 24 Sep 09 07:09:53 AM UTC 24 29856885647 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3459664576 Sep 09 07:09:43 AM UTC 24 Sep 09 07:09:53 AM UTC 24 2769611764 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.894497420 Sep 09 07:09:51 AM UTC 24 Sep 09 07:09:54 AM UTC 24 2146984074 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.4267703063 Sep 09 07:09:51 AM UTC 24 Sep 09 07:09:54 AM UTC 24 2044677170 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.720945299 Sep 09 07:09:50 AM UTC 24 Sep 09 07:09:54 AM UTC 24 2692744564 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.1717218899 Sep 09 07:09:51 AM UTC 24 Sep 09 07:09:55 AM UTC 24 2103922799 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3897989907 Sep 09 07:09:52 AM UTC 24 Sep 09 07:09:55 AM UTC 24 2717806105 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.208200171 Sep 09 07:09:48 AM UTC 24 Sep 09 07:09:56 AM UTC 24 2112005725 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2134678963 Sep 09 07:09:34 AM UTC 24 Sep 09 07:09:56 AM UTC 24 6541801682 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3520012036 Sep 09 07:09:54 AM UTC 24 Sep 09 07:09:58 AM UTC 24 6446708947 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3041454724 Sep 09 07:09:52 AM UTC 24 Sep 09 07:09:58 AM UTC 24 2612425964 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.113839782 Sep 09 07:09:50 AM UTC 24 Sep 09 07:09:59 AM UTC 24 2611405346 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.843013647 Sep 09 07:09:48 AM UTC 24 Sep 09 07:09:59 AM UTC 24 2452866598 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.4122389141 Sep 09 07:09:48 AM UTC 24 Sep 09 07:10:00 AM UTC 24 2511858547 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.130077016 Sep 09 07:09:30 AM UTC 24 Sep 09 07:10:00 AM UTC 24 40568738530 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1913048511 Sep 09 07:09:26 AM UTC 24 Sep 09 07:10:00 AM UTC 24 37520713029 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3736548993 Sep 09 07:09:56 AM UTC 24 Sep 09 07:10:00 AM UTC 24 2034860774 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.76425790 Sep 09 07:09:26 AM UTC 24 Sep 09 07:10:00 AM UTC 24 42092961112 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.2771078945 Sep 09 07:09:57 AM UTC 24 Sep 09 07:10:00 AM UTC 24 2511915045 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.4247790396 Sep 09 07:09:50 AM UTC 24 Sep 09 07:10:01 AM UTC 24 2704248499 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3460528437 Sep 09 07:09:34 AM UTC 24 Sep 09 07:10:01 AM UTC 24 36591733527 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.1240585331 Sep 09 07:09:51 AM UTC 24 Sep 09 07:10:01 AM UTC 24 2454595689 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2838249966 Sep 09 07:09:57 AM UTC 24 Sep 09 07:10:02 AM UTC 24 2135523246 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1732006587 Sep 09 07:09:55 AM UTC 24 Sep 09 07:10:02 AM UTC 24 2831721575 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2678752418 Sep 09 07:09:58 AM UTC 24 Sep 09 07:10:02 AM UTC 24 2130860652 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.473863749 Sep 09 07:09:25 AM UTC 24 Sep 09 07:10:02 AM UTC 24 48279797577 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4175367130 Sep 09 07:09:52 AM UTC 24 Sep 09 07:10:02 AM UTC 24 3171758418 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.1276526101 Sep 09 07:09:51 AM UTC 24 Sep 09 07:10:02 AM UTC 24 3149034507 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4233866354 Sep 09 07:09:46 AM UTC 24 Sep 09 07:10:02 AM UTC 24 19700255686 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1907798348 Sep 09 07:09:59 AM UTC 24 Sep 09 07:10:04 AM UTC 24 2640349885 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.435867992 Sep 09 07:10:01 AM UTC 24 Sep 09 07:10:04 AM UTC 24 7320016573 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.135163598 Sep 09 07:09:59 AM UTC 24 Sep 09 07:10:05 AM UTC 24 4186492271 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.1472312937 Sep 09 07:10:21 AM UTC 24 Sep 09 07:10:36 AM UTC 24 8619678527 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2607703560 Sep 09 07:10:02 AM UTC 24 Sep 09 07:10:05 AM UTC 24 2028359104 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3672066538 Sep 09 07:10:04 AM UTC 24 Sep 09 07:10:07 AM UTC 24 2656197071 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.3202996938 Sep 09 07:10:04 AM UTC 24 Sep 09 07:10:07 AM UTC 24 2537353893 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.4057766191 Sep 09 07:10:01 AM UTC 24 Sep 09 07:10:09 AM UTC 24 3171047886 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.970566707 Sep 09 07:10:04 AM UTC 24 Sep 09 07:10:10 AM UTC 24 2618006330 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.99492274 Sep 09 07:09:59 AM UTC 24 Sep 09 07:10:10 AM UTC 24 3520235286 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3365582229 Sep 09 07:09:51 AM UTC 24 Sep 09 07:10:11 AM UTC 24 10560967121 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.3267893850 Sep 09 07:10:07 AM UTC 24 Sep 09 07:10:11 AM UTC 24 2147754635 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3548882788 Sep 09 07:09:59 AM UTC 24 Sep 09 07:10:12 AM UTC 24 2511979361 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2324069750 Sep 09 07:10:09 AM UTC 24 Sep 09 07:10:12 AM UTC 24 2477568178 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.404138636 Sep 09 07:10:04 AM UTC 24 Sep 09 07:10:13 AM UTC 24 2784880640 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.76183353 Sep 09 07:09:56 AM UTC 24 Sep 09 07:10:13 AM UTC 24 4549036755 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3362978650 Sep 09 07:10:06 AM UTC 24 Sep 09 07:10:13 AM UTC 24 2021458978 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.2865627924 Sep 09 07:10:02 AM UTC 24 Sep 09 07:10:13 AM UTC 24 2108800861 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.3121951001 Sep 09 07:10:02 AM UTC 24 Sep 09 07:10:14 AM UTC 24 2460590054 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4013918654 Sep 09 07:10:02 AM UTC 24 Sep 09 07:10:14 AM UTC 24 3646184488 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1112519698 Sep 09 07:10:10 AM UTC 24 Sep 09 07:10:14 AM UTC 24 2535673983 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.4215278262 Sep 09 07:10:04 AM UTC 24 Sep 09 07:10:15 AM UTC 24 2025491672 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1014827424 Sep 09 07:10:11 AM UTC 24 Sep 09 07:10:16 AM UTC 24 3584264052 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3533306227 Sep 09 07:10:06 AM UTC 24 Sep 09 07:10:17 AM UTC 24 6657983717 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1215142828 Sep 09 07:10:09 AM UTC 24 Sep 09 07:10:18 AM UTC 24 2202133674 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3320573765 Sep 09 07:10:05 AM UTC 24 Sep 09 07:10:18 AM UTC 24 4990004708 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2963446824 Sep 09 07:10:15 AM UTC 24 Sep 09 07:10:18 AM UTC 24 2134513476 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1173247825 Sep 09 07:10:04 AM UTC 24 Sep 09 07:10:18 AM UTC 24 3781544586 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.814479637 Sep 09 07:10:16 AM UTC 24 Sep 09 07:10:19 AM UTC 24 2739863862 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1807244439 Sep 09 07:10:11 AM UTC 24 Sep 09 07:10:21 AM UTC 24 3166504704 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.422839101 Sep 09 07:10:17 AM UTC 24 Sep 09 07:10:21 AM UTC 24 2634911737 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.908718566 Sep 09 07:10:11 AM UTC 24 Sep 09 07:10:21 AM UTC 24 2610927940 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3132115717 Sep 09 07:10:11 AM UTC 24 Sep 09 07:10:22 AM UTC 24 3178076792 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.814161908 Sep 09 07:10:19 AM UTC 24 Sep 09 07:10:23 AM UTC 24 3231474243 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.438827831 Sep 09 07:10:15 AM UTC 24 Sep 09 07:10:23 AM UTC 24 2016694335 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.3769697377 Sep 09 07:10:15 AM UTC 24 Sep 09 07:10:23 AM UTC 24 2111551865 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4199753713 Sep 09 07:10:19 AM UTC 24 Sep 09 07:10:24 AM UTC 24 4449734175 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1088717301 Sep 09 07:10:19 AM UTC 24 Sep 09 07:10:25 AM UTC 24 5344185473 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.1483691385 Sep 09 07:10:13 AM UTC 24 Sep 09 07:10:25 AM UTC 24 2966030147 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.4216853878 Sep 09 07:10:15 AM UTC 24 Sep 09 07:10:25 AM UTC 24 2458882302 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.2995671787 Sep 09 07:10:23 AM UTC 24 Sep 09 07:10:26 AM UTC 24 2324868528 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3824457272 Sep 09 07:10:24 AM UTC 24 Sep 09 07:10:29 AM UTC 24 2633784011 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2607581932 Sep 09 07:10:22 AM UTC 24 Sep 09 07:10:29 AM UTC 24 2012907947 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.21065380 Sep 09 07:10:15 AM UTC 24 Sep 09 07:10:29 AM UTC 24 7224257316 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3057949532 Sep 09 07:10:20 AM UTC 24 Sep 09 07:10:29 AM UTC 24 2265836551 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.925776565 Sep 09 07:10:25 AM UTC 24 Sep 09 07:10:29 AM UTC 24 5293684314 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1756437775 Sep 09 07:10:19 AM UTC 24 Sep 09 07:10:31 AM UTC 24 5279783762 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2871402765 Sep 09 07:10:25 AM UTC 24 Sep 09 07:10:32 AM UTC 24 3094269723 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.2656725073 Sep 09 07:10:26 AM UTC 24 Sep 09 07:10:33 AM UTC 24 3188124538 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.1797978461 Sep 09 07:10:24 AM UTC 24 Sep 09 07:10:34 AM UTC 24 2514954168 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3788009083 Sep 09 07:10:22 AM UTC 24 Sep 09 07:10:35 AM UTC 24 2108924370 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.378328154 Sep 09 07:10:31 AM UTC 24 Sep 09 07:10:35 AM UTC 24 2487316304 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2251056381 Sep 09 07:10:30 AM UTC 24 Sep 09 07:10:37 AM UTC 24 2121050983 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.101845621 Sep 09 07:10:23 AM UTC 24 Sep 09 07:10:37 AM UTC 24 2444489413 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1693798485 Sep 09 07:10:15 AM UTC 24 Sep 09 07:10:39 AM UTC 24 16733166127 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4033578855 Sep 09 07:10:34 AM UTC 24 Sep 09 07:10:39 AM UTC 24 2621912423 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.555177582 Sep 09 07:09:51 AM UTC 24 Sep 09 07:10:39 AM UTC 24 17462995556 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1666492559 Sep 09 07:10:30 AM UTC 24 Sep 09 07:10:40 AM UTC 24 2012293441 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3034477094 Sep 09 07:10:33 AM UTC 24 Sep 09 07:10:40 AM UTC 24 2510572353 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2969850242 Sep 09 07:10:35 AM UTC 24 Sep 09 07:10:40 AM UTC 24 3491349196 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.667614086 Sep 09 07:10:32 AM UTC 24 Sep 09 07:10:40 AM UTC 24 2103072082 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3309959297 Sep 09 07:10:05 AM UTC 24 Sep 09 07:10:40 AM UTC 24 36933578904 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1582298671 Sep 09 07:10:36 AM UTC 24 Sep 09 07:10:40 AM UTC 24 4793632095 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3351161759 Sep 09 07:10:36 AM UTC 24 Sep 09 07:10:43 AM UTC 24 3615708957 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1950397599 Sep 09 07:10:30 AM UTC 24 Sep 09 07:10:46 AM UTC 24 4468518983 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1545310197 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:47 AM UTC 24 2613097500 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3157233695 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:48 AM UTC 24 2512413029 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.230738414 Sep 09 07:11:12 AM UTC 24 Sep 09 07:11:20 AM UTC 24 2718592173 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.155689036 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:49 AM UTC 24 2113966737 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2359821612 Sep 09 07:10:40 AM UTC 24 Sep 09 07:10:50 AM UTC 24 16989068924 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2038503096 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:52 AM UTC 24 2013301776 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.2940936938 Sep 09 07:10:48 AM UTC 24 Sep 09 07:10:52 AM UTC 24 5847795065 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1604157717 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:52 AM UTC 24 3245799542 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.2888236852 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:53 AM UTC 24 2224707657 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.2571989800 Sep 09 07:10:41 AM UTC 24 Sep 09 07:10:53 AM UTC 24 2468606097 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3798610620 Sep 09 07:10:40 AM UTC 24 Sep 09 07:10:55 AM UTC 24 16435413908 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3306320292 Sep 09 07:09:25 AM UTC 24 Sep 09 07:10:55 AM UTC 24 64845645778 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3737882821 Sep 09 07:10:37 AM UTC 24 Sep 09 07:10:56 AM UTC 24 4009420028 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1005498967 Sep 09 07:09:55 AM UTC 24 Sep 09 07:10:58 AM UTC 24 40908071342 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.302751907 Sep 09 07:10:53 AM UTC 24 Sep 09 07:10:58 AM UTC 24 2463132010 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.1126583718 Sep 09 07:09:34 AM UTC 24 Sep 09 07:10:59 AM UTC 24 147930162163 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.4235635448 Sep 09 07:10:52 AM UTC 24 Sep 09 07:10:59 AM UTC 24 2014440517 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.2242052364 Sep 09 07:10:53 AM UTC 24 Sep 09 07:11:00 AM UTC 24 2065063843 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.320995012 Sep 09 07:09:26 AM UTC 24 Sep 09 07:11:00 AM UTC 24 41022651000 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2404891592 Sep 09 07:10:45 AM UTC 24 Sep 09 07:11:01 AM UTC 24 3663567312 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.781011642 Sep 09 07:10:56 AM UTC 24 Sep 09 07:11:01 AM UTC 24 3664856796 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2198650120 Sep 09 07:10:58 AM UTC 24 Sep 09 07:11:02 AM UTC 24 3743949349 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1481889147 Sep 09 07:10:52 AM UTC 24 Sep 09 07:11:02 AM UTC 24 2110616212 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.2353021735 Sep 09 07:09:46 AM UTC 24 Sep 09 07:11:03 AM UTC 24 42061460922 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.253412776 Sep 09 07:11:00 AM UTC 24 Sep 09 07:11:04 AM UTC 24 2026958309 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2719401551 Sep 09 07:10:30 AM UTC 24 Sep 09 07:11:05 AM UTC 24 12987563216 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.4143557209 Sep 09 07:10:54 AM UTC 24 Sep 09 07:11:05 AM UTC 24 2510985243 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1298279168 Sep 09 07:11:01 AM UTC 24 Sep 09 07:11:06 AM UTC 24 2196053975 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1961605150 Sep 09 07:10:54 AM UTC 24 Sep 09 07:11:07 AM UTC 24 2611563632 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2936815757 Sep 09 07:10:20 AM UTC 24 Sep 09 07:11:07 AM UTC 24 62432864829 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1772716368 Sep 09 07:10:56 AM UTC 24 Sep 09 07:11:08 AM UTC 24 10693113343 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2440400598 Sep 09 07:10:54 AM UTC 24 Sep 09 07:11:08 AM UTC 24 3545595875 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.327894851 Sep 09 07:11:02 AM UTC 24 Sep 09 07:11:08 AM UTC 24 3604852166 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2583808114 Sep 09 07:11:01 AM UTC 24 Sep 09 07:11:09 AM UTC 24 2114847887 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3116616690 Sep 09 07:11:04 AM UTC 24 Sep 09 07:11:10 AM UTC 24 3704188070 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1894135957 Sep 09 07:11:05 AM UTC 24 Sep 09 07:11:10 AM UTC 24 2645685347 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3313838865 Sep 09 07:11:02 AM UTC 24 Sep 09 07:11:10 AM UTC 24 2613148943 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1662491936 Sep 09 07:10:59 AM UTC 24 Sep 09 07:11:11 AM UTC 24 19103657992 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1032215841 Sep 09 07:11:11 AM UTC 24 Sep 09 07:11:21 AM UTC 24 2807190111 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3749934035 Sep 09 07:11:09 AM UTC 24 Sep 09 07:11:11 AM UTC 24 2048450328 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.1680491309 Sep 09 07:11:02 AM UTC 24 Sep 09 07:11:12 AM UTC 24 2509013316 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3440097481 Sep 09 07:09:44 AM UTC 24 Sep 09 07:11:12 AM UTC 24 124283467318 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.2588755747 Sep 09 07:11:01 AM UTC 24 Sep 09 07:11:12 AM UTC 24 2462520987 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1050478163 Sep 09 07:11:09 AM UTC 24 Sep 09 07:11:12 AM UTC 24 2134311639 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.581311397 Sep 09 07:11:09 AM UTC 24 Sep 09 07:11:13 AM UTC 24 2484225749 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2019493519 Sep 09 07:11:06 AM UTC 24 Sep 09 07:11:13 AM UTC 24 4863650036 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1900348971 Sep 09 07:11:10 AM UTC 24 Sep 09 07:11:13 AM UTC 24 2126997311 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1865698731 Sep 09 07:10:50 AM UTC 24 Sep 09 07:11:14 AM UTC 24 4340577222 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1943176655 Sep 09 07:11:05 AM UTC 24 Sep 09 07:11:14 AM UTC 24 3700298786 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.351007544 Sep 09 07:11:09 AM UTC 24 Sep 09 07:11:14 AM UTC 24 6556111902 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1379354407 Sep 09 07:11:11 AM UTC 24 Sep 09 07:11:15 AM UTC 24 2975071960 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.999032341 Sep 09 07:11:13 AM UTC 24 Sep 09 07:11:16 AM UTC 24 2031309077 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.418217987 Sep 09 07:09:51 AM UTC 24 Sep 09 07:11:19 AM UTC 24 67768550095 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3626632054 Sep 09 07:11:10 AM UTC 24 Sep 09 07:11:19 AM UTC 24 2513370439 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2818069726 Sep 09 07:11:00 AM UTC 24 Sep 09 07:11:19 AM UTC 24 17461820336 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2414027118 Sep 09 07:11:15 AM UTC 24 Sep 09 07:11:20 AM UTC 24 2631969697 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3757841769 Sep 09 07:11:11 AM UTC 24 Sep 09 07:11:20 AM UTC 24 2612270047 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.4230685903 Sep 09 07:10:14 AM UTC 24 Sep 09 07:11:20 AM UTC 24 84657081305 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.2635420288 Sep 09 07:11:15 AM UTC 24 Sep 09 07:11:20 AM UTC 24 2526560123 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.644158543 Sep 09 07:11:16 AM UTC 24 Sep 09 07:11:22 AM UTC 24 3612219354 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.992592127 Sep 09 07:10:37 AM UTC 24 Sep 09 07:11:22 AM UTC 24 59123789721 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3400954451 Sep 09 07:11:15 AM UTC 24 Sep 09 07:11:22 AM UTC 24 2485018199 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.492914213 Sep 09 07:11:56 AM UTC 24 Sep 09 07:12:07 AM UTC 24 2612595943 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3219186105 Sep 09 07:11:15 AM UTC 24 Sep 09 07:11:23 AM UTC 24 2078098070 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.152788172 Sep 09 07:11:20 AM UTC 24 Sep 09 07:11:24 AM UTC 24 3357036734 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1184666191 Sep 09 07:11:22 AM UTC 24 Sep 09 07:11:24 AM UTC 24 2176633522 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1181386002 Sep 09 07:10:49 AM UTC 24 Sep 09 07:11:25 AM UTC 24 24837687336 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.3701242217 Sep 09 07:11:14 AM UTC 24 Sep 09 07:11:25 AM UTC 24 2112813597 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2794455457 Sep 09 07:11:22 AM UTC 24 Sep 09 07:11:25 AM UTC 24 2478594615 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1683870628 Sep 09 07:11:23 AM UTC 24 Sep 09 07:11:26 AM UTC 24 2583704357 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3967742319 Sep 09 07:11:22 AM UTC 24 Sep 09 07:11:26 AM UTC 24 2044329820 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1347095448 Sep 09 07:11:17 AM UTC 24 Sep 09 07:11:26 AM UTC 24 3374889258 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1286150456 Sep 09 07:11:23 AM UTC 24 Sep 09 07:11:26 AM UTC 24 2216452537 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1089271074 Sep 09 07:11:13 AM UTC 24 Sep 09 07:11:26 AM UTC 24 3552698465 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.3607664848 Sep 09 07:12:04 AM UTC 24 Sep 09 07:12:08 AM UTC 24 2170163566 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3551147381 Sep 09 07:11:23 AM UTC 24 Sep 09 07:11:27 AM UTC 24 2626607887 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.1151627778 Sep 09 07:12:02 AM UTC 24 Sep 09 07:12:07 AM UTC 24 2122941854 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2704819926 Sep 09 07:11:27 AM UTC 24 Sep 09 07:11:32 AM UTC 24 4526487305 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.956561788 Sep 09 07:11:25 AM UTC 24 Sep 09 07:11:32 AM UTC 24 8831115572 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.271167056 Sep 09 07:09:35 AM UTC 24 Sep 09 07:11:33 AM UTC 24 42011786176 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2556510738 Sep 09 07:11:20 AM UTC 24 Sep 09 07:11:33 AM UTC 24 13859665051 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.691754198 Sep 09 07:11:27 AM UTC 24 Sep 09 07:11:33 AM UTC 24 2015207331 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.13634529 Sep 09 07:11:24 AM UTC 24 Sep 09 07:11:33 AM UTC 24 3184871412 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1806165888 Sep 09 07:11:20 AM UTC 24 Sep 09 07:11:34 AM UTC 24 8948605263 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2747546856 Sep 09 07:11:25 AM UTC 24 Sep 09 07:11:34 AM UTC 24 3679363931 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1347435767 Sep 09 07:11:28 AM UTC 24 Sep 09 07:11:35 AM UTC 24 2032585027 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3570495107 Sep 09 07:11:27 AM UTC 24 Sep 09 07:11:35 AM UTC 24 2111759533 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3070289499 Sep 09 07:11:27 AM UTC 24 Sep 09 07:11:37 AM UTC 24 2452994174 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2691941545 Sep 09 07:11:36 AM UTC 24 Sep 09 07:11:38 AM UTC 24 2565348114 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1044262229 Sep 09 07:11:36 AM UTC 24 Sep 09 07:11:38 AM UTC 24 2171029237 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.548444521 Sep 09 07:09:46 AM UTC 24 Sep 09 07:11:40 AM UTC 24 169549085959 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.2015730381 Sep 09 07:11:37 AM UTC 24 Sep 09 07:11:40 AM UTC 24 2260616438 ps