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COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1214224016	4959	4959	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1214224016	2544	2544	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1214224016	5309	5309	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1214224016	13126	13126	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1214224016	98494	98494	851

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	1214224016	607151	607151	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	1214224016	3366	3366	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	1214224016	8392	8392	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	1214224016	6289	6289	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	1214224016	7942	7942	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	1214224016	4959	4959	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	1214224016	2544	2544	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	1214224016	5309	5309	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	1214224016	13126	13126	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	1214224016	98494	98494	851