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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 28 68 70.83 28
Automatically Generated Cross Bins 96 28 68 70.83 28
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * [auto[0]] [auto[0]] [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[0]] * [auto[1]] * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[1]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 45 1 T42 1 T58 1 T43 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 26 1 T287 2 T326 1 T46 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 36 1 T33 1 T41 1 T321 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 27 1 T40 2 T45 1 T182 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 51 1 T33 1 T58 3 T43 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 33 1 T40 2 T41 1 T307 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 52 1 T33 2 T58 2 T142 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 27 1 T43 3 T142 1 T307 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 53 1 T33 1 T58 1 T43 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 25 1 T307 1 T287 1 T45 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 37 1 T33 2 T43 1 T142 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 16 1 T45 1 T46 3 T401 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 40 1 T42 1 T58 3 T142 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 25 1 T287 2 T45 1 T182 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 43 1 T400 1 T322 1 T288 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 31 1 T182 1 T326 1 T271 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 56 1 T42 1 T58 1 T41 3
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 25 1 T40 2 T307 2 T287 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 40 1 T33 1 T44 2 T142 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 21 1 T40 1 T287 3 T326 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 54 1 T42 2 T58 2 T41 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 25 1 T40 1 T41 1 T326 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 41 1 T33 1 T42 6 T325 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 28 1 T117 5 T46 1 T402 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 52 1 T33 1 T58 1 T114 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 34 1 T40 1 T307 1 T287 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 52 1 T33 1 T43 1 T44 6
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 35 1 T142 1 T287 1 T45 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 50 1 T58 4 T325 1 T400 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 19 1 T307 1 T45 1 T182 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 55 1 T33 1 T43 1 T142 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 65 1 T43 7 T142 1 T45 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 48 1 T33 1 T41 2 T142 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 29 1 T40 1 T45 2 T182 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 34 1 T33 1 T58 2 T43 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 41 1 T142 10 T307 1 T45 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 39 1 T42 1 T142 1 T112 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 26 1 T40 2 T287 1 T45 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 63 1 T33 1 T42 2 T58 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 22 1 T40 1 T307 3 T287 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 49 1 T33 1 T114 2 T321 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 26 1 T307 1 T45 2 T182 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 48 1 T41 1 T112 1 T114 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 49 1 T40 1 T287 2 T45 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 41 1 T33 1 T112 1 T325 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 49 1 T307 1 T287 1 T45 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 35 1 T42 3 T112 1 T286 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 22 1 T307 1 T45 1 T403 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 55 1 T114 1 T282 1 T126 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 21 1 T307 1 T282 6 T182 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 74 1 T41 1 T112 1 T321 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 39 1 T40 1 T41 6 T307 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 71 1 T33 1 T112 2 T126 13
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 18 1 T40 2 T307 1 T287 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 64 1 T114 2 T124 1 T321 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 39 1 T41 1 T124 9 T326 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 39 1 T33 1 T59 1 T114 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 39 1 T307 1 T287 1 T46 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 82 1 T59 9 T41 2 T44 4
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 44 1 T41 3 T45 1 T182 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 60 1 T33 1 T114 1 T325 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 72 1 T40 1 T182 2 T326 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 177 1 T33 2 T40 2 T112 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 131 1 T40 6 T307 1 T287 4
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 1 1 T400 1 - - - -
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 1 1 T407 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 1 1 T411 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 17 1 T46 1 T403 2 T308 6


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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