Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
678 |
1 |
|
|
T5 |
13 |
|
T14 |
14 |
|
T25 |
8 |
| auto[1] |
682 |
1 |
|
|
T5 |
7 |
|
T14 |
6 |
|
T25 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
696 |
1 |
|
|
T5 |
13 |
|
T14 |
11 |
|
T25 |
8 |
| auto[1] |
664 |
1 |
|
|
T5 |
7 |
|
T14 |
9 |
|
T25 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
657 |
1 |
|
|
T5 |
8 |
|
T14 |
11 |
|
T25 |
9 |
| auto[1] |
703 |
1 |
|
|
T5 |
12 |
|
T14 |
9 |
|
T25 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
698 |
1 |
|
|
T5 |
10 |
|
T14 |
7 |
|
T25 |
12 |
| auto[1] |
662 |
1 |
|
|
T5 |
10 |
|
T14 |
13 |
|
T25 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
664 |
1 |
|
|
T5 |
9 |
|
T14 |
11 |
|
T25 |
10 |
| auto[1] |
696 |
1 |
|
|
T5 |
11 |
|
T14 |
9 |
|
T25 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
655 |
1 |
|
|
T5 |
9 |
|
T14 |
10 |
|
T25 |
6 |
| auto[1] |
705 |
1 |
|
|
T5 |
11 |
|
T14 |
10 |
|
T25 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
693 |
1 |
|
|
T5 |
8 |
|
T14 |
10 |
|
T25 |
10 |
| auto[1] |
667 |
1 |
|
|
T5 |
12 |
|
T14 |
10 |
|
T25 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
648 |
1 |
|
|
T5 |
12 |
|
T14 |
9 |
|
T25 |
8 |
| auto[1] |
712 |
1 |
|
|
T5 |
8 |
|
T14 |
11 |
|
T25 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
691 |
1 |
|
|
T5 |
8 |
|
T14 |
10 |
|
T25 |
4 |
| auto[1] |
669 |
1 |
|
|
T5 |
12 |
|
T14 |
10 |
|
T25 |
16 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
714 |
1 |
|
|
T5 |
11 |
|
T14 |
9 |
|
T25 |
10 |
| auto[1] |
646 |
1 |
|
|
T5 |
9 |
|
T14 |
11 |
|
T25 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
692 |
1 |
|
|
T5 |
10 |
|
T14 |
13 |
|
T25 |
13 |
| auto[1] |
668 |
1 |
|
|
T5 |
10 |
|
T14 |
7 |
|
T25 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
652 |
1 |
|
|
T5 |
7 |
|
T14 |
3 |
|
T25 |
8 |
| auto[1] |
708 |
1 |
|
|
T5 |
13 |
|
T14 |
17 |
|
T25 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
682 |
1 |
|
|
T5 |
13 |
|
T14 |
7 |
|
T25 |
14 |
| auto[1] |
678 |
1 |
|
|
T5 |
7 |
|
T14 |
13 |
|
T25 |
6 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
696 |
1 |
|
|
T5 |
13 |
|
T14 |
11 |
|
T25 |
8 |
| auto[1] |
664 |
1 |
|
|
T5 |
7 |
|
T14 |
9 |
|
T25 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
685 |
1 |
|
|
T5 |
5 |
|
T14 |
10 |
|
T25 |
11 |
| auto[1] |
675 |
1 |
|
|
T5 |
15 |
|
T14 |
10 |
|
T25 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
704 |
1 |
|
|
T5 |
13 |
|
T14 |
10 |
|
T25 |
10 |
| auto[1] |
656 |
1 |
|
|
T5 |
7 |
|
T14 |
10 |
|
T25 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
680 |
1 |
|
|
T5 |
10 |
|
T14 |
12 |
|
T25 |
6 |
| auto[1] |
680 |
1 |
|
|
T5 |
10 |
|
T14 |
8 |
|
T25 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
685 |
1 |
|
|
T5 |
10 |
|
T14 |
11 |
|
T25 |
8 |
| auto[1] |
675 |
1 |
|
|
T5 |
10 |
|
T14 |
9 |
|
T25 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
680 |
1 |
|
|
T5 |
3 |
|
T14 |
9 |
|
T25 |
12 |
| auto[1] |
680 |
1 |
|
|
T5 |
17 |
|
T14 |
11 |
|
T25 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
687 |
1 |
|
|
T5 |
11 |
|
T14 |
10 |
|
T25 |
8 |
| auto[1] |
673 |
1 |
|
|
T5 |
9 |
|
T14 |
10 |
|
T25 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
696 |
1 |
|
|
T5 |
11 |
|
T14 |
10 |
|
T25 |
13 |
| auto[1] |
664 |
1 |
|
|
T5 |
9 |
|
T14 |
10 |
|
T25 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
694 |
1 |
|
|
T5 |
10 |
|
T14 |
15 |
|
T25 |
8 |
| auto[1] |
666 |
1 |
|
|
T5 |
10 |
|
T14 |
5 |
|
T25 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
678 |
1 |
|
|
T5 |
11 |
|
T14 |
9 |
|
T25 |
11 |
| auto[1] |
682 |
1 |
|
|
T5 |
9 |
|
T14 |
11 |
|
T25 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
652 |
1 |
|
|
T5 |
7 |
|
T14 |
3 |
|
T25 |
8 |
| auto[1] |
708 |
1 |
|
|
T5 |
13 |
|
T14 |
17 |
|
T25 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
320 |
1 |
|
|
T14 |
4 |
|
T25 |
5 |
|
T92 |
8 |
| auto[0] |
auto[1] |
365 |
1 |
|
|
T5 |
5 |
|
T14 |
6 |
|
T25 |
6 |
| auto[1] |
auto[0] |
337 |
1 |
|
|
T5 |
8 |
|
T14 |
7 |
|
T25 |
4 |
| auto[1] |
auto[1] |
338 |
1 |
|
|
T5 |
7 |
|
T14 |
3 |
|
T25 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
350 |
1 |
|
|
T5 |
5 |
|
T14 |
2 |
|
T25 |
6 |
| auto[0] |
auto[1] |
354 |
1 |
|
|
T5 |
8 |
|
T14 |
8 |
|
T25 |
4 |
| auto[1] |
auto[0] |
348 |
1 |
|
|
T5 |
5 |
|
T14 |
5 |
|
T25 |
6 |
| auto[1] |
auto[1] |
308 |
1 |
|
|
T5 |
2 |
|
T14 |
5 |
|
T25 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
341 |
1 |
|
|
T5 |
4 |
|
T14 |
7 |
|
T25 |
4 |
| auto[0] |
auto[1] |
339 |
1 |
|
|
T5 |
6 |
|
T14 |
5 |
|
T25 |
2 |
| auto[1] |
auto[0] |
323 |
1 |
|
|
T5 |
5 |
|
T14 |
4 |
|
T25 |
6 |
| auto[1] |
auto[1] |
357 |
1 |
|
|
T5 |
5 |
|
T14 |
4 |
|
T25 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
339 |
1 |
|
|
T5 |
4 |
|
T14 |
6 |
|
T25 |
3 |
| auto[0] |
auto[1] |
346 |
1 |
|
|
T5 |
6 |
|
T14 |
5 |
|
T25 |
5 |
| auto[1] |
auto[0] |
316 |
1 |
|
|
T5 |
5 |
|
T14 |
4 |
|
T25 |
3 |
| auto[1] |
auto[1] |
359 |
1 |
|
|
T5 |
5 |
|
T14 |
5 |
|
T25 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
350 |
1 |
|
|
T5 |
1 |
|
T14 |
5 |
|
T25 |
5 |
| auto[0] |
auto[1] |
330 |
1 |
|
|
T5 |
2 |
|
T14 |
4 |
|
T25 |
7 |
| auto[1] |
auto[0] |
343 |
1 |
|
|
T5 |
7 |
|
T14 |
5 |
|
T25 |
5 |
| auto[1] |
auto[1] |
337 |
1 |
|
|
T5 |
10 |
|
T14 |
6 |
|
T25 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
331 |
1 |
|
|
T5 |
7 |
|
T14 |
5 |
|
T25 |
2 |
| auto[0] |
auto[1] |
356 |
1 |
|
|
T5 |
4 |
|
T14 |
5 |
|
T25 |
6 |
| auto[1] |
auto[0] |
317 |
1 |
|
|
T5 |
5 |
|
T14 |
4 |
|
T25 |
6 |
| auto[1] |
auto[1] |
356 |
1 |
|
|
T5 |
4 |
|
T14 |
6 |
|
T25 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
349 |
1 |
|
|
T5 |
7 |
|
T14 |
5 |
|
T25 |
6 |
| auto[0] |
auto[1] |
345 |
1 |
|
|
T5 |
3 |
|
T14 |
10 |
|
T25 |
2 |
| auto[1] |
auto[0] |
365 |
1 |
|
|
T5 |
4 |
|
T14 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
301 |
1 |
|
|
T5 |
6 |
|
T14 |
1 |
|
T25 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
330 |
1 |
|
|
T5 |
7 |
|
T14 |
4 |
|
T25 |
9 |
| auto[0] |
auto[1] |
348 |
1 |
|
|
T5 |
4 |
|
T14 |
5 |
|
T25 |
2 |
| auto[1] |
auto[0] |
362 |
1 |
|
|
T5 |
3 |
|
T14 |
9 |
|
T25 |
4 |
| auto[1] |
auto[1] |
320 |
1 |
|
|
T5 |
6 |
|
T14 |
2 |
|
T25 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
346 |
1 |
|
|
T5 |
8 |
|
T14 |
4 |
|
T25 |
5 |
| auto[0] |
auto[1] |
336 |
1 |
|
|
T5 |
5 |
|
T14 |
3 |
|
T25 |
9 |
| auto[1] |
auto[0] |
332 |
1 |
|
|
T5 |
5 |
|
T14 |
10 |
|
T25 |
3 |
| auto[1] |
auto[1] |
346 |
1 |
|
|
T5 |
2 |
|
T14 |
3 |
|
T25 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
696 |
1 |
|
|
T5 |
13 |
|
T14 |
11 |
|
T25 |
8 |
| auto[1] |
auto[1] |
664 |
1 |
|
|
T5 |
7 |
|
T14 |
9 |
|
T25 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
343 |
1 |
|
|
T5 |
3 |
|
T14 |
5 |
|
T25 |
2 |
| auto[0] |
auto[1] |
353 |
1 |
|
|
T5 |
8 |
|
T14 |
5 |
|
T25 |
11 |
| auto[1] |
auto[0] |
348 |
1 |
|
|
T5 |
5 |
|
T14 |
5 |
|
T25 |
2 |
| auto[1] |
auto[1] |
316 |
1 |
|
|
T5 |
4 |
|
T14 |
5 |
|
T25 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
652 |
1 |
|
|
T5 |
7 |
|
T14 |
3 |
|
T25 |
8 |
| auto[1] |
auto[1] |
708 |
1 |
|
|
T5 |
13 |
|
T14 |
17 |
|
T25 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T460 |
9 |
|
T290 |
7 |
|
T255 |
7 |
| auto[1] |
48 |
1 |
|
|
T460 |
11 |
|
T290 |
13 |
|
T255 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T460 |
17 |
|
T290 |
12 |
|
T255 |
9 |
| auto[1] |
31 |
1 |
|
|
T460 |
3 |
|
T290 |
8 |
|
T255 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
38 |
1 |
|
|
T460 |
7 |
|
T290 |
10 |
|
T255 |
13 |
| auto[1] |
42 |
1 |
|
|
T460 |
13 |
|
T290 |
10 |
|
T255 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
41 |
1 |
|
|
T460 |
8 |
|
T290 |
10 |
|
T255 |
13 |
| auto[1] |
39 |
1 |
|
|
T460 |
12 |
|
T290 |
10 |
|
T255 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T460 |
10 |
|
T290 |
6 |
|
T255 |
11 |
| auto[1] |
38 |
1 |
|
|
T460 |
10 |
|
T290 |
14 |
|
T255 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T460 |
11 |
|
T290 |
13 |
|
T255 |
13 |
| auto[1] |
31 |
1 |
|
|
T460 |
9 |
|
T290 |
7 |
|
T255 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T460 |
8 |
|
T290 |
8 |
|
T255 |
9 |
| auto[1] |
47 |
1 |
|
|
T460 |
12 |
|
T290 |
12 |
|
T255 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T460 |
7 |
|
T290 |
12 |
|
T255 |
6 |
| auto[1] |
45 |
1 |
|
|
T460 |
13 |
|
T290 |
8 |
|
T255 |
14 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T460 |
13 |
|
T290 |
11 |
|
T255 |
9 |
| auto[1] |
37 |
1 |
|
|
T460 |
7 |
|
T290 |
9 |
|
T255 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
36 |
1 |
|
|
T460 |
9 |
|
T290 |
10 |
|
T255 |
11 |
| auto[1] |
44 |
1 |
|
|
T460 |
11 |
|
T290 |
10 |
|
T255 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
43 |
1 |
|
|
T460 |
11 |
|
T290 |
9 |
|
T255 |
12 |
| auto[1] |
37 |
1 |
|
|
T460 |
9 |
|
T290 |
11 |
|
T255 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T460 |
10 |
|
T290 |
8 |
|
T255 |
13 |
| auto[1] |
36 |
1 |
|
|
T460 |
10 |
|
T290 |
12 |
|
T255 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T460 |
11 |
|
T290 |
11 |
|
T255 |
11 |
| auto[1] |
34 |
1 |
|
|
T460 |
9 |
|
T290 |
9 |
|
T255 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T460 |
17 |
|
T290 |
12 |
|
T255 |
9 |
| auto[1] |
31 |
1 |
|
|
T460 |
3 |
|
T290 |
8 |
|
T255 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T460 |
11 |
|
T290 |
13 |
|
T255 |
9 |
| auto[1] |
36 |
1 |
|
|
T460 |
9 |
|
T290 |
7 |
|
T255 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T460 |
12 |
|
T290 |
11 |
|
T255 |
11 |
| auto[1] |
35 |
1 |
|
|
T460 |
8 |
|
T290 |
9 |
|
T255 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
45 |
1 |
|
|
T460 |
12 |
|
T290 |
12 |
|
T255 |
12 |
| auto[1] |
35 |
1 |
|
|
T460 |
8 |
|
T290 |
8 |
|
T255 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
36 |
1 |
|
|
T460 |
9 |
|
T290 |
7 |
|
T255 |
10 |
| auto[1] |
44 |
1 |
|
|
T460 |
11 |
|
T290 |
13 |
|
T255 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
49 |
1 |
|
|
T460 |
12 |
|
T290 |
8 |
|
T255 |
14 |
| auto[1] |
31 |
1 |
|
|
T460 |
8 |
|
T290 |
12 |
|
T255 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
39 |
1 |
|
|
T460 |
11 |
|
T290 |
8 |
|
T255 |
11 |
| auto[1] |
41 |
1 |
|
|
T460 |
9 |
|
T290 |
12 |
|
T255 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T460 |
8 |
|
T290 |
11 |
|
T255 |
11 |
| auto[1] |
38 |
1 |
|
|
T460 |
12 |
|
T290 |
9 |
|
T255 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
37 |
1 |
|
|
T460 |
9 |
|
T290 |
10 |
|
T255 |
7 |
| auto[1] |
43 |
1 |
|
|
T460 |
11 |
|
T290 |
10 |
|
T255 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T460 |
11 |
|
T290 |
13 |
|
T255 |
10 |
| auto[1] |
34 |
1 |
|
|
T460 |
9 |
|
T290 |
7 |
|
T255 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T460 |
10 |
|
T290 |
8 |
|
T255 |
13 |
| auto[1] |
36 |
1 |
|
|
T460 |
10 |
|
T290 |
12 |
|
T255 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
19 |
1 |
|
|
T460 |
3 |
|
T290 |
7 |
|
T255 |
6 |
| auto[0] |
auto[1] |
25 |
1 |
|
|
T460 |
8 |
|
T290 |
6 |
|
T255 |
3 |
| auto[1] |
auto[0] |
19 |
1 |
|
|
T460 |
4 |
|
T290 |
3 |
|
T255 |
7 |
| auto[1] |
auto[1] |
17 |
1 |
|
|
T460 |
5 |
|
T290 |
4 |
|
T255 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
21 |
1 |
|
|
T460 |
4 |
|
T290 |
6 |
|
T255 |
7 |
| auto[0] |
auto[1] |
24 |
1 |
|
|
T460 |
8 |
|
T290 |
5 |
|
T255 |
4 |
| auto[1] |
auto[0] |
20 |
1 |
|
|
T460 |
4 |
|
T290 |
4 |
|
T255 |
6 |
| auto[1] |
auto[1] |
15 |
1 |
|
|
T460 |
4 |
|
T290 |
5 |
|
T255 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
22 |
1 |
|
|
T460 |
6 |
|
T290 |
4 |
|
T255 |
5 |
| auto[0] |
auto[1] |
23 |
1 |
|
|
T460 |
6 |
|
T290 |
8 |
|
T255 |
7 |
| auto[1] |
auto[0] |
20 |
1 |
|
|
T460 |
4 |
|
T290 |
2 |
|
T255 |
6 |
| auto[1] |
auto[1] |
15 |
1 |
|
|
T460 |
4 |
|
T290 |
6 |
|
T255 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
21 |
1 |
|
|
T460 |
5 |
|
T290 |
5 |
|
T255 |
5 |
| auto[0] |
auto[1] |
15 |
1 |
|
|
T460 |
4 |
|
T290 |
2 |
|
T255 |
5 |
| auto[1] |
auto[0] |
28 |
1 |
|
|
T460 |
6 |
|
T290 |
8 |
|
T255 |
8 |
| auto[1] |
auto[1] |
16 |
1 |
|
|
T460 |
5 |
|
T290 |
5 |
|
T255 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
21 |
1 |
|
|
T460 |
5 |
|
T290 |
4 |
|
T255 |
6 |
| auto[0] |
auto[1] |
28 |
1 |
|
|
T460 |
7 |
|
T290 |
4 |
|
T255 |
8 |
| auto[1] |
auto[0] |
12 |
1 |
|
|
T460 |
3 |
|
T290 |
4 |
|
T255 |
3 |
| auto[1] |
auto[1] |
19 |
1 |
|
|
T460 |
5 |
|
T290 |
8 |
|
T255 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
17 |
1 |
|
|
T460 |
4 |
|
T290 |
6 |
|
T255 |
3 |
| auto[0] |
auto[1] |
22 |
1 |
|
|
T460 |
7 |
|
T290 |
2 |
|
T255 |
8 |
| auto[1] |
auto[0] |
18 |
1 |
|
|
T460 |
3 |
|
T290 |
6 |
|
T255 |
3 |
| auto[1] |
auto[1] |
23 |
1 |
|
|
T460 |
6 |
|
T290 |
6 |
|
T255 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
16 |
1 |
|
|
T460 |
4 |
|
T290 |
5 |
|
T255 |
5 |
| auto[0] |
auto[1] |
21 |
1 |
|
|
T460 |
5 |
|
T290 |
5 |
|
T255 |
2 |
| auto[1] |
auto[0] |
20 |
1 |
|
|
T460 |
5 |
|
T290 |
5 |
|
T255 |
6 |
| auto[1] |
auto[1] |
23 |
1 |
|
|
T460 |
6 |
|
T290 |
5 |
|
T255 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
24 |
1 |
|
|
T460 |
6 |
|
T290 |
6 |
|
T255 |
7 |
| auto[0] |
auto[1] |
22 |
1 |
|
|
T460 |
5 |
|
T290 |
7 |
|
T255 |
3 |
| auto[1] |
auto[0] |
19 |
1 |
|
|
T460 |
5 |
|
T290 |
3 |
|
T255 |
5 |
| auto[1] |
auto[1] |
15 |
1 |
|
|
T460 |
4 |
|
T290 |
4 |
|
T255 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
19 |
1 |
|
|
T460 |
6 |
|
T290 |
3 |
|
T255 |
4 |
| auto[0] |
auto[1] |
27 |
1 |
|
|
T460 |
5 |
|
T290 |
8 |
|
T255 |
7 |
| auto[1] |
auto[0] |
13 |
1 |
|
|
T460 |
3 |
|
T290 |
4 |
|
T255 |
3 |
| auto[1] |
auto[1] |
21 |
1 |
|
|
T460 |
6 |
|
T290 |
5 |
|
T255 |
6 |