Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered80.78
Success102099.22
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091491400
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001226728340339014600
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001226727766586600
tb.dut.tlul_assert_device.gen_device.contigMask_M 0012267283401023786700
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00122672834017866000
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001226727766615300
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012267283401233291900
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00122672834052398300
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012267283401233291900
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00122672834052398300
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00122672834052398300
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00122672834052398300
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001226727766383900
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001226727766388500
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091491400
tb.dut.u_reg.en2addrHit 00122672776625064200
tb.dut.u_reg.reAfterRv 00122672776625064200
tb.dut.u_reg.rePulse 00122672776613317800
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 001226727766109475700
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001226727766116500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766116500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428116500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428104100
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766117400
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 001226727766101820300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001226727766105500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766105500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428105500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 00806742892900
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766106400
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091491400
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001226727766173438600
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001226727766185000
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766185000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428185000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428172700
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766186000
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001226727766166142900
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001226727766177000
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766177000
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428177000
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428164300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766177900
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001226727766166125500
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001226727766177700
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766177700
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428177700
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428165600
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766178800
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001226727766167114600
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001226727766180700
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766180700
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428180700
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428168400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766181600
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001226727766172700500
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001226727766183800
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766183800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428183800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428171500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766184800
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001226727766169964800
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001226727766180500
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766180500
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428180500
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428168000
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766181300
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001226727766169627500
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001226727766182000
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766182000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428182000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428169500
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766182900
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001226727766166077200
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001226727766178500
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766178500
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428178500
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428166100
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766179400
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001226727766120988900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001226727766126300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766126300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428126300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428113800
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766127100
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001226727766123750200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001226727766129200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766129200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428129200
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428117000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766130100
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 001226727766128708000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001226727766131800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766131800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428131800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428119200
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766132900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 001226727766122260400
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001226727766129600
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766129600
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428129600
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428117200
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766130400
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001226727766670207800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001226727766736600
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766736600
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428736600
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428723700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766737500
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001226727766658351800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001226727766734900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766734900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428734900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428722200
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766735900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001226727766640377400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001226727766717500
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766717500
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428717500
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428704400
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766718400
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001226727766645314700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001226727766725100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766725100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428725100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428712200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766726000
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001226727766721576800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001226727766788200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766788200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428788200
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428774800
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766788900
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001226727766715939500
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001226727766791600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766791600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428791600
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428778800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766792600
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001226727766691885700
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001226727766769200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766769200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428769200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428756200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766770200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001226727766695353100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001226727766774800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766774800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428774800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428762200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766775600
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001226727766173015100
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 008067428741755100
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001226727766189000
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001226727766122629392300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001226727766189000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 008067428189000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 008067428176700
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001226727766190000
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A 00122672776697492400
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A 008067428741755100
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