Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.91 99.08 98.00 100.00 96.15 99.30 99.23 93.62


Total tests in report: 914
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.56 46.56 63.19 63.19 48.93 48.93 86.53 86.53 0.00 0.00 67.87 67.87 49.33 49.33 10.08 10.08 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3633452658
69.71 23.15 85.20 22.01 76.41 27.48 92.01 5.48 55.77 55.77 87.66 19.79 76.49 27.17 14.45 4.37 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.899783572
78.11 8.40 91.15 5.95 84.80 8.39 94.75 2.74 74.36 18.59 92.92 5.26 88.82 12.33 19.99 5.54 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3824365608
81.35 3.23 93.34 2.19 88.12 3.31 95.66 0.91 78.21 3.85 94.92 2.00 91.23 2.41 27.94 7.95 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4223232916
83.84 2.49 94.31 0.97 88.93 0.81 95.89 0.23 84.62 6.41 95.70 0.78 93.45 2.22 33.99 6.05 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1420097022
86.25 2.41 94.84 0.52 90.21 1.29 96.58 0.68 84.62 0.00 96.26 0.56 94.03 0.58 47.20 13.21 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3340790864
87.79 1.54 94.91 0.07 90.27 0.05 96.58 0.00 84.62 0.00 96.40 0.15 94.03 0.00 57.73 10.53 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3080431224
89.08 1.29 95.55 0.64 91.02 0.76 96.58 0.00 89.74 5.13 97.00 0.59 95.86 1.83 57.78 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2508600113
90.29 1.21 95.58 0.04 92.14 1.11 97.26 0.68 89.74 0.00 97.11 0.11 95.86 0.00 64.33 6.55 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3854943263
91.40 1.11 97.81 2.23 94.11 1.97 97.95 0.68 89.74 0.00 98.55 1.45 97.01 1.16 64.61 0.28 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.656433252
92.51 1.11 98.22 0.41 95.09 0.99 97.95 0.00 89.74 0.00 98.55 0.00 97.11 0.10 70.88 6.27 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2569622997
93.09 0.59 98.39 0.17 95.22 0.13 97.95 0.00 89.74 0.00 98.67 0.11 97.11 0.00 74.58 3.70 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1090765827
93.57 0.48 98.39 0.00 95.22 0.00 97.95 0.00 89.74 0.00 98.67 0.00 97.11 0.00 77.94 3.36 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1790208479
93.96 0.39 98.45 0.06 95.27 0.05 97.95 0.00 89.74 0.00 98.67 0.00 97.11 0.00 80.57 2.63 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3406537404
94.29 0.33 98.45 0.00 95.32 0.05 99.77 1.83 89.74 0.00 98.67 0.00 97.21 0.10 80.91 0.34 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1488074513
94.58 0.29 98.48 0.04 95.40 0.08 99.77 0.00 89.74 0.00 98.67 0.00 97.21 0.00 82.81 1.90 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3175020822
94.79 0.21 98.48 0.00 95.40 0.00 99.77 0.00 89.74 0.00 98.67 0.00 97.40 0.19 84.10 1.29 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2589782021
95.00 0.20 98.52 0.04 95.73 0.33 99.77 0.00 90.38 0.64 98.70 0.04 97.50 0.10 84.38 0.28 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2959802995
95.19 0.19 98.54 0.02 95.73 0.00 99.77 0.00 91.67 1.28 98.74 0.04 97.50 0.00 84.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2640058826
95.37 0.18 98.58 0.04 95.83 0.10 99.77 0.00 91.67 0.00 98.74 0.00 98.17 0.67 84.83 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3079991014
95.54 0.17 98.58 0.00 95.83 0.00 99.77 0.00 91.67 0.00 98.74 0.00 98.17 0.00 86.00 1.18 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.3216472119
95.69 0.15 98.58 0.00 96.56 0.73 99.77 0.00 91.67 0.00 98.74 0.00 98.17 0.00 86.34 0.34 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.902789210
95.84 0.15 98.58 0.00 96.56 0.00 99.77 0.00 91.67 0.00 98.74 0.00 98.17 0.00 87.40 1.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2000851393
95.99 0.15 98.63 0.06 96.64 0.08 99.77 0.00 92.31 0.64 98.81 0.07 98.36 0.19 87.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1630472758
96.13 0.14 98.63 0.00 96.66 0.03 99.77 0.00 92.31 0.00 98.81 0.00 98.46 0.10 88.24 0.84 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.3451734566
96.26 0.14 98.69 0.06 96.69 0.03 99.77 0.00 92.95 0.64 98.89 0.07 98.55 0.10 88.30 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2470581458
96.39 0.13 98.73 0.04 96.74 0.05 99.77 0.00 93.59 0.64 98.93 0.04 98.65 0.10 88.35 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2671567838
96.51 0.12 98.73 0.00 96.74 0.00 99.77 0.00 93.59 0.00 98.93 0.00 98.65 0.00 89.19 0.84 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4105320412
96.63 0.12 98.76 0.04 96.76 0.03 99.77 0.00 94.23 0.64 98.96 0.04 98.75 0.10 89.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1546849253
96.75 0.12 98.80 0.04 96.79 0.03 99.77 0.00 94.87 0.64 99.00 0.04 98.84 0.10 89.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3944909225
96.87 0.12 98.84 0.04 96.81 0.03 99.77 0.00 95.51 0.64 99.04 0.04 98.94 0.10 89.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3090983520
96.99 0.12 98.86 0.02 96.84 0.03 99.77 0.00 96.15 0.64 99.07 0.04 99.04 0.10 89.19 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.713629267
97.06 0.07 98.90 0.04 96.84 0.00 99.77 0.00 96.15 0.00 99.07 0.00 99.04 0.00 89.64 0.45 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1705006623
97.12 0.07 98.95 0.06 97.02 0.18 100.00 0.23 96.15 0.00 99.07 0.00 99.04 0.00 89.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3378867664
97.18 0.06 98.95 0.00 97.42 0.40 100.00 0.00 96.15 0.00 99.07 0.00 99.04 0.00 89.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.231606336
97.23 0.05 98.99 0.04 97.52 0.10 100.00 0.00 96.15 0.00 99.15 0.07 99.13 0.10 89.70 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2229889982
97.28 0.05 98.99 0.00 97.52 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.13 0.00 90.03 0.34 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.155786680
97.33 0.05 98.99 0.00 97.52 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.13 0.00 90.37 0.34 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2841075993
97.38 0.05 98.99 0.00 97.52 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.13 0.00 90.71 0.34 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2067057448
97.43 0.05 98.99 0.00 97.85 0.33 100.00 0.00 96.15 0.00 99.15 0.00 99.13 0.00 90.71 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1860448290
97.46 0.03 98.99 0.00 97.88 0.03 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.10 90.82 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1619509924
97.49 0.03 98.99 0.00 97.88 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 91.04 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1902578302
97.52 0.03 98.99 0.00 97.88 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 91.27 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1586178258
97.56 0.03 98.99 0.00 97.88 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 91.49 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.551513831
97.59 0.03 98.99 0.00 97.88 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 91.71 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1492079805
97.61 0.03 98.99 0.00 97.90 0.03 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 91.88 0.17 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2888439307
97.63 0.02 99.01 0.02 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 91.99 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3754875067
97.65 0.02 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.11 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3643638873
97.67 0.02 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.22 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1754202643
97.68 0.02 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.33 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2920765036
97.70 0.02 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.44 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1023623778
97.71 0.02 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.55 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4141962986
97.73 0.02 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.67 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.4286909426
97.74 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.72 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2724324080
97.75 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.78 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1825550732
97.75 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.83 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3485102053
97.76 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.89 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2258615347
97.77 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 92.95 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2364278987
97.78 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.00 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.10264569
97.79 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.06 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.489108948
97.79 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.11 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.3504948263
97.80 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.17 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1897153700
97.81 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.23 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1237305242
97.82 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.28 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.3879703745
97.83 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.34 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.528473811
97.83 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.39 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.89524474
97.84 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.45 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1702976168
97.85 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.51 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.737114539
97.86 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.56 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.316242607
97.87 0.01 99.01 0.00 97.90 0.00 100.00 0.00 96.15 0.00 99.15 0.00 99.23 0.00 93.62 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2890738075
97.87 0.01 99.03 0.02 97.90 0.00 100.00 0.00 96.15 0.00 99.18 0.04 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3765486086
97.88 0.01 99.05 0.02 97.90 0.00 100.00 0.00 96.15 0.00 99.22 0.04 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.752182343
97.89 0.01 99.06 0.02 97.90 0.00 100.00 0.00 96.15 0.00 99.26 0.04 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3032872548
97.90 0.01 99.08 0.02 97.90 0.00 100.00 0.00 96.15 0.00 99.30 0.04 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.3793379452
97.90 0.01 99.08 0.00 97.95 0.05 100.00 0.00 96.15 0.00 99.30 0.00 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.135021903
97.91 0.01 99.08 0.00 97.98 0.03 100.00 0.00 96.15 0.00 99.30 0.00 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1866423913
97.91 0.01 99.08 0.00 98.00 0.03 100.00 0.00 96.15 0.00 99.30 0.00 99.23 0.00 93.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.4063597911

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3516211400
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1185740609
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1949375744
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1363491125
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2292611705
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3902435054
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1600646952
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2810069521
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2356950799
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2278743599
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2893865090
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4214447070
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2355316729
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2452160065
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2266009080
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1783875283
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.64519346
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1135462425
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3988346513
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.308537388
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3150034590
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3245327785
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.4125126870
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3763936141
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2816587688
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1871965748
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1646032133
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.491246342
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1174066050
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2795320358
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1115010403
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1304086646
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2445005499
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3472400883
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1133674040
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.4181528882
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.586505362
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1740086524
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.517148037
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.659779605
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.528953068
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1798947302
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2142973210
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1856847796
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2283622424
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.300405469
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3705487709
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1460001228
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3831076314
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1575894322
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4000355800
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2748905884
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2137562458
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2347234231
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2080525647
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1784581123
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.767050257
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3715354610
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1148571187
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2608882991
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.611262324
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2120649853
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1273434820
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.215093034
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1213764921
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/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2980626253
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.836213052
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.4093471739
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.78143490
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3953177582
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1560788350
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2329446105
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Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2304452180 Sep 18 06:21:54 AM UTC 24 Sep 18 06:21:57 AM UTC 24 2484260411 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.3094175392 Sep 18 06:21:54 AM UTC 24 Sep 18 06:21:59 AM UTC 24 2126040417 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1141874227 Sep 18 06:21:57 AM UTC 24 Sep 18 06:22:01 AM UTC 24 2277201202 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.571356239 Sep 18 06:21:57 AM UTC 24 Sep 18 06:22:01 AM UTC 24 2274107349 ps
T1 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.459295616 Sep 18 06:21:56 AM UTC 24 Sep 18 06:22:02 AM UTC 24 2443791107 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.297324468 Sep 18 06:21:59 AM UTC 24 Sep 18 06:22:03 AM UTC 24 3960477434 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3633452658 Sep 18 06:21:58 AM UTC 24 Sep 18 06:22:06 AM UTC 24 2508577408 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1586178258 Sep 18 06:22:00 AM UTC 24 Sep 18 06:22:07 AM UTC 24 3891934004 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1717961008 Sep 18 06:22:07 AM UTC 24 Sep 18 06:22:10 AM UTC 24 2146812673 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3378867664 Sep 18 06:22:05 AM UTC 24 Sep 18 06:22:10 AM UTC 24 2038411470 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.656433252 Sep 18 06:22:37 AM UTC 24 Sep 18 06:22:47 AM UTC 24 2201205403 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3460147734 Sep 18 06:21:58 AM UTC 24 Sep 18 06:22:11 AM UTC 24 2610591086 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3434622669 Sep 18 06:22:07 AM UTC 24 Sep 18 06:22:11 AM UTC 24 2222917090 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.1598332037 Sep 18 06:22:08 AM UTC 24 Sep 18 06:22:12 AM UTC 24 2627126156 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1655002585 Sep 18 06:22:09 AM UTC 24 Sep 18 06:22:12 AM UTC 24 2955367791 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.2824324908 Sep 18 06:22:07 AM UTC 24 Sep 18 06:22:12 AM UTC 24 2461987175 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1619509924 Sep 18 06:22:04 AM UTC 24 Sep 18 06:22:13 AM UTC 24 11416791880 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3546553625 Sep 18 06:22:08 AM UTC 24 Sep 18 06:22:13 AM UTC 24 2540296265 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1163761782 Sep 18 06:22:09 AM UTC 24 Sep 18 06:22:14 AM UTC 24 3674364845 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2470581458 Sep 18 06:22:02 AM UTC 24 Sep 18 06:22:15 AM UTC 24 3898257698 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.1869057123 Sep 18 06:22:08 AM UTC 24 Sep 18 06:22:16 AM UTC 24 2049999228 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2488388852 Sep 18 06:22:08 AM UTC 24 Sep 18 06:22:16 AM UTC 24 2514604307 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.1051969780 Sep 18 06:22:14 AM UTC 24 Sep 18 06:22:17 AM UTC 24 2485335100 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3486542238 Sep 18 06:22:15 AM UTC 24 Sep 18 06:22:17 AM UTC 24 2533271385 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1827338789 Sep 18 06:22:03 AM UTC 24 Sep 18 06:22:17 AM UTC 24 7026696130 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.2262110690 Sep 18 06:22:16 AM UTC 24 Sep 18 06:22:19 AM UTC 24 2199301749 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.266168790 Sep 18 06:22:16 AM UTC 24 Sep 18 06:22:20 AM UTC 24 2354399381 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.4249312904 Sep 18 06:22:17 AM UTC 24 Sep 18 06:22:20 AM UTC 24 2550707101 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.1988870126 Sep 18 06:22:14 AM UTC 24 Sep 18 06:22:20 AM UTC 24 2019449271 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.230426126 Sep 18 06:22:18 AM UTC 24 Sep 18 06:22:21 AM UTC 24 3952690362 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.467906420 Sep 18 06:22:17 AM UTC 24 Sep 18 06:22:22 AM UTC 24 2619916788 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.4066293005 Sep 18 06:22:14 AM UTC 24 Sep 18 06:22:23 AM UTC 24 2112323118 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.192150451 Sep 18 06:22:20 AM UTC 24 Sep 18 06:22:24 AM UTC 24 2959970275 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1972985220 Sep 18 06:22:03 AM UTC 24 Sep 18 06:22:25 AM UTC 24 33410485664 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.2083727136 Sep 18 06:22:22 AM UTC 24 Sep 18 06:22:27 AM UTC 24 8578639255 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.119623678 Sep 18 06:22:23 AM UTC 24 Sep 18 06:22:27 AM UTC 24 2115106735 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1222418 Sep 18 06:22:25 AM UTC 24 Sep 18 06:22:28 AM UTC 24 2419667665 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3742607747 Sep 18 06:22:24 AM UTC 24 Sep 18 06:22:31 AM UTC 24 2462148746 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3339095013 Sep 18 06:22:28 AM UTC 24 Sep 18 06:22:32 AM UTC 24 2524221239 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2470523685 Sep 18 06:22:28 AM UTC 24 Sep 18 06:22:34 AM UTC 24 2197545105 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1805733361 Sep 18 06:22:18 AM UTC 24 Sep 18 06:22:34 AM UTC 24 5442741320 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.957118072 Sep 18 06:22:29 AM UTC 24 Sep 18 06:22:34 AM UTC 24 2632256368 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2487254802 Sep 18 06:22:23 AM UTC 24 Sep 18 06:22:35 AM UTC 24 2016791121 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1481421591 Sep 18 06:22:18 AM UTC 24 Sep 18 06:22:35 AM UTC 24 3852290567 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3824365608 Sep 18 06:22:21 AM UTC 24 Sep 18 06:22:35 AM UTC 24 43460828727 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1110033602 Sep 18 06:22:41 AM UTC 24 Sep 18 06:22:47 AM UTC 24 3275839521 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2589782021 Sep 18 06:22:12 AM UTC 24 Sep 18 06:22:35 AM UTC 24 14879378517 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.537443496 Sep 18 06:22:12 AM UTC 24 Sep 18 06:22:36 AM UTC 24 7223181428 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2752793933 Sep 18 06:22:26 AM UTC 24 Sep 18 06:22:37 AM UTC 24 2309690412 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1327916583 Sep 18 06:22:31 AM UTC 24 Sep 18 06:22:37 AM UTC 24 3245652061 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.686496902 Sep 18 06:22:34 AM UTC 24 Sep 18 06:22:37 AM UTC 24 3860872594 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3750071227 Sep 18 06:22:35 AM UTC 24 Sep 18 06:22:38 AM UTC 24 3509595114 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3071538631 Sep 18 06:22:33 AM UTC 24 Sep 18 06:22:38 AM UTC 24 4162343945 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1418831804 Sep 18 06:22:36 AM UTC 24 Sep 18 06:22:38 AM UTC 24 2062248294 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.3998546878 Sep 18 06:22:37 AM UTC 24 Sep 18 06:22:40 AM UTC 24 2172148672 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1149910002 Sep 18 06:22:37 AM UTC 24 Sep 18 06:22:40 AM UTC 24 2517780022 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.1473877391 Sep 18 06:22:38 AM UTC 24 Sep 18 06:22:42 AM UTC 24 2134750520 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.899783572 Sep 18 06:22:03 AM UTC 24 Sep 18 06:22:43 AM UTC 24 29384917137 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1800748407 Sep 18 06:22:39 AM UTC 24 Sep 18 06:22:45 AM UTC 24 2860337406 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4157995730 Sep 18 06:22:38 AM UTC 24 Sep 18 06:22:46 AM UTC 24 2360037050 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1023623778 Sep 18 06:22:36 AM UTC 24 Sep 18 06:22:46 AM UTC 24 9736476837 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2900655385 Sep 18 06:22:42 AM UTC 24 Sep 18 06:22:47 AM UTC 24 4732872833 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.3307933559 Sep 18 06:22:38 AM UTC 24 Sep 18 06:22:48 AM UTC 24 2512127699 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3574901558 Sep 18 06:22:39 AM UTC 24 Sep 18 06:22:50 AM UTC 24 2609569259 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.810508729 Sep 18 06:22:47 AM UTC 24 Sep 18 06:22:50 AM UTC 24 2162346182 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.621298094 Sep 18 06:22:47 AM UTC 24 Sep 18 06:22:50 AM UTC 24 2229483977 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1488074513 Sep 18 06:22:14 AM UTC 24 Sep 18 06:22:51 AM UTC 24 42093019728 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.715069262 Sep 18 06:22:43 AM UTC 24 Sep 18 06:22:52 AM UTC 24 3293888481 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3292178589 Sep 18 06:22:48 AM UTC 24 Sep 18 06:22:53 AM UTC 24 2632948328 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4028970483 Sep 18 06:22:44 AM UTC 24 Sep 18 06:22:53 AM UTC 24 10439526170 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3944909225 Sep 18 06:22:52 AM UTC 24 Sep 18 06:22:55 AM UTC 24 2704878951 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.1339848344 Sep 18 06:22:22 AM UTC 24 Sep 18 06:22:56 AM UTC 24 22049246672 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.796641117 Sep 18 06:22:36 AM UTC 24 Sep 18 06:22:56 AM UTC 24 22066149514 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.4237821650 Sep 18 06:22:48 AM UTC 24 Sep 18 06:22:56 AM UTC 24 3562551966 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.1646251408 Sep 18 06:22:47 AM UTC 24 Sep 18 06:22:57 AM UTC 24 2465147849 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1229784831 Sep 18 06:22:47 AM UTC 24 Sep 18 06:22:57 AM UTC 24 2510349979 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2301261855 Sep 18 06:22:51 AM UTC 24 Sep 18 06:22:59 AM UTC 24 7355144427 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.4221512027 Sep 18 06:22:47 AM UTC 24 Sep 18 06:23:00 AM UTC 24 2012433064 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.1962113118 Sep 18 06:22:57 AM UTC 24 Sep 18 06:23:00 AM UTC 24 2552020156 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4223232916 Sep 18 06:22:45 AM UTC 24 Sep 18 06:23:00 AM UTC 24 13122043028 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3975072003 Sep 18 06:22:55 AM UTC 24 Sep 18 06:23:00 AM UTC 24 2115964324 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.504396494 Sep 18 06:22:56 AM UTC 24 Sep 18 06:23:00 AM UTC 24 2491354452 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1139758564 Sep 18 06:22:05 AM UTC 24 Sep 18 06:23:01 AM UTC 24 22012943321 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4089548816 Sep 18 06:22:50 AM UTC 24 Sep 18 06:23:01 AM UTC 24 3247455312 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.183065471 Sep 18 06:22:58 AM UTC 24 Sep 18 06:23:03 AM UTC 24 3199871257 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.230802688 Sep 18 06:22:54 AM UTC 24 Sep 18 06:23:04 AM UTC 24 2015315108 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.1819243487 Sep 18 06:23:01 AM UTC 24 Sep 18 06:23:05 AM UTC 24 2037992656 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3286388052 Sep 18 06:22:56 AM UTC 24 Sep 18 06:23:05 AM UTC 24 2031281191 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.868820670 Sep 18 06:22:58 AM UTC 24 Sep 18 06:23:05 AM UTC 24 4087880407 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2089296298 Sep 18 06:22:58 AM UTC 24 Sep 18 06:23:05 AM UTC 24 2613286660 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2814478048 Sep 18 06:22:59 AM UTC 24 Sep 18 06:23:07 AM UTC 24 4628492537 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3340790864 Sep 18 06:22:11 AM UTC 24 Sep 18 06:23:08 AM UTC 24 60117960036 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.85047346 Sep 18 06:23:02 AM UTC 24 Sep 18 06:23:09 AM UTC 24 2441587868 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.698031699 Sep 18 06:22:46 AM UTC 24 Sep 18 06:23:10 AM UTC 24 22100528508 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3694050641 Sep 18 06:23:06 AM UTC 24 Sep 18 06:23:11 AM UTC 24 3531404518 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1551749030 Sep 18 06:22:53 AM UTC 24 Sep 18 06:23:12 AM UTC 24 5657668158 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.1878414668 Sep 18 06:23:02 AM UTC 24 Sep 18 06:23:12 AM UTC 24 2205529688 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2196338442 Sep 18 06:23:06 AM UTC 24 Sep 18 06:23:12 AM UTC 24 5110781074 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.611438248 Sep 18 06:23:01 AM UTC 24 Sep 18 06:23:12 AM UTC 24 11100444775 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2685503930 Sep 18 06:23:08 AM UTC 24 Sep 18 06:23:13 AM UTC 24 2490239783 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.3048268908 Sep 18 06:23:01 AM UTC 24 Sep 18 06:23:13 AM UTC 24 4577877761 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4213370508 Sep 18 06:23:06 AM UTC 24 Sep 18 06:23:13 AM UTC 24 9213357891 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4037733935 Sep 18 06:23:04 AM UTC 24 Sep 18 06:23:13 AM UTC 24 2611855242 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1990072622 Sep 18 06:23:08 AM UTC 24 Sep 18 06:23:13 AM UTC 24 2027450578 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2812081767 Sep 18 06:23:08 AM UTC 24 Sep 18 06:23:13 AM UTC 24 9611785441 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.1355757152 Sep 18 06:23:08 AM UTC 24 Sep 18 06:23:15 AM UTC 24 2115251298 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.4143569947 Sep 18 06:23:02 AM UTC 24 Sep 18 06:23:16 AM UTC 24 2111186021 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3228852734 Sep 18 06:23:26 AM UTC 24 Sep 18 06:23:30 AM UTC 24 2535055447 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4105320412 Sep 18 06:23:00 AM UTC 24 Sep 18 06:23:30 AM UTC 24 43085412506 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.123367136 Sep 18 06:23:12 AM UTC 24 Sep 18 06:23:16 AM UTC 24 2984954615 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.489112450 Sep 18 06:23:11 AM UTC 24 Sep 18 06:23:16 AM UTC 24 2515109409 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.2772120090 Sep 18 06:23:04 AM UTC 24 Sep 18 06:23:17 AM UTC 24 2510982739 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2959802995 Sep 18 06:23:13 AM UTC 24 Sep 18 06:23:18 AM UTC 24 5824533552 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.228354809 Sep 18 06:23:14 AM UTC 24 Sep 18 06:23:18 AM UTC 24 2252097731 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2418632430 Sep 18 06:23:13 AM UTC 24 Sep 18 06:23:18 AM UTC 24 3304345122 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.409191429 Sep 18 06:23:09 AM UTC 24 Sep 18 06:23:18 AM UTC 24 2186188158 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3090983520 Sep 18 06:23:13 AM UTC 24 Sep 18 06:23:18 AM UTC 24 3345341487 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1433857475 Sep 18 06:23:11 AM UTC 24 Sep 18 06:23:19 AM UTC 24 2611469080 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2417752382 Sep 18 06:23:14 AM UTC 24 Sep 18 06:23:20 AM UTC 24 2013920103 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.1484716268 Sep 18 06:23:14 AM UTC 24 Sep 18 06:23:20 AM UTC 24 2459763548 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.3431466409 Sep 18 06:23:07 AM UTC 24 Sep 18 06:23:21 AM UTC 24 2383503636 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.3891009829 Sep 18 06:23:14 AM UTC 24 Sep 18 06:23:22 AM UTC 24 2508807172 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.4176337953 Sep 18 06:23:14 AM UTC 24 Sep 18 06:23:22 AM UTC 24 2108226903 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.405091364 Sep 18 06:23:17 AM UTC 24 Sep 18 06:23:22 AM UTC 24 4810298618 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2664585793 Sep 18 06:23:16 AM UTC 24 Sep 18 06:23:23 AM UTC 24 2623728625 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2794422198 Sep 18 06:23:20 AM UTC 24 Sep 18 06:23:24 AM UTC 24 2164358080 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3894091271 Sep 18 06:23:20 AM UTC 24 Sep 18 06:23:24 AM UTC 24 2535616088 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2231594045 Sep 18 06:23:22 AM UTC 24 Sep 18 06:23:24 AM UTC 24 3208658623 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2569622997 Sep 18 06:22:11 AM UTC 24 Sep 18 06:23:25 AM UTC 24 125489972509 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.261671842 Sep 18 06:23:20 AM UTC 24 Sep 18 06:23:25 AM UTC 24 2128111977 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.2869979329 Sep 18 06:23:20 AM UTC 24 Sep 18 06:23:25 AM UTC 24 2459200526 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1325503374 Sep 18 06:23:22 AM UTC 24 Sep 18 06:23:25 AM UTC 24 2627369517 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.730589954 Sep 18 06:23:19 AM UTC 24 Sep 18 06:23:26 AM UTC 24 2016072936 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2209453459 Sep 18 06:23:19 AM UTC 24 Sep 18 06:23:26 AM UTC 24 13875809862 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1896486125 Sep 18 06:23:17 AM UTC 24 Sep 18 06:23:27 AM UTC 24 8476613043 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2895063330 Sep 18 06:23:23 AM UTC 24 Sep 18 06:23:27 AM UTC 24 7159533931 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.1167917941 Sep 18 06:23:19 AM UTC 24 Sep 18 06:23:27 AM UTC 24 4861345215 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4013651432 Sep 18 06:23:14 AM UTC 24 Sep 18 06:23:28 AM UTC 24 3561978281 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1259656805 Sep 18 06:23:08 AM UTC 24 Sep 18 06:23:28 AM UTC 24 4769736154 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.362031555 Sep 18 06:23:19 AM UTC 24 Sep 18 06:23:28 AM UTC 24 8203066305 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3765486086 Sep 18 06:23:23 AM UTC 24 Sep 18 06:23:29 AM UTC 24 3226933591 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3944678499 Sep 18 06:22:19 AM UTC 24 Sep 18 06:23:29 AM UTC 24 99358600319 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3445795599 Sep 18 06:22:52 AM UTC 24 Sep 18 06:23:29 AM UTC 24 35703228913 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1584937368 Sep 18 06:23:26 AM UTC 24 Sep 18 06:23:30 AM UTC 24 2107279860 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1274535098 Sep 18 06:23:28 AM UTC 24 Sep 18 06:23:30 AM UTC 24 2887249357 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.713641705 Sep 18 06:23:26 AM UTC 24 Sep 18 06:23:31 AM UTC 24 2463269976 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2671567838 Sep 18 06:22:10 AM UTC 24 Sep 18 06:23:31 AM UTC 24 527178694177 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2397487553 Sep 18 06:23:25 AM UTC 24 Sep 18 06:23:32 AM UTC 24 2009535920 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1638689284 Sep 18 06:23:28 AM UTC 24 Sep 18 06:23:32 AM UTC 24 9238236978 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2394699660 Sep 18 06:23:29 AM UTC 24 Sep 18 06:23:32 AM UTC 24 2050528084 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2663063203 Sep 18 06:23:26 AM UTC 24 Sep 18 06:23:33 AM UTC 24 2113609086 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3485102053 Sep 18 06:23:23 AM UTC 24 Sep 18 06:23:33 AM UTC 24 3513834651 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1420097022 Sep 18 06:23:25 AM UTC 24 Sep 18 06:23:33 AM UTC 24 21267147396 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4202406369 Sep 18 06:23:17 AM UTC 24 Sep 18 06:23:35 AM UTC 24 3541984373 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1839901421 Sep 18 06:23:27 AM UTC 24 Sep 18 06:23:35 AM UTC 24 2612314448 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1499353041 Sep 18 06:23:32 AM UTC 24 Sep 18 06:23:35 AM UTC 24 5432500057 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2885007623 Sep 18 06:23:31 AM UTC 24 Sep 18 06:23:35 AM UTC 24 3580845937 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.4070856541 Sep 18 06:23:30 AM UTC 24 Sep 18 06:23:35 AM UTC 24 2481966090 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3451787488 Sep 18 06:23:32 AM UTC 24 Sep 18 06:23:36 AM UTC 24 3535055735 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.4162559457 Sep 18 06:23:28 AM UTC 24 Sep 18 06:23:36 AM UTC 24 5394139961 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.2898812163 Sep 18 06:23:33 AM UTC 24 Sep 18 06:23:37 AM UTC 24 2806608958 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.2429441671 Sep 18 06:23:30 AM UTC 24 Sep 18 06:23:38 AM UTC 24 2183264408 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2082103998 Sep 18 06:23:35 AM UTC 24 Sep 18 06:23:38 AM UTC 24 2718438448 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.111599529 Sep 18 06:23:30 AM UTC 24 Sep 18 06:23:38 AM UTC 24 2517354305 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.243406805 Sep 18 06:23:30 AM UTC 24 Sep 18 06:23:38 AM UTC 24 2112555404 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4103212769 Sep 18 06:23:29 AM UTC 24 Sep 18 06:23:39 AM UTC 24 13382497824 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1653192502 Sep 18 06:23:28 AM UTC 24 Sep 18 06:23:39 AM UTC 24 3561095367 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.448188839 Sep 18 06:23:31 AM UTC 24 Sep 18 06:23:40 AM UTC 24 2611210514 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2763469746 Sep 18 06:23:34 AM UTC 24 Sep 18 06:23:41 AM UTC 24 2016528034 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.4186209295 Sep 18 06:23:39 AM UTC 24 Sep 18 06:23:42 AM UTC 24 2177207528 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3114562330 Sep 18 06:23:29 AM UTC 24 Sep 18 06:23:42 AM UTC 24 15058127513 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3699343447 Sep 18 06:23:34 AM UTC 24 Sep 18 06:23:42 AM UTC 24 2113334035 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.162053604 Sep 18 06:23:39 AM UTC 24 Sep 18 06:23:42 AM UTC 24 2496422882 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.697626466 Sep 18 06:23:39 AM UTC 24 Sep 18 06:23:43 AM UTC 24 2037655910 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.989069100 Sep 18 06:23:36 AM UTC 24 Sep 18 06:23:44 AM UTC 24 4018939877 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.608778498 Sep 18 06:23:42 AM UTC 24 Sep 18 06:23:45 AM UTC 24 3470194465 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.4199193847 Sep 18 06:23:35 AM UTC 24 Sep 18 06:23:46 AM UTC 24 2512026881 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1541906651 Sep 18 06:23:34 AM UTC 24 Sep 18 06:23:46 AM UTC 24 2139644731 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.4246012251 Sep 18 06:23:37 AM UTC 24 Sep 18 06:23:47 AM UTC 24 2843721448 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4096514727 Sep 18 06:23:43 AM UTC 24 Sep 18 06:23:47 AM UTC 24 2922618049 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.4182488110 Sep 18 06:23:34 AM UTC 24 Sep 18 06:23:47 AM UTC 24 2480654183 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.3642467093 Sep 18 06:23:40 AM UTC 24 Sep 18 06:23:47 AM UTC 24 2184794616 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1408001917 Sep 18 06:23:40 AM UTC 24 Sep 18 06:23:49 AM UTC 24 2512422517 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2349790291 Sep 18 06:23:38 AM UTC 24 Sep 18 06:23:49 AM UTC 24 3617406430 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.455940486 Sep 18 06:23:35 AM UTC 24 Sep 18 06:23:50 AM UTC 24 3578240310 ps
T266 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1199762859 Sep 18 06:23:46 AM UTC 24 Sep 18 06:23:52 AM UTC 24 2453035921 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3912766875 Sep 18 06:23:48 AM UTC 24 Sep 18 06:23:52 AM UTC 24 2639837917 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2610794497 Sep 18 06:23:47 AM UTC 24 Sep 18 06:23:52 AM UTC 24 2530956006 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2524063924 Sep 18 06:22:21 AM UTC 24 Sep 18 06:23:52 AM UTC 24 38255443911 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1982250211 Sep 18 06:23:43 AM UTC 24 Sep 18 06:23:53 AM UTC 24 3561989081 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.799041451 Sep 18 06:23:46 AM UTC 24 Sep 18 06:23:53 AM UTC 24 2109126295 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1172127220 Sep 18 06:23:41 AM UTC 24 Sep 18 06:23:54 AM UTC 24 2611713839 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1499573153 Sep 18 06:23:50 AM UTC 24 Sep 18 06:23:54 AM UTC 24 5111857167 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3667726081 Sep 18 06:23:34 AM UTC 24 Sep 18 06:23:55 AM UTC 24 10856227552 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1945800234 Sep 18 06:23:41 AM UTC 24 Sep 18 06:23:55 AM UTC 24 2787621140 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3660862760 Sep 18 06:24:05 AM UTC 24 Sep 18 06:24:07 AM UTC 24 2223439207 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.1724910332 Sep 18 06:23:45 AM UTC 24 Sep 18 06:23:56 AM UTC 24 2012274450 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3269609376 Sep 18 06:23:53 AM UTC 24 Sep 18 06:23:56 AM UTC 24 2031370917 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.10264569 Sep 18 06:23:37 AM UTC 24 Sep 18 06:23:56 AM UTC 24 26829729536 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1255381503 Sep 18 06:23:47 AM UTC 24 Sep 18 06:23:57 AM UTC 24 2069018339 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2364278987 Sep 18 06:23:33 AM UTC 24 Sep 18 06:23:57 AM UTC 24 30106677418 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1723179110 Sep 18 06:23:54 AM UTC 24 Sep 18 06:23:57 AM UTC 24 2169191567 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3796885747 Sep 18 06:23:54 AM UTC 24 Sep 18 06:23:57 AM UTC 24 2527364690 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2916881355 Sep 18 06:23:55 AM UTC 24 Sep 18 06:23:59 AM UTC 24 2038482702 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1567256175 Sep 18 06:23:51 AM UTC 24 Sep 18 06:23:59 AM UTC 24 4363598540 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.1642339782 Sep 18 06:23:55 AM UTC 24 Sep 18 06:24:00 AM UTC 24 2515561690 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1019270367 Sep 18 06:23:55 AM UTC 24 Sep 18 06:24:01 AM UTC 24 2615024601 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3726235931 Sep 18 06:23:44 AM UTC 24 Sep 18 06:24:01 AM UTC 24 13933055950 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.3957269059 Sep 18 06:23:58 AM UTC 24 Sep 18 06:24:02 AM UTC 24 2032169758 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.231606336 Sep 18 06:22:12 AM UTC 24 Sep 18 06:24:07 AM UTC 24 41153191936 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2615636894 Sep 18 06:23:48 AM UTC 24 Sep 18 06:24:02 AM UTC 24 3303093447 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2813319313 Sep 18 06:23:55 AM UTC 24 Sep 18 06:24:03 AM UTC 24 3228431719 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.995203704 Sep 18 06:23:58 AM UTC 24 Sep 18 06:24:03 AM UTC 24 5566805847 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.268726705 Sep 18 06:23:25 AM UTC 24 Sep 18 06:24:03 AM UTC 24 13931047110 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.3427405490 Sep 18 06:23:59 AM UTC 24 Sep 18 06:24:03 AM UTC 24 2119888558 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2166945340 Sep 18 06:23:39 AM UTC 24 Sep 18 06:24:03 AM UTC 24 9455491011 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.689657728 Sep 18 06:23:57 AM UTC 24 Sep 18 06:24:04 AM UTC 24 6115127151 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.4047428413 Sep 18 06:24:00 AM UTC 24 Sep 18 06:24:04 AM UTC 24 2099553047 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1819672102 Sep 18 06:23:49 AM UTC 24 Sep 18 06:24:05 AM UTC 24 3485451052 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.3011772899 Sep 18 06:24:04 AM UTC 24 Sep 18 06:24:07 AM UTC 24 5531570280 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.195665367 Sep 18 06:24:05 AM UTC 24 Sep 18 06:24:08 AM UTC 24 2039604062 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3525789746 Sep 18 06:23:53 AM UTC 24 Sep 18 06:24:08 AM UTC 24 7745159736 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2632144218 Sep 18 06:24:01 AM UTC 24 Sep 18 06:24:08 AM UTC 24 2614646016 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.556073399 Sep 18 06:24:05 AM UTC 24 Sep 18 06:24:08 AM UTC 24 2479293271 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4154195359 Sep 18 06:24:02 AM UTC 24 Sep 18 06:24:08 AM UTC 24 3102073487 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.4221671716 Sep 18 06:24:06 AM UTC 24 Sep 18 06:24:09 AM UTC 24 2240926392 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.4166918883 Sep 18 06:23:24 AM UTC 24 Sep 18 06:24:09 AM UTC 24 69388532376 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.60381432 Sep 18 06:24:01 AM UTC 24 Sep 18 06:24:10 AM UTC 24 2510335425 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3754875067 Sep 18 06:23:14 AM UTC 24 Sep 18 06:24:11 AM UTC 24 75779183412 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.2355848449 Sep 18 06:24:00 AM UTC 24 Sep 18 06:24:12 AM UTC 24 2486541192 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1588536339 Sep 18 06:24:08 AM UTC 24 Sep 18 06:24:12 AM UTC 24 2679813651 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2168348281 Sep 18 06:24:10 AM UTC 24 Sep 18 06:24:12 AM UTC 24 5144704148 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.752182343 Sep 18 06:23:57 AM UTC 24 Sep 18 06:24:13 AM UTC 24 3342096196 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1758190688 Sep 18 06:24:07 AM UTC 24 Sep 18 06:24:14 AM UTC 24 2526601641 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1288044498 Sep 18 06:24:10 AM UTC 24 Sep 18 06:24:14 AM UTC 24 3268006711 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1180558789 Sep 18 06:24:04 AM UTC 24 Sep 18 06:24:14 AM UTC 24 2282836459 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1151312287 Sep 18 06:24:01 AM UTC 24 Sep 18 06:24:16 AM UTC 24 3511254103 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.239739652 Sep 18 06:24:11 AM UTC 24 Sep 18 06:24:17 AM UTC 24 2020122117 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3245442971 Sep 18 06:24:13 AM UTC 24 Sep 18 06:24:17 AM UTC 24 2081829887 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2850554977 Sep 18 06:24:15 AM UTC 24 Sep 18 06:24:18 AM UTC 24 12513958162 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1902963239 Sep 18 06:24:14 AM UTC 24 Sep 18 06:24:18 AM UTC 24 3052311896 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2576460186 Sep 18 06:22:53 AM UTC 24 Sep 18 06:24:19 AM UTC 24 132637068402 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1749933534 Sep 18 06:24:13 AM UTC 24 Sep 18 06:24:21 AM UTC 24 2610893076 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1529817803 Sep 18 06:23:58 AM UTC 24 Sep 18 06:24:21 AM UTC 24 7743439134 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.646737605 Sep 18 06:24:08 AM UTC 24 Sep 18 06:24:22 AM UTC 24 4840663728 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2377508128 Sep 18 06:24:10 AM UTC 24 Sep 18 06:24:22 AM UTC 24 3280802161 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.346702632 Sep 18 06:24:12 AM UTC 24 Sep 18 06:24:22 AM UTC 24 2109291130 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2420102409 Sep 18 06:24:04 AM UTC 24 Sep 18 06:24:23 AM UTC 24 26355182056 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2083641312 Sep 18 06:24:17 AM UTC 24 Sep 18 06:24:23 AM UTC 24 3961808293 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2099908938 Sep 18 06:24:12 AM UTC 24 Sep 18 06:24:25 AM UTC 24 2456212334 ps
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