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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 63 1 T95 1 T45 1 T141 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 16 1 T44 1 T130 2 T302 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 53 1 T37 1 T94 1 T47 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 28 1 T130 1 T46 1 T302 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 66 1 T43 1 T130 1 T45 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 15 1 T44 1 T130 1 T297 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 43 1 T37 3 T43 1 T94 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 35 1 T130 2 T46 1 T141 9
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 50 1 T36 1 T37 1 T58 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 22 1 T44 1 T130 1 T302 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 41 1 T37 1 T296 2 T304 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 31 1 T46 1 T302 1 T356 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 43 1 T34 1 T43 2 T58 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 35 1 T46 1 T357 1 T358 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 48 1 T58 1 T45 1 T296 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 37 1 T130 1 T305 1 T298 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 53 1 T43 4 T94 1 T45 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 17 1 T143 3 T294 1 T298 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 48 1 T36 1 T37 2 T45 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 23 1 T44 1 T143 1 T148 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 48 1 T37 2 T44 1 T47 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 22 1 T302 2 T356 1 T305 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 30 1 T37 1 T303 2 T294 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 34 1 T44 1 T130 1 T46 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 43 1 T296 1 T293 2 T295 4
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 34 1 T44 1 T46 2 T302 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 43 1 T37 1 T145 1 T294 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 30 1 T130 2 T143 1 T356 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 48 1 T45 2 T145 1 T132 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 28 1 T46 1 T356 1 T305 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 38 1 T37 1 T47 7 T296 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 42 1 T130 1 T46 1 T302 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 48 1 T37 1 T94 1 T95 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 26 1 T95 3 T130 2 T302 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 50 1 T47 1 T303 1 T145 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 38 1 T44 1 T130 1 T302 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 52 1 T43 2 T59 1 T94 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 28 1 T44 1 T59 7 T302 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 66 1 T36 2 T94 8 T58 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 49 1 T94 4 T46 2 T305 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 47 1 T34 1 T36 2 T58 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 31 1 T130 1 T302 2 T143 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 58 1 T45 1 T296 1 T303 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 36 1 T46 2 T302 1 T143 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 39 1 T37 2 T43 1 T59 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 38 1 T44 1 T59 7 T46 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 83 1 T43 1 T58 12 T145 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 49 1 T44 2 T302 1 T356 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 51 1 T43 1 T292 1 T47 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 20 1 T46 1 T143 1 T297 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 79 1 T36 1 T47 1 T296 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 32 1 T130 2 T298 1 T357 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 42 1 T37 1 T43 1 T59 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 46 1 T44 1 T59 2 T302 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 71 1 T45 1 T296 1 T303 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 55 1 T44 3 T46 3 T302 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 49 1 T43 1 T46 1 T292 5
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 28 1 T143 3 T356 1 T305 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 45 1 T36 7 T37 2 T43 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 62 1 T44 3 T130 1 T305 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 65 1 T34 9 T37 1 T43 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 63 1 T46 1 T143 2 T356 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 167 1 T37 4 T44 1 T43 7
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 148 1 T44 7 T302 5 T143 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 1 1 T294 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 24 1 T44 2 T356 2 T305 2


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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