Unified Coverage Report :: Cond split page

Go back

 LINE       6608
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T2,T82
1	1	Covered	T15,T82,T34

 LINE       6608
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T9,T82
1	1	Covered	T33,T34,T67

 LINE       6608
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T34
1	1	Covered	T15,T18,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T34
1	1	Covered	T82,T90,T34

 LINE       6608
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T2,T82
1	1	Covered	T15,T16,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T82,T34,T67
1	1	Covered	T15,T82,T83

 LINE       6608
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T82,T34,T67
1	1	Covered	T15,T18,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T34
1	1	Covered	T15,T83,T90

 LINE       6608
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T15
1	1	Covered	T15,T82,T33

 LINE       6608
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T18,T82
1	1	Covered	T15,T16,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T90
1	1	Covered	T18,T82,T90

 LINE       6608
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T83
1	1	Covered	T90,T34,T67

 LINE       6608
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T19
1	1	Covered	T15,T16,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T82,T34,T67
1	1	Covered	T15,T82,T34

 LINE       6608
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T34
1	1	Covered	T15,T9,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T82,T34,T67
1	1	Covered	T15,T9,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T15
1	1	Covered	T82,T90,T34

 LINE       6608
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T83
1	1	Covered	T15,T18,T82

 LINE       6608
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T80,T82,T90
1	1	Covered	T9,T82,T34

 LINE       6608
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T15,T82,T90
1	1	Covered	T15,T16,T18

 LINE       6608
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T15
1	1	Covered	T1,T15,T21

 LINE       6608
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T3,T82,T90
1	1	Covered	T3,T80,T90

 LINE       6655
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T16,T19
1	1	0	Covered	T105,T106,T115
1	1	1	Covered	T16,T19,T22

 LINE       6658
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T82,T90
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T103,T99,T104

 LINE       6661
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T18,T9
1	1	0	Covered	T105,T106,T115
1	1	1	Covered	T18,T91,T76

 LINE       6664
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T9,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T39,T40,T41

 LINE       6667
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T1,T14
1	1	0	Covered	T105,T115,T116
1	1	1	Covered	T6,T1,T14

 LINE       6669
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T28,T80
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T28,T8,T11

 LINE       6671
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T28,T9
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T28,T8,T11

 LINE       6673
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T28,T80
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T28,T8,T11

 LINE       6675
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T28,T82
1	1	0	Covered	T38,T115,T117
1	1	1	Covered	T8,T11,T13

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T28,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T8,T11,T13

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T16,T28,T82
1	1	0	Covered	T105,T106,T115
1	1	1	Covered	T8,T11,T13

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T4,T15,T29
1	1	0	Covered	T110,T38,T105
1	1	1	Covered	T4,T29,T30

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T4,T15,T20
1	1	0	Covered	T105,T106,T115
1	1	1	Covered	T4,T15,T20

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T4,T6,T1
1	1	0	Covered	T105,T118,T119
1	1	1	Covered	T4,T6,T1

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T20,T22
1	1	0	Covered	T38,T105,T120
1	1	1	Covered	T15,T20,T22

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T18,T3
1	1	0	Covered	T105,T106,T115
1	1	1	Covered	T3,T7,T12

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T1,T16
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T6,T1,T19

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T16,T18,T31
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T16,T31,T32

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T38,T115,T118
1	1	1	Covered	T16,T31,T32

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T15,T2
1	1	0	Covered	T105,T115,T117
1	1	1	Covered	T6,T2,T33

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T9,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T34,T35,T36

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T18,T82
1	1	0	Covered	T105,T106,T117
1	1	1	Covered	T34,T35,T36

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T82,T90
1	1	0	Covered	T38,T105,T121
1	1	1	Covered	T34,T35,T36

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T15,T16
1	1	0	Covered	T105,T106,T122
1	1	1	Covered	T6,T2,T33

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T82,T83
1	1	0	Covered	T105,T123,T117
1	1	1	Covered	T34,T35,T36

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T18,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T34,T35,T36

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T82,T83
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T34,T35,T36

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T1,T15
1	1	0	Covered	T105,T124,T106
1	1	1	Covered	T6,T1,T19

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T38,T105,T123
1	1	1	Covered	T34,T35,T36

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T18,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T34,T35,T36

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T82,T83
1	1	0	Covered	T105,T106,T115
1	1	1	Covered	T34,T35,T36

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T1,T15
1	1	0	Covered	T106,T115,T123
1	1	1	Covered	T6,T1,T19

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T82,T34
1	1	0	Covered	T38,T115,T117
1	1	1	Covered	T34,T35,T36

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T9,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T34,T35,T36

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T9,T82
1	1	0	Covered	T38,T105,T115
1	1	1	Covered	T34,T35,T36

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T1,T15
1	1	0	Covered	T38,T115,T117
1	1	1	Covered	T6,T1,T19

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T18,T82
1	1	0	Covered	T38,T106,T122
1	1	1	Covered	T34,T35,T36

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T80,T9,T82
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T34,T35,T36

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T15,T16,T18
1	1	0	Covered	T38,T106,T115
1	1	1	Covered	T34,T35,T36

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T6,T1,T15
1	1	0	Covered	T38,T105,T106
1	1	1	Covered	T1,T2,T9

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T6,T1
1	0	1	Covered	T3,T80,T82
1	1	0	Covered	T38,T106,T115
1	1	1	Covered	T3,T7,T12

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T6,T1