Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered111.07
Success101798.93
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0091191100
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001256237921298031500
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001256237361494300
tb.dut.tlul_assert_device.gen_device.contigMask_M 001256237921856507300
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00125623792115271500
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001256237361513500
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0012562379211047240800
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00125623792150269900
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0012562379211047240800
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00125623792150269900
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00125623792150269900
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00125623792150269900
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001256237361318700
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001256237361293900
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0091191100
tb.dut.u_reg.en2addrHit 00125623736123648500
tb.dut.u_reg.reAfterRv 00125623736123648400
tb.dut.u_reg.rePulse 00125623736112610700
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 00125623736194927400
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001256237361110000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361110000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343110000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343101300
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361110900
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 00125623736182506300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 00125623736198300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 00125623736198300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 00690234398300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 00690234389900
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 00125623736199400
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0091191100
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001256237361148759400
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001256237361169000
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361169000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343169000
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343160400
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361169800
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001256237361147733200
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001256237361165900
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361165900
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343165900
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343157500
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361166900
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001256237361140723700
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001256237361162300
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361162300
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343162300
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343153900
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361163300
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001256237361145023000
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001256237361166200
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361166200
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343166200
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343157600
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361167200
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001256237361143349600
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001256237361161400
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361161400
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343161400
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343152800
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361162500
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001256237361143736100
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001256237361164800
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361164800
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343164800
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343156300
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361165700
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001256237361142344700
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001256237361164700
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361164700
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343164700
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343156300
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361165700
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001256237361139584300
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001256237361163000
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361163000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343163000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343154800
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361164000
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 00125623736199596300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001256237361117500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361117500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343117500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343108900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361118500
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 00125623736198550500
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001256237361118000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361118000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343118000
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343109600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361118800
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 00125623736196682300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001256237361115700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361115700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343115700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343107100
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361116900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 00125623736193898100
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001256237361112900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361112900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343112900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343105000
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361113800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001256237361615779500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001256237361703000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361703000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343703000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343694200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361703800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001256237361600864400
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001256237361694800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361694800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343694800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343685900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361695800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001256237361602478300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001256237361695900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361695900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343695900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343687600
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361697000
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001256237361612695100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001256237361712700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361712700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343712700
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343704200
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361713700
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001256237361664986100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001256237361748100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361748100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343748100
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343739400
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361749100
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001256237361648749000
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001256237361740400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361740400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343740400
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343731300
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361741300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001256237361646964200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001256237361738200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361738200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343738200
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343729100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361739300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001256237361660873300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001256237361759100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361759100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343759100
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343750600
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001256237361760000
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001256237361143171200
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 006902343627211300
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001256237361169500
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001256237361125582232300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001256237361169500
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 006902343169500
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 006902343160800
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