Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	99.01	97.80	100.00	92.95	99.18	98.94	90.62

Total tests in report: 911

---

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
48.94	48.94	65.64	65.64	46.57	46.57	83.33	83.33	18.59	18.59	68.20	68.20	56.74	56.74	3.46	3.46	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1759397075
70.30	21.36	85.70	20.06	72.57	25.99	87.44	4.11	71.15	52.56	85.58	17.38	84.49	27.75	5.14	1.67	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.3723670059
75.43	5.13	90.16	4.45	82.60	10.04	90.98	3.54	71.15	0.00	90.25	4.67	86.32	1.83	16.55	11.41	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.510681935
77.94	2.51	92.42	2.26	84.17	1.57	91.89	0.91	77.56	6.41	93.14	2.89	88.63	2.31	17.74	1.19	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1153655388
80.13	2.19	94.89	2.47	88.80	4.63	93.95	2.05	78.21	0.64	95.85	2.71	91.33	2.70	17.86	0.12	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1626142786
82.25	2.13	96.46	1.57	91.88	3.08	95.09	1.14	78.21	0.00	97.33	1.48	92.00	0.67	24.79	6.93	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1265243088
84.36	2.11	96.91	0.45	92.77	0.88	95.32	0.23	78.21	0.00	97.33	0.00	93.74	1.73	36.26	11.47	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.2339745088
86.39	2.03	97.64	0.73	92.84	0.08	95.89	0.57	87.18	8.97	97.85	0.52	93.83	0.10	39.49	3.23	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.287429124
87.64	1.25	97.66	0.02	92.90	0.05	95.89	0.00	87.18	0.00	97.89	0.04	93.93	0.10	48.03	8.54	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.196978665
88.89	1.25	97.68	0.02	93.91	1.01	96.58	0.68	87.18	0.00	97.92	0.04	93.93	0.00	55.02	6.99	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1237541143
89.91	1.03	98.05	0.37	94.34	0.43	97.26	0.68	89.10	1.92	98.22	0.30	94.89	0.96	57.53	2.51	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1221238031
90.82	0.91	98.15	0.09	94.69	0.35	97.26	0.00	89.10	0.00	98.22	0.00	94.89	0.00	63.44	5.91	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1929027001
91.47	0.64	98.18	0.04	94.74	0.05	97.26	0.00	89.10	0.00	98.22	0.00	94.89	0.00	67.86	4.42	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.551227708
91.93	0.46	98.18	0.00	95.70	0.96	97.72	0.46	89.10	0.00	98.26	0.04	95.28	0.39	69.24	1.37	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.834617403
92.37	0.44	98.18	0.00	95.70	0.00	97.72	0.00	89.10	0.00	98.26	0.00	95.28	0.00	72.34	3.11	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1525440418
92.78	0.41	98.18	0.00	95.85	0.15	97.83	0.11	89.10	0.00	98.26	0.00	95.57	0.29	74.67	2.33	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1417562081
93.09	0.31	98.22	0.04	95.88	0.03	97.83	0.00	89.10	0.00	98.33	0.07	95.66	0.10	76.58	1.91	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2248632369
93.38	0.29	98.22	0.00	95.93	0.05	99.43	1.60	89.10	0.00	98.33	0.00	95.76	0.10	76.88	0.30	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2064126316
93.65	0.27	98.30	0.07	96.06	0.13	99.43	0.00	90.38	1.28	98.41	0.07	96.05	0.29	76.94	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.529278795
93.91	0.25	98.35	0.06	96.26	0.20	99.43	0.00	90.38	0.00	98.48	0.07	96.72	0.67	77.72	0.78	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1962447022
94.15	0.25	98.43	0.07	96.26	0.00	99.43	0.00	90.38	0.00	98.52	0.04	96.72	0.00	79.33	1.61	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1634458895
94.39	0.24	98.50	0.07	96.31	0.05	99.43	0.00	91.67	1.28	98.59	0.07	96.92	0.19	79.33	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.36579817
94.60	0.21	98.50	0.00	96.36	0.05	99.77	0.34	91.67	0.00	98.59	0.00	97.98	1.06	79.33	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1105088266
94.78	0.18	98.58	0.07	96.49	0.13	99.77	0.00	91.67	0.00	98.59	0.00	97.98	0.00	80.41	1.08	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2737646679
94.95	0.17	98.62	0.04	96.51	0.03	99.77	0.00	92.31	0.64	98.63	0.04	98.07	0.10	80.76	0.36	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1279856511
95.12	0.17	98.62	0.00	96.54	0.03	99.77	0.00	92.31	0.00	98.63	0.00	98.07	0.00	81.90	1.14	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1463014385
95.26	0.15	98.62	0.00	96.54	0.00	99.77	0.00	92.31	0.00	98.63	0.00	98.07	0.00	82.92	1.02	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.113541934
95.41	0.14	98.67	0.06	96.54	0.00	99.77	0.00	92.31	0.00	98.63	0.00	98.07	0.00	83.87	0.96	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2142115223
95.55	0.14	98.71	0.04	96.61	0.08	99.77	0.00	92.95	0.64	98.67	0.04	98.27	0.19	83.87	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.972961680
95.67	0.12	98.73	0.02	96.61	0.00	99.77	0.00	92.95	0.00	98.67	0.00	98.27	0.00	84.71	0.84	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.456528241
95.76	0.09	98.73	0.00	96.61	0.00	99.77	0.00	92.95	0.00	98.67	0.00	98.27	0.00	85.30	0.60	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.65718434
95.84	0.08	98.73	0.00	96.79	0.18	99.77	0.00	92.95	0.00	98.74	0.07	98.36	0.10	85.54	0.24	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1703074953
95.92	0.08	98.73	0.00	96.79	0.00	99.77	0.00	92.95	0.00	98.74	0.00	98.36	0.00	86.08	0.54	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.25952220
95.99	0.08	98.73	0.00	96.79	0.00	99.77	0.00	92.95	0.00	98.74	0.00	98.36	0.00	86.62	0.54	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2738822683
96.06	0.07	98.73	0.00	96.79	0.00	99.77	0.00	92.95	0.00	98.74	0.00	98.36	0.00	87.10	0.48	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3379047422
96.13	0.07	98.73	0.00	96.97	0.18	99.77	0.00	92.95	0.00	98.74	0.00	98.65	0.29	87.10	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3419288988
96.19	0.06	98.73	0.00	96.97	0.00	99.77	0.00	92.95	0.00	98.74	0.00	98.65	0.00	87.51	0.42	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4073783552
96.24	0.05	98.73	0.00	96.99	0.03	99.77	0.00	92.95	0.00	98.74	0.00	98.65	0.00	87.87	0.36	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3764674336
96.29	0.05	98.78	0.06	97.07	0.08	100.00	0.23	92.95	0.00	98.74	0.00	98.65	0.00	87.87	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3355678404
96.35	0.05	98.82	0.04	97.22	0.15	100.00	0.00	92.95	0.00	98.81	0.07	98.75	0.10	87.87	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.460159448
96.40	0.05	98.82	0.00	97.22	0.00	100.00	0.00	92.95	0.00	98.81	0.00	98.75	0.00	88.23	0.36	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3652082348
96.44	0.04	98.82	0.00	97.32	0.10	100.00	0.00	92.95	0.00	98.81	0.00	98.94	0.19	88.23	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.3916897143
96.48	0.04	98.84	0.02	97.35	0.03	100.00	0.00	92.95	0.00	98.85	0.04	98.94	0.00	88.41	0.18	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.819402797
96.51	0.04	98.84	0.00	97.60	0.25	100.00	0.00	92.95	0.00	98.85	0.00	98.94	0.00	88.41	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.190210559
96.55	0.03	98.84	0.00	97.60	0.00	100.00	0.00	92.95	0.00	98.85	0.00	98.94	0.00	88.65	0.24	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1537134379
96.58	0.03	98.84	0.00	97.60	0.00	100.00	0.00	92.95	0.00	98.85	0.00	98.94	0.00	88.89	0.24	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.2432627299
96.61	0.03	98.84	0.00	97.62	0.03	100.00	0.00	92.95	0.00	98.85	0.00	98.94	0.00	89.07	0.18	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1603131460
96.64	0.03	98.88	0.04	97.65	0.03	100.00	0.00	92.95	0.00	98.93	0.07	98.94	0.00	89.13	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2823576519
96.66	0.03	98.88	0.00	97.65	0.00	100.00	0.00	92.95	0.00	98.93	0.00	98.94	0.00	89.31	0.18	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1586545450
96.69	0.03	98.88	0.00	97.65	0.00	100.00	0.00	92.95	0.00	98.93	0.00	98.94	0.00	89.49	0.18	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.749368421
96.71	0.02	98.91	0.04	97.67	0.03	100.00	0.00	92.95	0.00	99.00	0.07	98.94	0.00	89.49	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2289032728
96.73	0.02	98.91	0.00	97.67	0.00	100.00	0.00	92.95	0.00	99.00	0.00	98.94	0.00	89.61	0.12	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1752574394
96.74	0.02	98.91	0.00	97.67	0.00	100.00	0.00	92.95	0.00	99.00	0.00	98.94	0.00	89.73	0.12	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2577709845
96.76	0.01	98.91	0.00	97.70	0.03	100.00	0.00	92.95	0.00	99.00	0.00	98.94	0.00	89.78	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.4159770202
96.77	0.01	98.93	0.02	97.72	0.03	100.00	0.00	92.95	0.00	99.04	0.04	98.94	0.00	89.78	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3213345560
96.78	0.01	98.95	0.02	97.75	0.03	100.00	0.00	92.95	0.00	99.07	0.04	98.94	0.00	89.78	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2854392076
96.79	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	89.84	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.592223900
96.80	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	89.90	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1131287513
96.80	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	89.96	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3561254688
96.81	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.02	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2117924347
96.82	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.08	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3266293389
96.83	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.14	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.3134694000
96.84	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.20	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.415286745
96.85	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.26	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2669602891
96.86	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.32	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1503465162
96.86	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.38	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3807152910
96.87	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.44	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1169394807
96.88	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.50	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2688409176
96.89	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.56	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.755504885
96.90	0.01	98.95	0.00	97.75	0.00	100.00	0.00	92.95	0.00	99.07	0.00	98.94	0.00	90.62	0.06	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2187101194
96.91	0.01	98.97	0.02	97.75	0.00	100.00	0.00	92.95	0.00	99.11	0.04	98.94	0.00	90.62	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1491653785
96.91	0.01	98.99	0.02	97.75	0.00	100.00	0.00	92.95	0.00	99.15	0.04	98.94	0.00	90.62	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3014568151
96.92	0.01	99.01	0.02	97.75	0.00	100.00	0.00	92.95	0.00	99.18	0.04	98.94	0.00	90.62	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.2422351172
96.93	0.01	99.01	0.00	97.77	0.03	100.00	0.00	92.95	0.00	99.18	0.00	98.94	0.00	90.62	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2885443836
96.93	0.01	99.01	0.00	97.80	0.03	100.00	0.00	92.95	0.00	99.18	0.00	98.94	0.00	90.62	0.00	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3634566697

---

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2642192792
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2423856330
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3837517774
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.201250275
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1592204002
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.65775479
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.511011364
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3576676172
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.121988771
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1658012008
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.900186242
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2665829443
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3973753529
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1263660575
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3198418220
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1569971316
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1314410430
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.922803410
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3436713564
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2464653902
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1810548235
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.499087226
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1502713401
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1712979226
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3993322644
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1519957062
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2126580931
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2940475791
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3891209039
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1428521396
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.497477085
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1994358844
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3332740171
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2379763803
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2680722276
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2364316140
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3316269221
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1732660552
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3101023971
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3168458801
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2654554579
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1172088279
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3297707817
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1522432903
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3273317394
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1534132200
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.211173986
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3744487833
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3665095571
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3255581826
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4059354668
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1883440468
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.916842670
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.554573143
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.497868563
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2685469020
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.773076688
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.952464355
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3524025084
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1039468302
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1468551171
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2994586659
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2201045331
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.4190431770
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2659291541
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.622777833
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2252081326
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2886334060
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1647331470
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2316917933
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2835126633
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3240265543
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2120218036
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3261399910
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.888446595
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3301409987
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3504128680
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3542871988
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.4280449835
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.747272671
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3478227486
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.4214106802
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1406025151
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.534543997
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1483996440
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4100429915
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1720983863
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3016771617
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.342119383
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.936230370
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1573045378
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2170031630
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3293033593
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.169629836
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2565010439
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1617485114
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2197588233
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3103462174
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3179111871
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2657923875
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3740187676
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2318189486
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.660367718
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.327873004
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1993062453
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1824699969
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1371363552
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.887255092
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2373909056
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.712419544
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1439025588
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.803729416
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2489799643
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.390079185
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1449509192
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3562345873
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4040423293
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2299083713

---

Total test records in report: 911

---

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2293244441			Sep 24 09:11:47 PM UTC 24	Sep 24 09:11:51 PM UTC 24	2231449840 ps
T5	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3248209132			Sep 24 09:13:14 PM UTC 24	Sep 24 09:13:31 PM UTC 24	2610842664 ps
T1	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1759397075			Sep 24 09:11:49 PM UTC 24	Sep 24 09:11:53 PM UTC 24	3067935504 ps
T13	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3149733652			Sep 24 09:11:47 PM UTC 24	Sep 24 09:11:53 PM UTC 24	2480717103 ps
T2	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1153655388			Sep 24 09:11:49 PM UTC 24	Sep 24 09:11:55 PM UTC 24	7102398141 ps
T14	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2516473217			Sep 24 09:11:47 PM UTC 24	Sep 24 09:11:55 PM UTC 24	2120882015 ps
T15	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1491653785			Sep 24 09:11:49 PM UTC 24	Sep 24 09:11:56 PM UTC 24	3196526541 ps
T3	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1626142786			Sep 24 09:11:47 PM UTC 24	Sep 24 09:11:57 PM UTC 24	2522881631 ps
T16	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.1756001431			Sep 24 09:11:54 PM UTC 24	Sep 24 09:11:58 PM UTC 24	2152768335 ps
T17	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.83102809			Sep 24 09:11:48 PM UTC 24	Sep 24 09:12:00 PM UTC 24	2176040156 ps
T18	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3355678404			Sep 24 09:11:53 PM UTC 24	Sep 24 09:12:01 PM UTC 24	2019415676 ps
T7	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3466236125			Sep 24 09:11:56 PM UTC 24	Sep 24 09:12:02 PM UTC 24	2450748614 ps
T8	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.888558679			Sep 24 09:11:57 PM UTC 24	Sep 24 09:12:02 PM UTC 24	2555702518 ps
T28	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3262608893			Sep 24 09:11:48 PM UTC 24	Sep 24 09:12:03 PM UTC 24	2510961911 ps
T29	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1406338314			Sep 24 09:11:49 PM UTC 24	Sep 24 09:12:04 PM UTC 24	2610379977 ps
T65	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.510681935			Sep 24 09:11:59 PM UTC 24	Sep 24 09:12:05 PM UTC 24	2517877273 ps
T73	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2315248045			Sep 24 09:11:49 PM UTC 24	Sep 24 09:12:06 PM UTC 24	2870344194 ps
T86	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.514906036			Sep 24 09:12:01 PM UTC 24	Sep 24 09:12:08 PM UTC 24	2629535075 ps
T6	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2718753551			Sep 24 09:12:03 PM UTC 24	Sep 24 09:12:09 PM UTC 24	3772214487 ps
T193	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.2507517261			Sep 24 09:11:58 PM UTC 24	Sep 24 09:12:11 PM UTC 24	2043367625 ps
T26	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1882317253			Sep 24 09:11:55 PM UTC 24	Sep 24 09:12:13 PM UTC 24	2478455555 ps
T74	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1753483379			Sep 24 09:12:02 PM UTC 24	Sep 24 09:12:13 PM UTC 24	3213640719 ps
T194	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3419033731			Sep 24 09:12:12 PM UTC 24	Sep 24 09:12:15 PM UTC 24	2041436813 ps
T30	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2436052022			Sep 24 09:12:02 PM UTC 24	Sep 24 09:12:15 PM UTC 24	3389516936 ps
T195	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.1137569372			Sep 24 09:12:14 PM UTC 24	Sep 24 09:12:17 PM UTC 24	2171844639 ps
T113	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3549081523			Sep 24 09:12:10 PM UTC 24	Sep 24 09:12:18 PM UTC 24	22522177824 ps
T24	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.639939690			Sep 24 09:12:03 PM UTC 24	Sep 24 09:12:20 PM UTC 24	10812597298 ps
T32	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1055044609			Sep 24 09:12:16 PM UTC 24	Sep 24 09:12:21 PM UTC 24	2282860413 ps
T87	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1105088266			Sep 24 09:12:07 PM UTC 24	Sep 24 09:12:22 PM UTC 24	8106148308 ps
T295	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.113541934			Sep 24 09:12:18 PM UTC 24	Sep 24 09:12:23 PM UTC 24	2166127253 ps
T88	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1789108291			Sep 24 09:12:21 PM UTC 24	Sep 24 09:12:26 PM UTC 24	2631086520 ps
T56	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1031324954			Sep 24 09:12:16 PM UTC 24	Sep 24 09:12:29 PM UTC 24	2198995438 ps
T75	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2835434208			Sep 24 09:12:23 PM UTC 24	Sep 24 09:12:30 PM UTC 24	3598709613 ps
T27	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2861673565			Sep 24 09:12:14 PM UTC 24	Sep 24 09:12:31 PM UTC 24	2467744158 ps
T89	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2312404444			Sep 24 09:12:20 PM UTC 24	Sep 24 09:12:33 PM UTC 24	2513875468 ps
T31	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4182278598			Sep 24 09:12:23 PM UTC 24	Sep 24 09:12:35 PM UTC 24	3668932180 ps
T9	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.347976596			Sep 24 09:12:29 PM UTC 24	Sep 24 09:12:37 PM UTC 24	3064400422 ps
T231	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.1843513789			Sep 24 09:12:34 PM UTC 24	Sep 24 09:12:37 PM UTC 24	2123527558 ps
T114	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3897004607			Sep 24 09:12:30 PM UTC 24	Sep 24 09:12:41 PM UTC 24	4120846876 ps
T79	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1498794236			Sep 24 09:12:36 PM UTC 24	Sep 24 09:12:41 PM UTC 24	2471008110 ps
T232	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.3873196039			Sep 24 09:12:33 PM UTC 24	Sep 24 09:12:42 PM UTC 24	2016752860 ps
T10	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1850092931			Sep 24 09:12:24 PM UTC 24	Sep 24 09:12:44 PM UTC 24	12016353238 ps
T57	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3335982004			Sep 24 09:12:38 PM UTC 24	Sep 24 09:12:46 PM UTC 24	2181931068 ps
T153	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2112840886			Sep 24 09:12:41 PM UTC 24	Sep 24 09:12:46 PM UTC 24	2216911022 ps
T58	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.550066445			Sep 24 09:12:38 PM UTC 24	Sep 24 09:12:47 PM UTC 24	2312639284 ps
T90	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1463014385			Sep 24 09:12:42 PM UTC 24	Sep 24 09:12:47 PM UTC 24	2537309889 ps
T76	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1008695347			Sep 24 09:12:47 PM UTC 24	Sep 24 09:12:50 PM UTC 24	4533288394 ps
T59	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.404729836			Sep 24 09:12:47 PM UTC 24	Sep 24 09:12:53 PM UTC 24	3060487290 ps
T11	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2289032728			Sep 24 09:12:48 PM UTC 24	Sep 24 09:12:53 PM UTC 24	2934590785 ps
T91	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2662828780			Sep 24 09:12:42 PM UTC 24	Sep 24 09:12:58 PM UTC 24	2607551105 ps
T80	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1265243088			Sep 24 09:12:50 PM UTC 24	Sep 24 09:12:59 PM UTC 24	7682944290 ps
T176	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.3723060885			Sep 24 09:12:45 PM UTC 24	Sep 24 09:13:01 PM UTC 24	3242963995 ps
T177	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.3001878088			Sep 24 09:12:59 PM UTC 24	Sep 24 09:13:03 PM UTC 24	2141507661 ps
T178	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3461801650			Sep 24 09:12:58 PM UTC 24	Sep 24 09:13:07 PM UTC 24	2013425265 ps
T60	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1729161312			Sep 24 09:13:04 PM UTC 24	Sep 24 09:13:08 PM UTC 24	2206638419 ps
T179	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.650572750			Sep 24 09:13:09 PM UTC 24	Sep 24 09:13:12 PM UTC 24	2240056179 ps
T12	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2353645956			Sep 24 09:13:08 PM UTC 24	Sep 24 09:13:13 PM UTC 24	2558959290 ps
T81	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2929363920			Sep 24 09:13:02 PM UTC 24	Sep 24 09:13:18 PM UTC 24	2454530455 ps
T273	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2064126316			Sep 24 09:11:52 PM UTC 24	Sep 24 09:13:20 PM UTC 24	42026950960 ps
T61	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1221238031			Sep 24 09:12:53 PM UTC 24	Sep 24 09:13:21 PM UTC 24	12258871782 ps
T77	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1943923804			Sep 24 09:13:21 PM UTC 24	Sep 24 09:13:24 PM UTC 24	5386637010 ps
T395	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.533600707			Sep 24 09:13:13 PM UTC 24	Sep 24 09:13:28 PM UTC 24	2511184205 ps
T389	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.4023061482			Sep 24 09:13:16 PM UTC 24	Sep 24 09:13:32 PM UTC 24	4739092573 ps
T50	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.2922712312			Sep 24 09:13:47 PM UTC 24	Sep 24 09:13:54 PM UTC 24	3443331361 ps
T19	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.1085064272			Sep 24 09:12:26 PM UTC 24	Sep 24 09:13:35 PM UTC 24	33639323429 ps
T66	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2516793451			Sep 24 09:12:32 PM UTC 24	Sep 24 09:13:35 PM UTC 24	22014501290 ps
T67	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2064336906			Sep 24 09:13:39 PM UTC 24	Sep 24 09:13:41 PM UTC 24	2047971572 ps
T68	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.907698670			Sep 24 09:13:36 PM UTC 24	Sep 24 09:13:41 PM UTC 24	2137387157 ps
T53	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3198815274			Sep 24 09:13:26 PM UTC 24	Sep 24 09:13:42 PM UTC 24	3193074330 ps
T82	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.421374348			Sep 24 09:13:36 PM UTC 24	Sep 24 09:13:43 PM UTC 24	2457199316 ps
T104	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.340257788			Sep 24 09:13:33 PM UTC 24	Sep 24 09:13:45 PM UTC 24	22258375530 ps
T105	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3421694927			Sep 24 09:13:36 PM UTC 24	Sep 24 09:13:47 PM UTC 24	2010047439 ps
T106	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1417562081			Sep 24 09:13:43 PM UTC 24	Sep 24 09:13:47 PM UTC 24	2550050467 ps
T62	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1279856511			Sep 24 09:13:44 PM UTC 24	Sep 24 09:13:51 PM UTC 24	3403367092 ps
T133	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1817443673			Sep 24 09:13:32 PM UTC 24	Sep 24 09:13:51 PM UTC 24	3016769799 ps
T134	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2806912702			Sep 24 09:13:43 PM UTC 24	Sep 24 09:13:52 PM UTC 24	2620023095 ps
T135	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3726099344			Sep 24 09:13:43 PM UTC 24	Sep 24 09:13:54 PM UTC 24	3731265742 ps
T33	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1603131460			Sep 24 09:12:05 PM UTC 24	Sep 24 09:13:55 PM UTC 24	121694599051 ps
T83	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.4244637358			Sep 24 09:13:55 PM UTC 24	Sep 24 09:13:59 PM UTC 24	2481993842 ps
T97	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.1680431128			Sep 24 09:13:56 PM UTC 24	Sep 24 09:14:00 PM UTC 24	2200669796 ps
T98	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3349045074			Sep 24 09:13:55 PM UTC 24	Sep 24 09:14:02 PM UTC 24	2119152216 ps
T99	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1997857731			Sep 24 09:13:53 PM UTC 24	Sep 24 09:14:05 PM UTC 24	2016894400 ps
T100	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3973867254			Sep 24 09:14:00 PM UTC 24	Sep 24 09:14:06 PM UTC 24	2524405600 ps
T101	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1680219863			Sep 24 09:13:52 PM UTC 24	Sep 24 09:14:07 PM UTC 24	5718689177 ps
T102	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3490380220			Sep 24 09:14:01 PM UTC 24	Sep 24 09:14:17 PM UTC 24	2612651328 ps
T52	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1727696676			Sep 24 09:14:08 PM UTC 24	Sep 24 09:14:20 PM UTC 24	4070428248 ps
T103	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3203204364			Sep 24 09:14:03 PM UTC 24	Sep 24 09:14:21 PM UTC 24	3376990143 ps
T25	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3343491665			Sep 24 09:14:06 PM UTC 24	Sep 24 09:14:22 PM UTC 24	5360378782 ps
T34	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.287429124			Sep 24 09:12:05 PM UTC 24	Sep 24 09:14:23 PM UTC 24	31675867307 ps
T63	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1402258270			Sep 24 09:14:03 PM UTC 24	Sep 24 09:14:25 PM UTC 24	3712649516 ps
T35	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.3723670059			Sep 24 09:11:51 PM UTC 24	Sep 24 09:14:26 PM UTC 24	42510142712 ps
T207	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2393899827			Sep 24 09:14:26 PM UTC 24	Sep 24 09:14:31 PM UTC 24	2155208099 ps
T208	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.199210532			Sep 24 09:14:24 PM UTC 24	Sep 24 09:14:32 PM UTC 24	2016521074 ps
T209	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1943598634			Sep 24 09:14:28 PM UTC 24	Sep 24 09:14:33 PM UTC 24	2629765619 ps
T210	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2344134635			Sep 24 09:14:24 PM UTC 24	Sep 24 09:14:36 PM UTC 24	2111522933 ps
T84	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.3987139024			Sep 24 09:14:24 PM UTC 24	Sep 24 09:14:40 PM UTC 24	2442585603 ps
T242	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.1165671808			Sep 24 09:14:28 PM UTC 24	Sep 24 09:14:43 PM UTC 24	2508338723 ps
T64	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3427935570			Sep 24 09:14:33 PM UTC 24	Sep 24 09:14:45 PM UTC 24	3383817844 ps
T51	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2854392076			Sep 24 09:14:39 PM UTC 24	Sep 24 09:14:46 PM UTC 24	3562889949 ps
T54	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.551227708			Sep 24 09:13:29 PM UTC 24	Sep 24 09:14:52 PM UTC 24	84276720821 ps
T78	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3036449621			Sep 24 09:14:24 PM UTC 24	Sep 24 09:14:52 PM UTC 24	15194278326 ps
T44	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2117924347			Sep 24 09:11:51 PM UTC 24	Sep 24 09:14:53 PM UTC 24	105850038438 ps
T296	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3076211466			Sep 24 09:14:24 PM UTC 24	Sep 24 09:14:56 PM UTC 24	5235726584 ps
T304	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.987948632			Sep 24 09:14:48 PM UTC 24	Sep 24 09:14:57 PM UTC 24	2107463037 ps
T305	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.3566474617			Sep 24 09:14:46 PM UTC 24	Sep 24 09:14:58 PM UTC 24	2012116149 ps
T306	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1078981840			Sep 24 09:14:53 PM UTC 24	Sep 24 09:14:58 PM UTC 24	2211534923 ps
T307	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.4116438780			Sep 24 09:14:54 PM UTC 24	Sep 24 09:14:59 PM UTC 24	2526093272 ps
T92	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3873655095			Sep 24 09:14:24 PM UTC 24	Sep 24 09:15:01 PM UTC 24	23844673351 ps
T308	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2046628790			Sep 24 09:14:57 PM UTC 24	Sep 24 09:15:02 PM UTC 24	2633218711 ps
T120	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3326673167			Sep 24 09:14:59 PM UTC 24	Sep 24 09:15:03 PM UTC 24	3686596429 ps
T400	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.685062404			Sep 24 09:14:58 PM UTC 24	Sep 24 09:15:03 PM UTC 24	2625478204 ps
T85	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.4193958478			Sep 24 09:14:53 PM UTC 24	Sep 24 09:15:06 PM UTC 24	2454055137 ps
T55	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3561254688			Sep 24 09:11:49 PM UTC 24	Sep 24 09:15:06 PM UTC 24	52638640228 ps
T136	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3184036650			Sep 24 09:14:44 PM UTC 24	Sep 24 09:15:07 PM UTC 24	3397393069 ps
T109	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.529278795			Sep 24 09:15:02 PM UTC 24	Sep 24 09:15:09 PM UTC 24	4515871853 ps
T137	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1115954934			Sep 24 09:15:08 PM UTC 24	Sep 24 09:15:12 PM UTC 24	2042531967 ps
T138	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2885356781			Sep 24 09:15:08 PM UTC 24	Sep 24 09:15:15 PM UTC 24	2117331546 ps
T93	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.751266314			Sep 24 09:15:02 PM UTC 24	Sep 24 09:15:15 PM UTC 24	29419490684 ps
T139	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.4019144028			Sep 24 09:15:09 PM UTC 24	Sep 24 09:15:17 PM UTC 24	2054093852 ps
T94	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.308402821			Sep 24 09:12:50 PM UTC 24	Sep 24 09:15:18 PM UTC 24	80634081886 ps
T70	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2823576519			Sep 24 09:14:59 PM UTC 24	Sep 24 09:15:19 PM UTC 24	478443403464 ps
T140	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1703074953			Sep 24 09:15:03 PM UTC 24	Sep 24 09:15:19 PM UTC 24	34644560431 ps
T180	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2668524977			Sep 24 09:15:16 PM UTC 24	Sep 24 09:15:21 PM UTC 24	2625314053 ps
T181	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.4239064951			Sep 24 09:15:08 PM UTC 24	Sep 24 09:15:22 PM UTC 24	2455303766 ps
T141	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2649685485			Sep 24 09:15:17 PM UTC 24	Sep 24 09:15:22 PM UTC 24	3366515000 ps
T224	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3524007311			Sep 24 09:15:18 PM UTC 24	Sep 24 09:15:24 PM UTC 24	4410240003 ps
T225	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.850658717			Sep 24 09:15:16 PM UTC 24	Sep 24 09:15:27 PM UTC 24	2829012080 ps
T121	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1082389389			Sep 24 09:12:09 PM UTC 24	Sep 24 09:15:27 PM UTC 24	43123286646 ps
T226	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.2432627299			Sep 24 09:15:13 PM UTC 24	Sep 24 09:15:29 PM UTC 24	2510236854 ps
T227	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.1201706693			Sep 24 09:15:30 PM UTC 24	Sep 24 09:15:34 PM UTC 24	2551195235 ps
T228	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.3960647931			Sep 24 09:15:24 PM UTC 24	Sep 24 09:15:34 PM UTC 24	2111988225 ps
T48	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.1397452948			Sep 24 09:15:20 PM UTC 24	Sep 24 09:15:36 PM UTC 24	4948786599 ps
T233	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1425192219			Sep 24 09:15:23 PM UTC 24	Sep 24 09:15:36 PM UTC 24	2014010949 ps
T234	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1720309071			Sep 24 09:15:35 PM UTC 24	Sep 24 09:15:40 PM UTC 24	2648491501 ps
T235	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4119808424			Sep 24 09:15:35 PM UTC 24	Sep 24 09:15:40 PM UTC 24	2895558319 ps
T236	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.286774377			Sep 24 09:15:27 PM UTC 24	Sep 24 09:15:41 PM UTC 24	2452714586 ps
T71	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.918823712			Sep 24 09:15:37 PM UTC 24	Sep 24 09:15:43 PM UTC 24	3866729601 ps
T237	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.3144902609			Sep 24 09:15:27 PM UTC 24	Sep 24 09:15:43 PM UTC 24	2209259895 ps
T173	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.255539157			Sep 24 09:15:41 PM UTC 24	Sep 24 09:15:44 PM UTC 24	3546804002 ps
T238	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2615706720			Sep 24 09:15:22 PM UTC 24	Sep 24 09:15:47 PM UTC 24	4496582448 ps
T45	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.1413805325			Sep 24 09:12:03 PM UTC 24	Sep 24 09:15:49 PM UTC 24	194780337849 ps
T142	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1440060899			Sep 24 09:15:23 PM UTC 24	Sep 24 09:15:52 PM UTC 24	7634703797 ps
T401	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2663436255			Sep 24 09:15:48 PM UTC 24	Sep 24 09:15:53 PM UTC 24	2132414100 ps
T402	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.2374856187			Sep 24 09:15:50 PM UTC 24	Sep 24 09:15:56 PM UTC 24	2469865708 ps
T143	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.4150396449			Sep 24 09:13:53 PM UTC 24	Sep 24 09:15:58 PM UTC 24	1361415166007 ps
T49	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2892714539			Sep 24 09:15:43 PM UTC 24	Sep 24 09:15:56 PM UTC 24	9066604588 ps
T403	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3707286777			Sep 24 09:15:45 PM UTC 24	Sep 24 09:15:58 PM UTC 24	2008635653 ps
T148	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.171691779			Sep 24 09:15:37 PM UTC 24	Sep 24 09:15:59 PM UTC 24	3572831937 ps
T297	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.3990810555			Sep 24 09:15:43 PM UTC 24	Sep 24 09:16:00 PM UTC 24	15314600311 ps
T404	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.84430282			Sep 24 09:15:57 PM UTC 24	Sep 24 09:16:00 PM UTC 24	2753480279 ps
T405	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3219432487			Sep 24 09:15:57 PM UTC 24	Sep 24 09:16:03 PM UTC 24	3454591851 ps
T406	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3610758827			Sep 24 09:15:53 PM UTC 24	Sep 24 09:16:03 PM UTC 24	2209832477 ps
T294	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.718523314			Sep 24 09:12:53 PM UTC 24	Sep 24 09:16:05 PM UTC 24	42011669563 ps
T95	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3570485941			Sep 24 09:15:21 PM UTC 24	Sep 24 09:16:05 PM UTC 24	24084049658 ps
T174	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.3391489577			Sep 24 09:16:01 PM UTC 24	Sep 24 09:16:09 PM UTC 24	2413868967 ps
T396	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3266293389			Sep 24 09:15:54 PM UTC 24	Sep 24 09:16:09 PM UTC 24	2507373649 ps
T407	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.2883386724			Sep 24 09:16:08 PM UTC 24	Sep 24 09:16:11 PM UTC 24	2099362916 ps
T408	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1172132554			Sep 24 09:16:07 PM UTC 24	Sep 24 09:16:11 PM UTC 24	2484652435 ps
T409	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.3283588200			Sep 24 09:16:06 PM UTC 24	Sep 24 09:16:13 PM UTC 24	2123052814 ps
T397	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.4000948952			Sep 24 09:16:10 PM UTC 24	Sep 24 09:16:15 PM UTC 24	2539007979 ps
T410	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.660185718			Sep 24 09:16:11 PM UTC 24	Sep 24 09:16:15 PM UTC 24	2633939785 ps
T319	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.238697807			Sep 24 09:15:59 PM UTC 24	Sep 24 09:16:16 PM UTC 24	4340397283 ps
T411	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.982766803			Sep 24 09:16:05 PM UTC 24	Sep 24 09:16:18 PM UTC 24	2015429753 ps
T320	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3910236122			Sep 24 09:16:04 PM UTC 24	Sep 24 09:16:18 PM UTC 24	3204645545 ps
T175	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3042352013			Sep 24 09:16:16 PM UTC 24	Sep 24 09:16:20 PM UTC 24	3360652776 ps
T116	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.383580243			Sep 24 09:16:12 PM UTC 24	Sep 24 09:16:24 PM UTC 24	3327757977 ps
T72	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2233491917			Sep 24 09:16:13 PM UTC 24	Sep 24 09:16:28 PM UTC 24	5289136903 ps
T412	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3835940701			Sep 24 09:16:26 PM UTC 24	Sep 24 09:16:30 PM UTC 24	2133974018 ps
T413	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.4233657504			Sep 24 09:16:12 PM UTC 24	Sep 24 09:16:31 PM UTC 24	3178121625 ps
T164	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1778589259			Sep 24 09:16:18 PM UTC 24	Sep 24 09:16:31 PM UTC 24	7843592452 ps
T41	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.2339745088			Sep 24 09:14:38 PM UTC 24	Sep 24 09:16:32 PM UTC 24	118110752560 ps
T414	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2474095543			Sep 24 09:16:21 PM UTC 24	Sep 24 09:16:32 PM UTC 24	2012730890 ps
T96	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1634458895			Sep 24 09:15:42 PM UTC 24	Sep 24 09:16:33 PM UTC 24	147774897600 ps
T415	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.441219216			Sep 24 09:16:32 PM UTC 24	Sep 24 09:16:37 PM UTC 24	2534208317 ps
T416	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2707810418			Sep 24 09:16:32 PM UTC 24	Sep 24 09:16:37 PM UTC 24	2622722619 ps
T261	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.345316121			Sep 24 09:14:07 PM UTC 24	Sep 24 09:16:37 PM UTC 24	89335492102 ps
T417	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.2586190115			Sep 24 09:16:31 PM UTC 24	Sep 24 09:16:39 PM UTC 24	2264159080 ps
T107	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2811032513			Sep 24 09:16:34 PM UTC 24	Sep 24 09:16:40 PM UTC 24	9350988511 ps
T418	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.3287095292			Sep 24 09:16:29 PM UTC 24	Sep 24 09:16:41 PM UTC 24	2475139506 ps
T419	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1245338631			Sep 24 09:16:18 PM UTC 24	Sep 24 09:16:45 PM UTC 24	4773763007 ps
T420	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1159573961			Sep 24 09:16:33 PM UTC 24	Sep 24 09:16:45 PM UTC 24	3292887581 ps
T421	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2991182234			Sep 24 09:16:33 PM UTC 24	Sep 24 09:16:46 PM UTC 24	3339271083 ps
T196	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3213345560			Sep 24 09:16:38 PM UTC 24	Sep 24 09:16:50 PM UTC 24	6273253494 ps
T422	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.3990167907			Sep 24 09:16:42 PM UTC 24	Sep 24 09:16:52 PM UTC 24	2010730638 ps
T298	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.871361109			Sep 24 09:16:40 PM UTC 24	Sep 24 09:16:53 PM UTC 24	4367390920 ps
T423	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4250496793			Sep 24 09:16:47 PM UTC 24	Sep 24 09:16:53 PM UTC 24	2247563630 ps
T398	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.25952220			Sep 24 09:16:50 PM UTC 24	Sep 24 09:16:54 PM UTC 24	2640540153 ps
T424	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.667959723			Sep 24 09:16:45 PM UTC 24	Sep 24 09:16:56 PM UTC 24	2110185343 ps
T249	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3169268581			Sep 24 09:13:46 PM UTC 24	Sep 24 09:16:58 PM UTC 24	95725775394 ps
T425	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2599166505			Sep 24 09:16:46 PM UTC 24	Sep 24 09:17:00 PM UTC 24	2481130579 ps
T426	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4037157976			Sep 24 09:16:54 PM UTC 24	Sep 24 09:17:01 PM UTC 24	3800254627 ps
T427	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1301963140			Sep 24 09:16:53 PM UTC 24	Sep 24 09:17:02 PM UTC 24	2622162529 ps
T108	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.1528132806			Sep 24 09:16:55 PM UTC 24	Sep 24 09:17:02 PM UTC 24	3459288323 ps
T428	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.1271445340			Sep 24 09:17:03 PM UTC 24	Sep 24 09:17:07 PM UTC 24	2033376075 ps
T243	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2034603021			Sep 24 09:13:48 PM UTC 24	Sep 24 09:17:07 PM UTC 24	54073346565 ps
T42	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2383860110			Sep 24 09:15:20 PM UTC 24	Sep 24 09:17:09 PM UTC 24	140204240773 ps
T43	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.35381273			Sep 24 09:16:38 PM UTC 24	Sep 24 09:17:12 PM UTC 24	53363135563 ps
T429	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.1783811990			Sep 24 09:17:07 PM UTC 24	Sep 24 09:17:14 PM UTC 24	2118563064 ps
T430	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1742245152			Sep 24 09:17:13 PM UTC 24	Sep 24 09:17:16 PM UTC 24	2788728241 ps
T431	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.848019412			Sep 24 09:17:08 PM UTC 24	Sep 24 09:17:17 PM UTC 24	2474063667 ps
T432	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2898925767			Sep 24 09:16:54 PM UTC 24	Sep 24 09:17:18 PM UTC 24	3701143729 ps
T433	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.672034210			Sep 24 09:17:10 PM UTC 24	Sep 24 09:17:20 PM UTC 24	2513055044 ps
T299	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3575683955			Sep 24 09:17:02 PM UTC 24	Sep 24 09:17:20 PM UTC 24	2991517939 ps
T434	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1779784206			Sep 24 09:17:08 PM UTC 24	Sep 24 09:17:21 PM UTC 24	2212393106 ps
T435	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1299741286			Sep 24 09:17:18 PM UTC 24	Sep 24 09:17:23 PM UTC 24	2912176114 ps
T436	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1666507364			Sep 24 09:17:17 PM UTC 24	Sep 24 09:17:25 PM UTC 24	3617046721 ps
T165	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.969078656			Sep 24 09:17:21 PM UTC 24	Sep 24 09:17:25 PM UTC 24	3935105249 ps
T122	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3648154138			Sep 24 09:16:01 PM UTC 24	Sep 24 09:17:26 PM UTC 24	101657486509 ps
T197	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3357407939			Sep 24 09:17:15 PM UTC 24	Sep 24 09:17:26 PM UTC 24	2854480004 ps
T198	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.871777969			Sep 24 09:14:41 PM UTC 24	Sep 24 09:17:26 PM UTC 24	34420490149 ps
T123	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2792864651			Sep 24 09:16:39 PM UTC 24	Sep 24 09:17:28 PM UTC 24	47879722384 ps
T199	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3121500820			Sep 24 09:17:24 PM UTC 24	Sep 24 09:17:30 PM UTC 24	2016468856 ps
T200	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3072437264			Sep 24 09:17:26 PM UTC 24	Sep 24 09:17:31 PM UTC 24	2536981951 ps
T201	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2944267002			Sep 24 09:17:28 PM UTC 24	Sep 24 09:17:32 PM UTC 24	2637221198 ps
T202	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2125735066			Sep 24 09:17:21 PM UTC 24	Sep 24 09:17:33 PM UTC 24	3521410866 ps
T203	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2251302816			Sep 24 09:17:26 PM UTC 24	Sep 24 09:17:33 PM UTC 24	2069084056 ps
T313	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.1244500395			Sep 24 09:17:26 PM UTC 24	Sep 24 09:17:35 PM UTC 24	2461707843 ps
T300	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.259224195			Sep 24 09:17:31 PM UTC 24	Sep 24 09:17:35 PM UTC 24	3661156940 ps
T437	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.2711080452			Sep 24 09:17:25 PM UTC 24	Sep 24 09:17:38 PM UTC 24	2110866193 ps
T257	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2737646679			Sep 24 09:16:01 PM UTC 24	Sep 24 09:17:38 PM UTC 24	96788848110 ps
T110	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3014568151			Sep 24 09:17:33 PM UTC 24	Sep 24 09:17:42 PM UTC 24	2783850547 ps
T438	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1864349059			Sep 24 09:17:29 PM UTC 24	Sep 24 09:17:42 PM UTC 24	2677181627 ps
T439	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.1765483064			Sep 24 09:17:40 PM UTC 24	Sep 24 09:17:45 PM UTC 24	2497504781 ps
T274	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2943472112			Sep 24 09:16:41 PM UTC 24	Sep 24 09:17:47 PM UTC 24	508262573288 ps
T440	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.475311420			Sep 24 09:17:39 PM UTC 24	Sep 24 09:17:47 PM UTC 24	2111318016 ps
T144	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1930476301			Sep 24 09:17:32 PM UTC 24	Sep 24 09:17:48 PM UTC 24	8089201887 ps
T317	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.401462462			Sep 24 09:17:43 PM UTC 24	Sep 24 09:17:48 PM UTC 24	2538494356 ps
T441	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3109176585			Sep 24 09:17:43 PM UTC 24	Sep 24 09:17:50 PM UTC 24	2131521630 ps
T442	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.1121670809			Sep 24 09:17:39 PM UTC 24	Sep 24 09:17:52 PM UTC 24	2010951409 ps
T443	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2738385565			Sep 24 09:17:48 PM UTC 24	Sep 24 09:17:52 PM UTC 24	10153586618 ps
T301	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1752574394			Sep 24 09:17:48 PM UTC 24	Sep 24 09:17:53 PM UTC 24	3418334955 ps
T46	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1702106646			Sep 24 09:15:41 PM UTC 24	Sep 24 09:17:53 PM UTC 24	161842703379 ps
T444	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3578166301			Sep 24 09:17:48 PM UTC 24	Sep 24 09:17:55 PM UTC 24	3409803299 ps
T334	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2882423935			Sep 24 09:17:35 PM UTC 24	Sep 24 09:17:59 PM UTC 24	9887863284 ps
T445	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3276837781			Sep 24 09:17:54 PM UTC 24	Sep 24 09:17:59 PM UTC 24	2043157237 ps
T272	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.771203426			Sep 24 09:13:22 PM UTC 24	Sep 24 09:18:02 PM UTC 24	82257623946 ps
T446	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1337939710			Sep 24 09:18:00 PM UTC 24	Sep 24 09:18:03 PM UTC 24	2544185686 ps
T47	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2227547673			Sep 24 09:17:01 PM UTC 24	Sep 24 09:18:03 PM UTC 24	114962690949 ps
T447	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2704660850			Sep 24 09:17:46 PM UTC 24	Sep 24 09:18:04 PM UTC 24	2611545233 ps
T182	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.497682669			Sep 24 09:17:50 PM UTC 24	Sep 24 09:18:06 PM UTC 24	4913631185 ps
T448	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1474923286			Sep 24 09:17:56 PM UTC 24	Sep 24 09:18:08 PM UTC 24	2113331398 ps
T399	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3444953584			Sep 24 09:18:03 PM UTC 24	Sep 24 09:18:08 PM UTC 24	2534922348 ps
T449	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.2717754977			Sep 24 09:18:00 PM UTC 24	Sep 24 09:18:09 PM UTC 24	2081641855 ps
T302	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.4019335786			Sep 24 09:18:05 PM UTC 24	Sep 24 09:18:09 PM UTC 24	3738299963 ps
T450	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.893877434			Sep 24 09:18:03 PM UTC 24	Sep 24 09:18:12 PM UTC 24	2620849618 ps
T190	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.819402797			Sep 24 09:17:54 PM UTC 24	Sep 24 09:18:13 PM UTC 24	15121116610 ps
T451	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.264260076			Sep 24 09:18:13 PM UTC 24	Sep 24 09:18:16 PM UTC 24	2146074032 ps
T186	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.282795026			Sep 24 09:18:09 PM UTC 24	Sep 24 09:18:16 PM UTC 24	4424258060 ps
T452	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.930126443			Sep 24 09:18:16 PM UTC 24	Sep 24 09:18:21 PM UTC 24	2134994951 ps
T453	/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.182547787			Sep 24 09:18:05 PM UTC 24	Sep 24 09:18:21 PM UTC 24	4902834481 ps