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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 67 1 T54 1 T44 1 T55 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 12 1 T248 1 T268 1 T335 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 51 1 T33 2 T44 1 T96 4
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 22 1 T41 2 T43 1 T46 3
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 47 1 T19 1 T94 1 T261 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 13 1 T121 1 T46 1 T125 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 42 1 T249 1 T257 2 T336 4
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 18 1 T42 1 T46 2 T125 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 38 1 T54 1 T55 1 T94 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 12 1 T41 1 T125 1 T127 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 37 1 T33 4 T44 1 T45 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 20 1 T41 1 T43 1 T122 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 39 1 T33 2 T54 1 T55 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 19 1 T33 2 T121 1 T41 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 36 1 T44 1 T122 3 T257 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 42 1 T33 10 T42 2 T122 6
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 55 1 T54 1 T94 1 T45 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 22 1 T121 1 T41 2 T42 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 49 1 T54 1 T55 2 T45 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 14 1 T131 1 T337 1 T268 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 42 1 T55 2 T94 1 T261 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 23 1 T121 1 T41 1 T42 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 67 1 T54 1 T44 1 T55 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 46 1 T42 2 T125 1 T127 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 42 1 T96 1 T249 1 T43 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 13 1 T121 1 T43 1 T127 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 54 1 T19 1 T55 2 T45 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 51 1 T41 2 T96 9 T42 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 35 1 T19 1 T55 2 T94 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 32 1 T43 1 T127 1 T128 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 45 1 T44 1 T121 1 T261 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 62 1 T44 1 T121 1 T41 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 54 1 T33 1 T54 1 T55 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T121 1 T41 1 T43 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 38 1 T45 2 T272 2 T267 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 14 1 T121 1 T43 3 T248 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 45 1 T19 4 T33 4 T44 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 22 1 T33 3 T41 1 T42 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 51 1 T54 3 T261 1 T249 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 26 1 T43 1 T46 1 T127 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 38 1 T19 1 T55 2 T94 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 31 1 T121 2 T42 1 T43 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 52 1 T19 1 T261 2 T249 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 17 1 T41 1 T42 1 T244 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 44 1 T19 4 T94 1 T45 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 24 1 T121 3 T41 1 T42 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 67 1 T19 2 T54 2 T55 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 60 1 T43 1 T198 9 T125 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 54 1 T19 3 T44 1 T96 5
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 25 1 T121 3 T96 4 T125 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 52 1 T45 1 T261 1 T272 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 17 1 T46 1 T248 1 T131 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 51 1 T261 1 T267 2 T336 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 21 1 T125 1 T127 1 T131 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 65 1 T54 3 T44 1 T55 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 83 1 T44 11 T42 1 T43 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 42 1 T19 1 T55 1 T45 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 26 1 T121 2 T41 2 T42 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 41 1 T45 1 T261 1 T272 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 55 1 T41 1 T42 1 T125 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 74 1 T94 6 T261 1 T249 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 60 1 T42 1 T46 1 T126 9
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 158 1 T19 1 T55 1 T45 6
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 67 1 T121 1 T41 4 T46 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 1 1 T341 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 19 1 T46 6 T248 1 T337 1


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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