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 LINE       6608
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T26,T24,T87
1	1	Covered	T26,T24,T87

 LINE       6608
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T65,T26,T24
1	1	Covered	T65,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T1,T26,T24
1	1	Covered	T73,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T8,T26
1	1	Covered	T65,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T26,T24,T87
1	1	Covered	T65,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T26,T24,T87
1	1	Covered	T3,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T65,T26,T24
1	1	Covered	T1,T65,T86

 LINE       6608
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T3,T18
1	1	Covered	T86,T193,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T3,T86,T26
1	1	Covered	T65,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T65,T26,T24
1	1	Covered	T86,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T65,T26,T24
1	1	Covered	T26,T24,T87

 LINE       6608
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T3,T7
1	1	Covered	T3,T18,T65

 LINE       6608
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T65,T26,T24
1	1	Covered	T65,T73,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T26,T24,T87
1	1	Covered	T65,T86,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T65,T26,T87
1	1	Covered	T65,T73,T86

 LINE       6608
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T3,T7
1	1	Covered	T65,T73,T86

 LINE       6608
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T26,T24,T87
1	1	Covered	T65,T26,T24

 LINE       6608
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T1,T65,T86
1	1	Covered	T65,T86,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T65,T26,T24
1	1	Covered	T1,T65,T26

 LINE       6608
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T3,T7,T8
1	1	Covered	T4,T3,T7

 LINE       6608
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T65,T6
1	1	Covered	T1,T65,T73

 LINE       6655
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T4,T5,T1

 LINE       6658
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T3,T65,T86
1	1	0	Covered	T286,T287,T288
1	1	1	Covered	T61,T274,T190

 LINE       6661
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T18,T65
1	1	0	Covered	T277,T286,T289
1	1	1	Covered	T18,T194,T232

 LINE       6664
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T86,T26
1	1	0	Covered	T286,T278,T290
1	1	1	Covered	T36,T37,T38

 LINE       6667
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T3,T7
1	1	0	Covered	T277,T286,T287
1	1	1	Covered	T4,T3,T7

 LINE       6669
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T18,T65
1	1	0	Covered	T281,T275,T276
1	1	1	Covered	T2,T24,T10

 LINE       6671
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T2,T65
1	1	0	Covered	T275,T277,T291
1	1	1	Covered	T2,T24,T10

 LINE       6673
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T65,T86
1	1	0	Covered	T275,T276,T277
1	1	1	Covered	T2,T24,T10

 LINE       6675
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T3,T18
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T2,T10,T25

 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T65,T86
1	1	0	Covered	T275,T277,T287
1	1	1	Covered	T2,T10,T25

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T2,T65,T86
1	1	0	Covered	T275,T292,T287
1	1	1	Covered	T2,T10,T19

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T13,T65,T86
1	1	0	Covered	T275,T286,T287
1	1	1	Covered	T13,T26,T27

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T5,T1,T13
1	1	0	Covered	T287,T289,T293
1	1	1	Covered	T5,T13,T28

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T5,T13
1	1	0	Covered	T277,T286,T287
1	1	1	Covered	T4,T5,T13

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T5,T3,T18
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T5,T28,T29

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T65,T73
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T1,T6,T9

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T1,T3
1	1	0	Covered	T275,T292,T290
1	1	1	Covered	T4,T1,T3

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T15,T65,T86
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T15,T30,T31

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T15,T65,T26
1	1	0	Covered	T277,T286,T287
1	1	1	Covered	T15,T30,T31

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T3,T8
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T3,T8,T32

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T26,T24,T87
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T33,T34,T35

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T26,T24
1	1	0	Covered	T277,T292,T289
1	1	1	Covered	T33,T34,T35

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T73,T26
1	1	0	Covered	T275,T290,T287
1	1	1	Covered	T33,T34,T35

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T3,T8,T65
1	1	0	Covered	T275,T286,T290
1	1	1	Covered	T3,T8,T32

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T26,T24
1	1	0	Covered	T275,T277,T292
1	1	1	Covered	T33,T34,T35

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T3,T26,T24
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T33,T34,T35

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T65,T86
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T33,T34,T35

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T3,T18
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T4,T3,T7

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T3,T65,T86
1	1	0	Covered	T275,T277,T290
1	1	1	Covered	T19,T33,T34

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T86,T26
1	1	0	Covered	T277,T286,T290
1	1	1	Covered	T19,T33,T34

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T26,T24
1	1	0	Covered	T275,T276,T286
1	1	1	Covered	T19,T33,T34

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T3,T18
1	1	0	Covered	T275,T277,T292
1	1	1	Covered	T4,T3,T7

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T73,T26
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T19,T33,T34

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T86,T26
1	1	0	Covered	T275,T277,T292
1	1	1	Covered	T19,T33,T34

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T73,T86
1	1	0	Covered	T286,T290,T287
1	1	1	Covered	T19,T33,T34

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T3,T7
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T4,T3,T7

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T65,T26,T24
1	1	0	Covered	T275,T277,T286
1	1	1	Covered	T19,T33,T34

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T65,T86
1	1	0	Covered	T275,T276,T277
1	1	1	Covered	T19,T33,T34

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T65,T26
1	1	0	Covered	T276,T277,T288
1	1	1	Covered	T19,T33,T34

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T4,T3,T7
1	1	0	Covered	T275,T277,T287
1	1	1	Covered	T3,T7,T8

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T1
1	0	1	Covered	T1,T65,T73
1	1	0	Covered	T275,T286,T287
1	1	1	Covered	T1,T6,T9

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T5,T1