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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 26 70 72.92 26
Automatically Generated Cross Bins 96 26 70 72.92 26
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] [auto[0]] * [auto[0]] [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[0]] [auto[1]] -- -- 2
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 52 1 T32 2 T58 3 T52 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 11 1 T388 1 T112 1 T303 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 44 1 T89 1 T285 1 T137 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 23 1 T41 1 T89 1 T109 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 67 1 T37 1 T38 1 T302 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 14 1 T53 1 T41 1 T388 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 72 1 T302 2 T89 1 T39 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 24 1 T53 1 T41 2 T109 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 47 1 T32 1 T37 1 T38 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 19 1 T293 2 T389 1 T288 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 39 1 T302 1 T89 2 T292 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 18 1 T53 1 T41 1 T293 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 44 1 T52 1 T38 1 T89 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 22 1 T388 1 T389 2 T393 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 45 1 T52 2 T37 1 T302 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 29 1 T41 1 T89 11 T109 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 52 1 T52 1 T37 1 T306 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 10 1 T393 1 T288 1 T117 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 39 1 T32 1 T52 1 T37 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 18 1 T293 2 T393 1 T287 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 51 1 T53 1 T42 1 T39 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 15 1 T37 2 T53 2 T41 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 52 1 T37 3 T39 1 T285 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 25 1 T53 2 T41 1 T109 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 35 1 T302 2 T292 1 T283 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 23 1 T53 1 T109 1 T112 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 37 1 T32 1 T285 1 T292 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 29 1 T32 8 T53 1 T41 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 60 1 T52 3 T40 1 T285 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 34 1 T388 3 T112 2 T389 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 40 1 T52 2 T40 7 T282 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 52 1 T37 8 T53 2 T388 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 49 1 T302 1 T39 1 T285 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 18 1 T293 3 T112 1 T303 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 62 1 T52 1 T38 1 T42 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 20 1 T293 1 T389 1 T393 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 50 1 T58 1 T285 1 T292 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 26 1 T58 7 T53 1 T109 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 36 1 T52 1 T285 1 T306 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 36 1 T53 2 T39 1 T388 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 41 1 T38 1 T302 1 T285 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 16 1 T41 1 T109 1 T293 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 38 1 T52 1 T38 1 T285 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 35 1 T109 1 T388 1 T112 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 40 1 T52 1 T38 2 T306 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 29 1 T293 1 T388 2 T288 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 77 1 T302 4 T39 1 T293 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 78 1 T109 1 T39 3 T112 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 66 1 T52 2 T42 1 T302 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 14 1 T53 1 T41 2 T39 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 26 1 T52 1 T42 1 T285 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 29 1 T41 1 T109 1 T293 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 53 1 T42 3 T302 1 T39 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 33 1 T41 1 T39 6 T388 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 66 1 T52 1 T42 1 T39 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 74 1 T53 1 T42 14 T109 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 64 1 T52 1 T41 1 T88 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 23 1 T41 1 T109 1 T293 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 48 1 T38 8 T302 2 T292 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 38 1 T53 3 T88 9 T388 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 30 1 T292 1 T111 1 T286 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 45 1 T41 1 T293 1 T389 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 124 1 T302 1 T285 12 T292 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 73 1 T53 1 T109 1 T293 5
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 2 1 T281 2 - - - -
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 1 1 T404 1 - - - -
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 1 1 T404 1 - - - -
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 2 1 T405 2 - - - -
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 2 1 T42 2 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 14 1 T293 1 T388 1 T112 2


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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