Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.20 97.95 100.00 94.87 99.44 99.23 93.51


Total tests in report: 916
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
47.01 47.01 63.66 63.66 49.18 49.18 85.84 85.84 0.00 0.00 68.05 68.05 49.61 49.61 12.73 12.73 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2235332885
76.72 29.71 90.92 27.26 83.77 34.59 92.58 6.74 73.08 73.08 92.88 24.83 87.28 37.67 16.54 3.81 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.521451891
79.23 2.51 92.65 1.72 87.41 3.64 94.41 1.83 73.08 0.00 94.66 1.78 87.96 0.67 24.47 7.93 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3643725462
81.70 2.46 94.99 2.34 89.30 1.90 94.86 0.46 82.69 9.62 96.18 1.52 89.31 1.35 24.53 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1653439141
83.92 2.23 97.25 2.26 91.15 1.85 95.43 0.57 88.46 5.77 97.78 1.59 91.91 2.60 25.47 0.94 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3587505667
85.95 2.03 97.62 0.37 92.34 1.19 95.89 0.46 88.46 0.00 98.07 0.30 92.20 0.29 37.08 11.61 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2236042778
87.23 1.28 97.64 0.02 93.30 0.96 96.58 0.68 88.46 0.00 98.11 0.04 92.20 0.00 44.32 7.24 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3815238873
88.42 1.19 97.94 0.30 93.60 0.30 97.03 0.46 88.46 0.00 98.26 0.15 92.29 0.10 51.37 7.05 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.992834592
89.36 0.94 98.02 0.07 93.91 0.30 97.03 0.00 88.46 0.00 98.26 0.00 93.93 1.64 55.93 4.56 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2208558393
90.28 0.92 98.02 0.00 94.18 0.28 97.03 0.00 88.46 0.00 98.26 0.00 94.32 0.39 61.67 5.74 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3979154294
90.81 0.54 98.13 0.11 94.26 0.08 97.03 0.00 88.46 0.00 98.26 0.00 94.32 0.00 65.23 3.56 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2317774268
91.28 0.47 98.22 0.09 94.69 0.43 97.49 0.46 88.46 0.00 98.37 0.11 94.80 0.48 66.92 1.69 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.279794597
91.74 0.46 98.28 0.06 94.77 0.08 97.49 0.00 88.46 0.00 98.37 0.00 94.80 0.00 70.04 3.12 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.4103415437
92.20 0.46 98.28 0.00 94.92 0.15 97.95 0.46 88.46 0.00 98.37 0.00 96.34 1.54 71.10 1.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.761680393
92.57 0.37 98.28 0.00 95.04 0.13 97.95 0.00 88.46 0.00 98.37 0.00 96.34 0.00 73.53 2.43 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.912419812
92.89 0.33 98.28 0.00 95.09 0.05 99.77 1.83 88.46 0.00 98.37 0.00 96.44 0.10 73.85 0.31 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3138599919
93.21 0.32 98.32 0.04 95.09 0.00 99.77 0.00 88.46 0.00 98.37 0.00 96.44 0.00 76.03 2.18 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2721528050
93.51 0.30 98.35 0.04 95.35 0.25 99.77 0.00 88.46 0.00 98.41 0.04 96.53 0.10 77.72 1.69 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3543414390
93.80 0.29 98.45 0.09 95.50 0.15 99.77 0.00 89.74 1.28 98.52 0.11 96.92 0.39 77.72 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1379797243
94.05 0.24 98.47 0.02 95.75 0.25 99.77 0.00 89.74 0.00 98.59 0.07 97.59 0.67 78.40 0.69 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2092535754
94.25 0.21 98.47 0.00 95.75 0.00 99.77 0.00 89.74 0.00 98.59 0.00 97.59 0.00 79.84 1.44 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1705812536
94.45 0.20 98.50 0.04 96.49 0.73 99.77 0.00 89.74 0.00 98.59 0.00 97.69 0.10 80.40 0.56 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1388164499
94.65 0.20 98.50 0.00 96.49 0.00 99.77 0.00 89.74 0.00 98.59 0.00 97.69 0.00 81.77 1.37 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2700745859
94.83 0.18 98.52 0.02 96.49 0.00 99.77 0.00 89.74 0.00 98.63 0.04 97.69 0.00 82.96 1.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2329711961
95.00 0.17 98.52 0.00 96.49 0.00 99.77 0.00 89.74 0.00 98.63 0.00 97.69 0.00 84.14 1.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2707763736
95.16 0.16 98.58 0.06 96.94 0.46 99.77 0.00 89.74 0.00 98.74 0.11 98.17 0.48 84.14 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3427423627
95.31 0.15 98.63 0.06 96.97 0.03 99.77 0.00 90.38 0.64 98.81 0.07 98.27 0.10 84.33 0.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1628225318
95.46 0.15 98.63 0.00 96.97 0.00 99.77 0.00 90.38 0.00 98.81 0.00 98.27 0.00 85.39 1.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.2460124499
95.60 0.14 98.69 0.06 97.02 0.05 99.77 0.00 91.03 0.64 98.89 0.07 98.36 0.10 85.46 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2260621142
95.74 0.14 98.76 0.07 97.04 0.03 99.77 0.00 91.67 0.64 99.00 0.11 98.46 0.10 85.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.408067919
95.86 0.13 98.82 0.06 97.07 0.03 99.77 0.00 92.31 0.64 99.07 0.07 98.55 0.10 85.46 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1447014003
95.99 0.13 98.84 0.02 97.07 0.00 99.77 0.00 92.31 0.00 99.07 0.00 98.55 0.00 86.33 0.87 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2836780092
96.12 0.12 98.84 0.00 97.07 0.00 99.77 0.00 92.31 0.00 99.07 0.00 98.55 0.00 87.20 0.87 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3660594522
96.24 0.12 98.88 0.04 97.09 0.03 99.77 0.00 92.95 0.64 99.11 0.04 98.65 0.10 87.20 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1186389087
96.36 0.12 98.91 0.04 97.12 0.03 99.77 0.00 93.59 0.64 99.15 0.04 98.75 0.10 87.20 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.3228247871
96.48 0.12 98.95 0.04 97.14 0.03 99.77 0.00 94.23 0.64 99.18 0.04 98.84 0.10 87.20 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1846801184
96.60 0.12 98.99 0.04 97.17 0.03 99.77 0.00 94.87 0.64 99.22 0.04 98.94 0.10 87.20 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3274360199
96.68 0.08 98.99 0.00 97.17 0.00 99.77 0.00 94.87 0.00 99.22 0.00 98.94 0.00 87.77 0.56 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.2890430897
96.76 0.08 98.99 0.00 97.17 0.00 99.77 0.00 94.87 0.00 99.22 0.00 98.94 0.00 88.33 0.56 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.456578341
96.82 0.06 99.05 0.06 97.24 0.08 100.00 0.23 94.87 0.00 99.22 0.00 98.94 0.00 88.39 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.1910039635
96.87 0.05 99.05 0.00 97.62 0.38 100.00 0.00 94.87 0.00 99.22 0.00 98.94 0.00 88.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1331570035
96.92 0.05 99.05 0.00 97.62 0.00 100.00 0.00 94.87 0.00 99.22 0.00 98.94 0.00 88.76 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3531196276
96.98 0.05 99.05 0.00 97.62 0.00 100.00 0.00 94.87 0.00 99.22 0.00 98.94 0.00 89.14 0.37 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2126316754
97.03 0.05 99.08 0.04 97.72 0.10 100.00 0.00 94.87 0.00 99.30 0.07 99.04 0.10 89.20 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.4192538748
97.07 0.04 99.08 0.00 97.72 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.04 0.00 89.51 0.31 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3838208342
97.12 0.04 99.08 0.00 97.72 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.04 0.00 89.83 0.31 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1404453938
97.16 0.04 99.08 0.00 97.72 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.04 0.00 90.14 0.31 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2758978247
97.21 0.04 99.08 0.00 97.75 0.03 100.00 0.00 94.87 0.00 99.30 0.00 99.13 0.10 90.32 0.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.3708709474
97.25 0.04 99.08 0.00 97.77 0.03 100.00 0.00 94.87 0.00 99.30 0.00 99.13 0.00 90.57 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.72758160
97.28 0.04 99.08 0.00 97.77 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.13 0.00 90.82 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.770715820
97.32 0.04 99.08 0.00 97.77 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.13 0.00 91.07 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3670046999
97.35 0.03 99.08 0.00 97.77 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.10 91.20 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1530255963
97.38 0.03 99.08 0.00 97.80 0.03 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 91.39 0.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.22068738
97.41 0.03 99.08 0.00 97.80 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 91.57 0.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1977265680
97.43 0.03 99.08 0.00 97.80 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 91.76 0.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1209818852
97.46 0.03 99.08 0.00 97.80 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 91.95 0.19 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3298849442
97.48 0.02 99.12 0.04 97.85 0.05 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.01 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3759395222
97.50 0.02 99.12 0.00 97.85 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.13 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.890531777
97.52 0.02 99.12 0.00 97.85 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.26 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2878438025
97.54 0.02 99.12 0.00 97.85 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.38 0.12 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3926504050
97.55 0.02 99.12 0.00 97.90 0.05 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.45 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2845957773
97.56 0.01 99.12 0.00 97.93 0.03 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.51 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1761383380
97.57 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.57 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3772358932
97.58 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.63 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.994845908
97.59 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.70 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.880692336
97.60 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.76 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3648031505
97.61 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.82 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.72026944
97.62 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.88 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2374668334
97.63 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 92.95 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2282541968
97.64 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.01 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1450542174
97.65 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.07 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2808712270
97.65 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.13 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1498786359
97.66 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.20 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.333616649
97.67 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.26 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2087723499
97.68 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.32 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.15973675
97.69 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.38 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2488226232
97.70 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.45 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3498159811
97.71 0.01 99.12 0.00 97.93 0.00 100.00 0.00 94.87 0.00 99.30 0.00 99.23 0.00 93.51 0.06 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1893505530
97.72 0.01 99.14 0.02 97.93 0.00 100.00 0.00 94.87 0.00 99.33 0.04 99.23 0.00 93.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3524164568
97.72 0.01 99.16 0.02 97.93 0.00 100.00 0.00 94.87 0.00 99.37 0.04 99.23 0.00 93.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.2552330588
97.73 0.01 99.18 0.02 97.93 0.00 100.00 0.00 94.87 0.00 99.41 0.04 99.23 0.00 93.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2369119421
97.74 0.01 99.20 0.02 97.93 0.00 100.00 0.00 94.87 0.00 99.44 0.04 99.23 0.00 93.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1274673375
97.74 0.01 99.20 0.00 97.95 0.03 100.00 0.00 94.87 0.00 99.44 0.00 99.23 0.00 93.51 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.344460742

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3670784556
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2902336069
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3889251074
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2293103625
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3859800520
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2863606045
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3025575847
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1789854165
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3603360058
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2126832550
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2940301831
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2907354130
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1986418718
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1676777934
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.856030186
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2235212623
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.634806440
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2174558059
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.167875952
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2021887999
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1862975883
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.174086028
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.955394385
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3975099729
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.783161998
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.652610041
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.294997397
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1093240587
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.4130435316
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4066101727
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2422137273
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3508582091
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.640224275
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1343472597
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3831715590
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3420383231
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.4210981903
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1162162747
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2690304455
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3146494987
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1523498045
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.964348311
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2064520264
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.365148326
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2668469674
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2698799922
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.390137416
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3928307989
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2913531074
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2920824950
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2266828380
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.997610229
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.541542257
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2531842855
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3469774724
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.726727896
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3098484286
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3959954226
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4075522377
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.275805486
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.132753684
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1243549280
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2144146714
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3058188489
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3541952833
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.881564504
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.611342992
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1293789743
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3005060326
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.307331387
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2592374403
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1462670462
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3625202897
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4191978750
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3568747068
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2520356651
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3719138770
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3359452092
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3963682686
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.85222925
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2999829619
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2925528876
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1039912219
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2561067293
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2146356054
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.409524021
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.858693448
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3324174627
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.436655522
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2386153882
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3782750863
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3306304374
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3275469900
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1853068002
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.408261388
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1798730819
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3383513070
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.656872212
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3561045483
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1460603559
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1224673378
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.4277817509
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.231382962
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3802561843
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1124337309
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1730387111
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3300783129
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.568289582
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2117481375
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2369900216
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/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2508428993
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2778129470
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1184194773
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.4164130186
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1300862349
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Total test records in report: 916
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3759395222 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:17 AM UTC 24 2418960813 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.3394400190 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:18 AM UTC 24 2099995046 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.96597688 Oct 09 07:14:15 AM UTC 24 Oct 09 07:14:19 AM UTC 24 3406475413 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1403400521 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:19 AM UTC 24 2636714405 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.1436529635 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:20 AM UTC 24 2112165739 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.675094116 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:21 AM UTC 24 2260865976 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2235332885 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:22 AM UTC 24 2511487522 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3838208342 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:22 AM UTC 24 3585039954 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3643725462 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:23 AM UTC 24 2456277844 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3946812051 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:23 AM UTC 24 8930644095 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.880692336 Oct 09 07:14:14 AM UTC 24 Oct 09 07:14:24 AM UTC 24 3549510433 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3587505667 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:27 AM UTC 24 6637255968 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2457528914 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:27 AM UTC 24 2018609751 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1581618675 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:27 AM UTC 24 3626439497 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2313917902 Oct 09 07:14:25 AM UTC 24 Oct 09 07:14:28 AM UTC 24 3949766521 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3512414279 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:28 AM UTC 24 2361780338 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3193392291 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:28 AM UTC 24 2483413453 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.789128691 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:28 AM UTC 24 2114897899 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3723488932 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:29 AM UTC 24 2403384999 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3489301991 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:29 AM UTC 24 2617460760 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.2460124499 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:32 AM UTC 24 2143803913 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.72026944 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:34 AM UTC 24 2508175555 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3586880492 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:34 AM UTC 24 7238583771 ps
T170 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.271373148 Oct 09 07:14:27 AM UTC 24 Oct 09 07:14:34 AM UTC 24 2021158938 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.4033912979 Oct 09 07:14:30 AM UTC 24 Oct 09 07:14:34 AM UTC 24 2636875191 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2632393798 Oct 09 07:14:29 AM UTC 24 Oct 09 07:14:34 AM UTC 24 2370948458 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.1424033817 Oct 09 07:14:29 AM UTC 24 Oct 09 07:14:35 AM UTC 24 2121743097 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3648031505 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:36 AM UTC 24 3962862612 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2959665686 Oct 09 07:14:29 AM UTC 24 Oct 09 07:14:37 AM UTC 24 2398479030 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3949622135 Oct 09 07:14:29 AM UTC 24 Oct 09 07:14:38 AM UTC 24 2461825112 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.486617372 Oct 09 07:14:30 AM UTC 24 Oct 09 07:14:38 AM UTC 24 2516861485 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.2166871480 Oct 09 07:14:29 AM UTC 24 Oct 09 07:14:40 AM UTC 24 2046093154 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1653439141 Oct 09 07:14:25 AM UTC 24 Oct 09 07:14:40 AM UTC 24 34191877849 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.393431670 Oct 09 07:14:35 AM UTC 24 Oct 09 07:14:40 AM UTC 24 2616778045 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3864334543 Oct 09 07:14:23 AM UTC 24 Oct 09 07:14:40 AM UTC 24 4488781415 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.584439247 Oct 09 07:14:32 AM UTC 24 Oct 09 07:14:41 AM UTC 24 2702148677 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1549942621 Oct 09 07:14:25 AM UTC 24 Oct 09 07:14:41 AM UTC 24 5805782461 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3593309917 Oct 09 07:14:32 AM UTC 24 Oct 09 07:14:42 AM UTC 24 3756905062 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.22068738 Oct 09 07:14:41 AM UTC 24 Oct 09 07:14:43 AM UTC 24 2800196323 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1342312999 Oct 09 07:14:40 AM UTC 24 Oct 09 07:14:44 AM UTC 24 2460348418 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3774411398 Oct 09 07:14:41 AM UTC 24 Oct 09 07:14:45 AM UTC 24 2175288701 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1718230985 Oct 09 07:14:40 AM UTC 24 Oct 09 07:14:46 AM UTC 24 2355154288 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.1262482437 Oct 09 07:14:38 AM UTC 24 Oct 09 07:14:46 AM UTC 24 2108093243 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3710718529 Oct 09 07:14:38 AM UTC 24 Oct 09 07:14:48 AM UTC 24 2472535763 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2776399537 Oct 09 07:14:34 AM UTC 24 Oct 09 07:14:48 AM UTC 24 4321251687 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.1910039635 Oct 09 07:14:38 AM UTC 24 Oct 09 07:14:49 AM UTC 24 2010718646 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4089789188 Oct 09 07:14:42 AM UTC 24 Oct 09 07:14:50 AM UTC 24 3808520281 ps
T347 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.3955034445 Oct 09 07:14:47 AM UTC 24 Oct 09 07:14:50 AM UTC 24 2138029055 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3543414390 Oct 09 07:14:41 AM UTC 24 Oct 09 07:14:51 AM UTC 24 3217304123 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.761680393 Oct 09 07:14:36 AM UTC 24 Oct 09 07:14:52 AM UTC 24 4232723939 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.521451891 Oct 09 07:14:22 AM UTC 24 Oct 09 07:14:52 AM UTC 24 41071298018 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2883000587 Oct 09 07:14:49 AM UTC 24 Oct 09 07:14:52 AM UTC 24 2486882936 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3962365089 Oct 09 07:14:46 AM UTC 24 Oct 09 07:14:52 AM UTC 24 7557377947 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2177748564 Oct 09 07:14:43 AM UTC 24 Oct 09 07:14:53 AM UTC 24 3227180209 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4011813289 Oct 09 07:14:49 AM UTC 24 Oct 09 07:14:53 AM UTC 24 2544471144 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3224448505 Oct 09 07:14:47 AM UTC 24 Oct 09 07:14:54 AM UTC 24 2018906367 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.4195141887 Oct 09 07:14:41 AM UTC 24 Oct 09 07:14:54 AM UTC 24 2610464406 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.639033367 Oct 09 07:14:49 AM UTC 24 Oct 09 07:14:57 AM UTC 24 2162200247 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.912419812 Oct 09 07:14:51 AM UTC 24 Oct 09 07:14:57 AM UTC 24 2518578993 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.580907275 Oct 09 07:14:51 AM UTC 24 Oct 09 07:14:57 AM UTC 24 2187251146 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2175810451 Oct 09 07:14:54 AM UTC 24 Oct 09 07:14:58 AM UTC 24 4438674920 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3546440226 Oct 09 07:14:54 AM UTC 24 Oct 09 07:14:58 AM UTC 24 3285953930 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1846801184 Oct 09 07:14:54 AM UTC 24 Oct 09 07:15:00 AM UTC 24 2591095912 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3498821197 Oct 09 07:14:25 AM UTC 24 Oct 09 07:15:01 AM UTC 24 39508661808 ps
T195 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3722952514 Oct 09 07:14:52 AM UTC 24 Oct 09 07:15:01 AM UTC 24 4335212247 ps
T196 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.625197816 Oct 09 07:14:41 AM UTC 24 Oct 09 07:15:02 AM UTC 24 5194654415 ps
T197 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.704183602 Oct 09 07:14:52 AM UTC 24 Oct 09 07:15:03 AM UTC 24 2609428763 ps
T198 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3078358009 Oct 09 07:14:57 AM UTC 24 Oct 09 07:15:03 AM UTC 24 2016982519 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.3873080085 Oct 09 07:14:46 AM UTC 24 Oct 09 07:15:05 AM UTC 24 10883620232 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3352818630 Oct 09 07:14:58 AM UTC 24 Oct 09 07:15:05 AM UTC 24 2111758880 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1623896213 Oct 09 07:15:00 AM UTC 24 Oct 09 07:15:06 AM UTC 24 2533986692 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.2580777944 Oct 09 07:15:06 AM UTC 24 Oct 09 07:15:12 AM UTC 24 2114585418 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.393772420 Oct 09 07:15:01 AM UTC 24 Oct 09 07:15:06 AM UTC 24 2636869913 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2853253755 Oct 09 07:14:36 AM UTC 24 Oct 09 07:15:07 AM UTC 24 45222789964 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2256394989 Oct 09 07:14:59 AM UTC 24 Oct 09 07:15:07 AM UTC 24 2080988939 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1792452959 Oct 09 07:15:02 AM UTC 24 Oct 09 07:15:11 AM UTC 24 2885555084 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.1703141279 Oct 09 07:14:59 AM UTC 24 Oct 09 07:15:11 AM UTC 24 2469702067 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1782482899 Oct 09 07:15:04 AM UTC 24 Oct 09 07:15:11 AM UTC 24 4917665922 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3660594522 Oct 09 07:15:08 AM UTC 24 Oct 09 07:15:12 AM UTC 24 2531896357 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.288242198 Oct 09 07:15:07 AM UTC 24 Oct 09 07:15:14 AM UTC 24 2023362049 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.382648350 Oct 09 07:15:03 AM UTC 24 Oct 09 07:15:14 AM UTC 24 5680713256 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.435244604 Oct 09 07:15:02 AM UTC 24 Oct 09 07:15:15 AM UTC 24 3345001449 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.4067096 Oct 09 07:15:13 AM UTC 24 Oct 09 07:15:16 AM UTC 24 3282599929 ps
T273 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1343450593 Oct 09 07:15:06 AM UTC 24 Oct 09 07:15:17 AM UTC 24 2012526259 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1044877586 Oct 09 07:15:09 AM UTC 24 Oct 09 07:15:17 AM UTC 24 2611503727 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.2996919387 Oct 09 07:15:04 AM UTC 24 Oct 09 07:15:18 AM UTC 24 3207758403 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3138599919 Oct 09 07:14:23 AM UTC 24 Oct 09 07:15:19 AM UTC 24 22030208081 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2130438065 Oct 09 07:15:12 AM UTC 24 Oct 09 07:15:19 AM UTC 24 3516508871 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.527436741 Oct 09 07:15:15 AM UTC 24 Oct 09 07:15:20 AM UTC 24 2036073467 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2925432317 Oct 09 07:15:16 AM UTC 24 Oct 09 07:15:21 AM UTC 24 2132132677 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.3659157438 Oct 09 07:15:06 AM UTC 24 Oct 09 07:15:22 AM UTC 24 2467954284 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.1250949335 Oct 09 07:15:19 AM UTC 24 Oct 09 07:15:24 AM UTC 24 2512732311 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1985702832 Oct 09 07:15:21 AM UTC 24 Oct 09 07:15:24 AM UTC 24 3620443599 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1177107760 Oct 09 07:15:21 AM UTC 24 Oct 09 07:15:25 AM UTC 24 3081287926 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2731838498 Oct 09 07:15:12 AM UTC 24 Oct 09 07:15:25 AM UTC 24 3638302790 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.992834592 Oct 09 07:14:34 AM UTC 24 Oct 09 07:15:26 AM UTC 24 71249058230 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.149358761 Oct 09 07:15:22 AM UTC 24 Oct 09 07:15:27 AM UTC 24 5674233626 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.645909561 Oct 09 07:15:24 AM UTC 24 Oct 09 07:15:28 AM UTC 24 4359163815 ps
T232 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3252939991 Oct 09 07:15:19 AM UTC 24 Oct 09 07:15:29 AM UTC 24 2259191916 ps
T233 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.688628266 Oct 09 07:14:55 AM UTC 24 Oct 09 07:15:29 AM UTC 24 6621389645 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2469977824 Oct 09 07:15:15 AM UTC 24 Oct 09 07:15:29 AM UTC 24 8858221665 ps
T234 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1849550810 Oct 09 07:14:57 AM UTC 24 Oct 09 07:15:30 AM UTC 24 22023045670 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1377385758 Oct 09 07:15:15 AM UTC 24 Oct 09 07:15:30 AM UTC 24 10051403342 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.769709068 Oct 09 07:15:17 AM UTC 24 Oct 09 07:15:30 AM UTC 24 2447033612 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2882445092 Oct 09 07:15:28 AM UTC 24 Oct 09 07:15:31 AM UTC 24 2528838914 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1966359490 Oct 09 07:15:29 AM UTC 24 Oct 09 07:15:33 AM UTC 24 2048211543 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.842393137 Oct 09 07:15:30 AM UTC 24 Oct 09 07:15:33 AM UTC 24 3863312746 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1502610610 Oct 09 07:15:28 AM UTC 24 Oct 09 07:15:34 AM UTC 24 2025039215 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.504306350 Oct 09 07:15:28 AM UTC 24 Oct 09 07:15:34 AM UTC 24 2116136205 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.842742132 Oct 09 07:15:20 AM UTC 24 Oct 09 07:15:34 AM UTC 24 2611285048 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1084678132 Oct 09 07:15:31 AM UTC 24 Oct 09 07:15:35 AM UTC 24 6861209447 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2013311287 Oct 09 07:15:26 AM UTC 24 Oct 09 07:15:35 AM UTC 24 9532106654 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2797433050 Oct 09 07:15:30 AM UTC 24 Oct 09 07:15:35 AM UTC 24 2626207969 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.2190214860 Oct 09 07:14:36 AM UTC 24 Oct 09 07:15:35 AM UTC 24 11407923548 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1036184461 Oct 09 07:15:25 AM UTC 24 Oct 09 07:15:38 AM UTC 24 10766769269 ps
T343 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.1648134852 Oct 09 07:15:05 AM UTC 24 Oct 09 07:15:38 AM UTC 24 10222926022 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.3212512706 Oct 09 07:15:30 AM UTC 24 Oct 09 07:15:39 AM UTC 24 2521540407 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1536810975 Oct 09 07:15:36 AM UTC 24 Oct 09 07:15:39 AM UTC 24 2197136661 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2064930410 Oct 09 07:15:31 AM UTC 24 Oct 09 07:15:40 AM UTC 24 3046131254 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3875627507 Oct 09 07:15:36 AM UTC 24 Oct 09 07:15:40 AM UTC 24 2024338273 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2236042778 Oct 09 07:14:44 AM UTC 24 Oct 09 07:15:40 AM UTC 24 72875787157 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2744723290 Oct 09 07:15:36 AM UTC 24 Oct 09 07:15:41 AM UTC 24 2478075365 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.3249992500 Oct 09 07:15:36 AM UTC 24 Oct 09 07:15:42 AM UTC 24 2521413957 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.847143766 Oct 09 07:15:12 AM UTC 24 Oct 09 07:15:43 AM UTC 24 323929761679 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1373759878 Oct 09 07:15:37 AM UTC 24 Oct 09 07:15:43 AM UTC 24 2620339728 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.571730781 Oct 09 07:14:36 AM UTC 24 Oct 09 07:15:43 AM UTC 24 42014721814 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1502136832 Oct 09 07:15:39 AM UTC 24 Oct 09 07:15:43 AM UTC 24 3813788185 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2275671482 Oct 09 07:15:36 AM UTC 24 Oct 09 07:15:45 AM UTC 24 2114080743 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.3440547949 Oct 09 07:15:44 AM UTC 24 Oct 09 07:15:49 AM UTC 24 2477364740 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1116832148 Oct 09 07:15:33 AM UTC 24 Oct 09 07:15:49 AM UTC 24 15109568547 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1231304884 Oct 09 07:15:46 AM UTC 24 Oct 09 07:15:50 AM UTC 24 3324291244 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1437987723 Oct 09 07:15:44 AM UTC 24 Oct 09 07:15:51 AM UTC 24 2616463115 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2635100920 Oct 09 07:15:42 AM UTC 24 Oct 09 07:15:51 AM UTC 24 7737569732 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2725676474 Oct 09 07:14:14 AM UTC 24 Oct 09 07:15:51 AM UTC 24 41326307548 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.3414711367 Oct 09 07:15:44 AM UTC 24 Oct 09 07:15:51 AM UTC 24 2233288566 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.860313390 Oct 09 07:15:42 AM UTC 24 Oct 09 07:15:53 AM UTC 24 2008903303 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3150218636 Oct 09 07:15:44 AM UTC 24 Oct 09 07:15:53 AM UTC 24 2514018663 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3427423627 Oct 09 07:15:31 AM UTC 24 Oct 09 07:15:53 AM UTC 24 4921469427 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.889019190 Oct 09 07:15:39 AM UTC 24 Oct 09 07:15:54 AM UTC 24 6357199679 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3524164568 Oct 09 07:15:52 AM UTC 24 Oct 09 07:15:55 AM UTC 24 4448183490 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.879301497 Oct 09 07:15:43 AM UTC 24 Oct 09 07:15:56 AM UTC 24 2107589178 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3926799327 Oct 09 07:15:40 AM UTC 24 Oct 09 07:15:56 AM UTC 24 4528160630 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4063378057 Oct 09 07:15:40 AM UTC 24 Oct 09 07:15:57 AM UTC 24 3265646616 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1573741706 Oct 09 07:15:54 AM UTC 24 Oct 09 07:15:57 AM UTC 24 2206766973 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.1045791393 Oct 09 07:15:54 AM UTC 24 Oct 09 07:15:58 AM UTC 24 2485604403 ps
T229 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3047184006 Oct 09 07:15:54 AM UTC 24 Oct 09 07:16:00 AM UTC 24 2023427660 ps
T230 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3697723647 Oct 09 07:15:56 AM UTC 24 Oct 09 07:16:01 AM UTC 24 2640516172 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.4193100312 Oct 09 07:15:39 AM UTC 24 Oct 09 07:16:04 AM UTC 24 4525223122 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1264730011 Oct 09 07:15:04 AM UTC 24 Oct 09 07:16:05 AM UTC 24 68932914591 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3677472780 Oct 09 07:15:56 AM UTC 24 Oct 09 07:16:05 AM UTC 24 2520233443 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1761383380 Oct 09 07:15:59 AM UTC 24 Oct 09 07:16:06 AM UTC 24 9672526386 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.423471606 Oct 09 07:15:54 AM UTC 24 Oct 09 07:16:06 AM UTC 24 2109300249 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2208558393 Oct 09 07:15:40 AM UTC 24 Oct 09 07:16:08 AM UTC 24 68754068541 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1385551785 Oct 09 07:15:59 AM UTC 24 Oct 09 07:16:08 AM UTC 24 4490290726 ps
T214 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.3302580875 Oct 09 07:15:53 AM UTC 24 Oct 09 07:16:08 AM UTC 24 9479509525 ps
T215 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.719132556 Oct 09 07:15:55 AM UTC 24 Oct 09 07:16:10 AM UTC 24 2508091912 ps
T216 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.1403513124 Oct 09 07:16:05 AM UTC 24 Oct 09 07:16:10 AM UTC 24 2127684345 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.915710192 Oct 09 07:16:05 AM UTC 24 Oct 09 07:16:10 AM UTC 24 2021018640 ps
T218 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.31491485 Oct 09 07:16:06 AM UTC 24 Oct 09 07:16:11 AM UTC 24 2277455504 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1932409825 Oct 09 07:16:09 AM UTC 24 Oct 09 07:16:13 AM UTC 24 3234572674 ps
T219 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.1088103115 Oct 09 07:16:07 AM UTC 24 Oct 09 07:16:15 AM UTC 24 2614010250 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.2552330588 Oct 09 07:16:11 AM UTC 24 Oct 09 07:16:16 AM UTC 24 3528104457 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1765922958 Oct 09 07:15:53 AM UTC 24 Oct 09 07:16:16 AM UTC 24 5487931593 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2103776060 Oct 09 07:16:06 AM UTC 24 Oct 09 07:16:17 AM UTC 24 2455805213 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1290068845 Oct 09 07:16:09 AM UTC 24 Oct 09 07:16:20 AM UTC 24 4115226208 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3274922458 Oct 09 07:16:07 AM UTC 24 Oct 09 07:16:20 AM UTC 24 2509471544 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1835362873 Oct 09 07:16:17 AM UTC 24 Oct 09 07:16:21 AM UTC 24 2476696616 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1754725304 Oct 09 07:14:25 AM UTC 24 Oct 09 07:16:22 AM UTC 24 42010238264 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1488016928 Oct 09 07:16:16 AM UTC 24 Oct 09 07:16:22 AM UTC 24 2021884785 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.892549131 Oct 09 07:16:18 AM UTC 24 Oct 09 07:16:23 AM UTC 24 2215609842 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2700745859 Oct 09 07:16:18 AM UTC 24 Oct 09 07:16:23 AM UTC 24 2537974352 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3143569099 Oct 09 07:16:17 AM UTC 24 Oct 09 07:16:24 AM UTC 24 2110771871 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2346972804 Oct 09 07:16:20 AM UTC 24 Oct 09 07:16:25 AM UTC 24 2633255252 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1617448092 Oct 09 07:16:20 AM UTC 24 Oct 09 07:16:26 AM UTC 24 3672114199 ps
T346 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1581035987 Oct 09 07:16:10 AM UTC 24 Oct 09 07:16:26 AM UTC 24 7744494116 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2863330684 Oct 09 07:16:21 AM UTC 24 Oct 09 07:16:27 AM UTC 24 3365987368 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3791397636 Oct 09 07:16:02 AM UTC 24 Oct 09 07:16:28 AM UTC 24 10135415058 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2730800346 Oct 09 07:16:21 AM UTC 24 Oct 09 07:16:29 AM UTC 24 4160562159 ps
T362 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3711746580 Oct 09 07:16:12 AM UTC 24 Oct 09 07:16:29 AM UTC 24 6388621695 ps
T363 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.2444165275 Oct 09 07:16:27 AM UTC 24 Oct 09 07:16:30 AM UTC 24 2112559571 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.4203837055 Oct 09 07:15:34 AM UTC 24 Oct 09 07:16:30 AM UTC 24 17721713245 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1728357874 Oct 09 07:16:25 AM UTC 24 Oct 09 07:16:32 AM UTC 24 2111510764 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.300992507 Oct 09 07:16:28 AM UTC 24 Oct 09 07:16:33 AM UTC 24 2519169561 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.3514792414 Oct 09 07:16:27 AM UTC 24 Oct 09 07:16:35 AM UTC 24 2488613524 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3622346202 Oct 09 07:16:30 AM UTC 24 Oct 09 07:16:35 AM UTC 24 3731910772 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.690971590 Oct 09 07:16:25 AM UTC 24 Oct 09 07:16:36 AM UTC 24 2011181716 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3786508447 Oct 09 07:16:30 AM UTC 24 Oct 09 07:16:37 AM UTC 24 3609820150 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.4200975138 Oct 09 07:16:23 AM UTC 24 Oct 09 07:16:37 AM UTC 24 2833574026 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1587163496 Oct 09 07:16:29 AM UTC 24 Oct 09 07:16:40 AM UTC 24 2612536782 ps
T169 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.2292404950 Oct 09 07:16:22 AM UTC 24 Oct 09 07:16:40 AM UTC 24 4112164909 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1839899861 Oct 09 07:16:33 AM UTC 24 Oct 09 07:16:41 AM UTC 24 2828422562 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2078175015 Oct 09 07:16:38 AM UTC 24 Oct 09 07:16:42 AM UTC 24 2039946597 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3544864146 Oct 09 07:15:40 AM UTC 24 Oct 09 07:16:42 AM UTC 24 40615950527 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2701541731 Oct 09 07:16:24 AM UTC 24 Oct 09 07:16:42 AM UTC 24 12186888878 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3746939895 Oct 09 07:16:31 AM UTC 24 Oct 09 07:16:45 AM UTC 24 4916601347 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3498159811 Oct 09 07:15:33 AM UTC 24 Oct 09 07:16:45 AM UTC 24 85446705458 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.979212581 Oct 09 07:16:38 AM UTC 24 Oct 09 07:16:46 AM UTC 24 2109060764 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1211349014 Oct 09 07:16:42 AM UTC 24 Oct 09 07:16:46 AM UTC 24 2647348088 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.4185083660 Oct 09 07:14:47 AM UTC 24 Oct 09 07:16:46 AM UTC 24 42010371445 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2369119421 Oct 09 07:16:13 AM UTC 24 Oct 09 07:16:47 AM UTC 24 13016727589 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3598778745 Oct 09 07:16:42 AM UTC 24 Oct 09 07:16:48 AM UTC 24 3664219642 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.540059182 Oct 09 07:16:43 AM UTC 24 Oct 09 07:16:49 AM UTC 24 3369718839 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.3271541158 Oct 09 07:16:41 AM UTC 24 Oct 09 07:16:50 AM UTC 24 2514149464 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.2631217034 Oct 09 07:16:39 AM UTC 24 Oct 09 07:16:50 AM UTC 24 2459931681 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3248561789 Oct 09 07:16:41 AM UTC 24 Oct 09 07:16:52 AM UTC 24 2211213988 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.723714306 Oct 09 07:16:49 AM UTC 24 Oct 09 07:16:53 AM UTC 24 2495386810 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3732195124 Oct 09 07:16:43 AM UTC 24 Oct 09 07:16:54 AM UTC 24 7667438371 ps
T185 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3351106028 Oct 09 07:16:35 AM UTC 24 Oct 09 07:16:56 AM UTC 24 3484135737 ps
T186 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.4156593550 Oct 09 07:16:48 AM UTC 24 Oct 09 07:16:57 AM UTC 24 2015715782 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3688635549 Oct 09 07:16:02 AM UTC 24 Oct 09 07:16:59 AM UTC 24 12248718157 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2424629975 Oct 09 07:16:50 AM UTC 24 Oct 09 07:16:59 AM UTC 24 2616142943 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.4005816532 Oct 09 07:16:48 AM UTC 24 Oct 09 07:17:00 AM UTC 24 2110784185 ps
T302 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.3842237828 Oct 09 07:15:50 AM UTC 24 Oct 09 07:17:00 AM UTC 24 88367636938 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3634583494 Oct 09 07:16:50 AM UTC 24 Oct 09 07:17:00 AM UTC 24 2510994341 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.2860449319 Oct 09 07:16:50 AM UTC 24 Oct 09 07:17:02 AM UTC 24 2223011673 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1532711593 Oct 09 07:16:53 AM UTC 24 Oct 09 07:17:03 AM UTC 24 4028853575 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1249109580 Oct 09 07:15:15 AM UTC 24 Oct 09 07:17:04 AM UTC 24 125089719594 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4262842072 Oct 09 07:15:13 AM UTC 24 Oct 09 07:17:05 AM UTC 24 130279321428 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1667364757 Oct 09 07:16:47 AM UTC 24 Oct 09 07:17:06 AM UTC 24 8338420874 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1190763632 Oct 09 07:17:03 AM UTC 24 Oct 09 07:17:06 AM UTC 24 2270030470 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.1097919762 Oct 09 07:17:01 AM UTC 24 Oct 09 07:17:07 AM UTC 24 2461387082 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3510892206 Oct 09 07:16:51 AM UTC 24 Oct 09 07:17:07 AM UTC 24 5159111247 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2317774268 Oct 09 07:16:01 AM UTC 24 Oct 09 07:17:08 AM UTC 24 101042192740 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1447014003 Oct 09 07:16:54 AM UTC 24 Oct 09 07:17:08 AM UTC 24 6912468009 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2595583251 Oct 09 07:17:00 AM UTC 24 Oct 09 07:17:10 AM UTC 24 2010316164 ps
T194 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.45949440 Oct 09 07:16:57 AM UTC 24 Oct 09 07:17:11 AM UTC 24 2626396461 ps
T356 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2922544177 Oct 09 07:17:07 AM UTC 24 Oct 09 07:17:12 AM UTC 24 6631370975 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.2110638506 Oct 09 07:17:04 AM UTC 24 Oct 09 07:17:13 AM UTC 24 2515396084 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2374668334 Oct 09 07:16:47 AM UTC 24 Oct 09 07:17:13 AM UTC 24 66325662557 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.58761742 Oct 09 07:16:47 AM UTC 24 Oct 09 07:17:14 AM UTC 24 8735050785 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1903574614 Oct 09 07:17:01 AM UTC 24 Oct 09 07:17:14 AM UTC 24 2113982437 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.87303544 Oct 09 07:16:59 AM UTC 24 Oct 09 07:17:15 AM UTC 24 5158347920 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1056858573 Oct 09 07:17:00 AM UTC 24 Oct 09 07:17:16 AM UTC 24 8716665920 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1744227688 Oct 09 07:17:14 AM UTC 24 Oct 09 07:17:18 AM UTC 24 2129673064 ps
T493 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.1006787467 Oct 09 07:17:12 AM UTC 24 Oct 09 07:17:19 AM UTC 24 2012686222 ps
T494 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2053296924 Oct 09 07:17:15 AM UTC 24 Oct 09 07:17:20 AM UTC 24 2621036420 ps
T495 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1250934723 Oct 09 07:17:05 AM UTC 24 Oct 09 07:17:20 AM UTC 24 2611379685 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3976432459 Oct 09 07:17:09 AM UTC 24 Oct 09 07:17:22 AM UTC 24 19241806039 ps
T496 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.938014969 Oct 09 07:17:06 AM UTC 24 Oct 09 07:17:22 AM UTC 24 3438876224 ps
T497 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.754337774 Oct 09 07:17:16 AM UTC 24 Oct 09 07:17:23 AM UTC 24 3738247592 ps
T203 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.551506265 Oct 09 07:17:08 AM UTC 24 Oct 09 07:17:23 AM UTC 24 5514147715 ps
T498 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2823244688 Oct 09 07:17:14 AM UTC 24 Oct 09 07:17:26 AM UTC 24 2449847269 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.33600405 Oct 09 07:15:57 AM UTC 24 Oct 09 07:17:26 AM UTC 24 315899336289 ps
T499 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1857273884 Oct 09 07:17:14 AM UTC 24 Oct 09 07:17:26 AM UTC 24 2255062193 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1189060011 Oct 09 07:17:19 AM UTC 24 Oct 09 07:17:26 AM UTC 24 6260095206 ps
T500 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.945454111 Oct 09 07:17:15 AM UTC 24 Oct 09 07:17:28 AM UTC 24 2512150425 ps
T501 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.2877815288 Oct 09 07:17:26 AM UTC 24 Oct 09 07:17:31 AM UTC 24 2208471307 ps
T502 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2695662335 Oct 09 07:17:24 AM UTC 24 Oct 09 07:17:32 AM UTC 24 2017944029 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2813945957 Oct 09 07:17:22 AM UTC 24 Oct 09 07:17:32 AM UTC 24 4980383083 ps
T285 /workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.345270838 Oct 09 07:15:59 AM UTC 24 Oct 09 07:17:34 AM UTC 24 134288886561 ps
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