Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1028010
Category 01028010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1028010
Severity 01028010

Summary for Assertions
NUMBERPERCENT
Total Number1028100.00
Uncovered40.39
Success102499.61
Failure00.00
Incomplete10.10
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered00.00
All Matches10100.00
First Matches10100.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 0092392300
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 001064255972234380400
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 001064255403597600
tb.dut.tlul_assert_device.gen_device.contigMask_M 0010642559721684331800
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 00106425597216727600
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 001064255403634800
tb.dut.tlul_assert_device.gen_device.legalAParam_M 0010642559721837359900
tb.dut.tlul_assert_device.gen_device.legalDParam_A 00106425597258134000
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 0010642559721837359900
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 00106425597258134000
tb.dut.tlul_assert_device.gen_device.respOpcode_A 00106425597258134000
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 00106425597258134000
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 001064255403396200
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 001064255403373200
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 0092392300
tb.dut.u_reg.en2addrHit 00106425540325885800
tb.dut.u_reg.reAfterRv 00106425540325885800
tb.dut.u_reg.rePulse 00106425540313756800
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.BusySrcReqChk_A 001064255403126721600
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcAckBusyChk_A 001064255403127400
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403127400
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718127400
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718121000
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403128500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.BusySrcReqChk_A 001064255403116075100
tb.dut.u_reg.u_auto_block_out_ctl_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcAckBusyChk_A 001064255403120700
tb.dut.u_reg.u_auto_block_out_ctl_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403120700
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718120700
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718114300
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403121700
tb.dut.u_reg.u_chk.PayLoadWidthCheck 0092392300
tb.dut.u_reg.u_com_det_ctl_0_cdc.BusySrcReqChk_A 001064255403186577300
tb.dut.u_reg.u_com_det_ctl_0_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcAckBusyChk_A 001064255403193700
tb.dut.u_reg.u_com_det_ctl_0_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403193700
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718193700
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718187500
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403194900
tb.dut.u_reg.u_com_det_ctl_1_cdc.BusySrcReqChk_A 001064255403179756200
tb.dut.u_reg.u_com_det_ctl_1_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcAckBusyChk_A 001064255403190300
tb.dut.u_reg.u_com_det_ctl_1_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403190300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718190300
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718184000
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403191300
tb.dut.u_reg.u_com_det_ctl_2_cdc.BusySrcReqChk_A 001064255403180502900
tb.dut.u_reg.u_com_det_ctl_2_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcAckBusyChk_A 001064255403190700
tb.dut.u_reg.u_com_det_ctl_2_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403190700
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718190700
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718184700
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403191700
tb.dut.u_reg.u_com_det_ctl_3_cdc.BusySrcReqChk_A 001064255403179384400
tb.dut.u_reg.u_com_det_ctl_3_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcAckBusyChk_A 001064255403189800
tb.dut.u_reg.u_com_det_ctl_3_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403189800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718189800
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718183400
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403191000
tb.dut.u_reg.u_com_out_ctl_0_cdc.BusySrcReqChk_A 001064255403189237000
tb.dut.u_reg.u_com_out_ctl_0_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcAckBusyChk_A 001064255403200500
tb.dut.u_reg.u_com_out_ctl_0_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403200500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718200500
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718194300
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403201500
tb.dut.u_reg.u_com_out_ctl_1_cdc.BusySrcReqChk_A 001064255403182400600
tb.dut.u_reg.u_com_out_ctl_1_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcAckBusyChk_A 001064255403190600
tb.dut.u_reg.u_com_out_ctl_1_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403190600
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718190600
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718184500
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403191800
tb.dut.u_reg.u_com_out_ctl_2_cdc.BusySrcReqChk_A 001064255403179372200
tb.dut.u_reg.u_com_out_ctl_2_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcAckBusyChk_A 001064255403190000
tb.dut.u_reg.u_com_out_ctl_2_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403190000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718190000
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718183700
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403191400
tb.dut.u_reg.u_com_out_ctl_3_cdc.BusySrcReqChk_A 001064255403181058200
tb.dut.u_reg.u_com_out_ctl_3_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcAckBusyChk_A 001064255403192000
tb.dut.u_reg.u_com_out_ctl_3_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403192000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718192000
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718185200
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403193000
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.BusySrcReqChk_A 001064255403125250600
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcAckBusyChk_A 001064255403132200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403132200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718132200
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718125500
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403133400
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.BusySrcReqChk_A 001064255403127666800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcAckBusyChk_A 001064255403133800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403133800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718133800
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718127600
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403134700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.BusySrcReqChk_A 001064255403125462700
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcAckBusyChk_A 001064255403132400
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403132400
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718132400
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718126000
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403133500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.BusySrcReqChk_A 001064255403122371500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcAckBusyChk_A 001064255403130000
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403130000
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718130000
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718123700
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403131000
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.BusySrcReqChk_A 001064255403686271800
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcAckBusyChk_A 001064255403744700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403744700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718744700
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718738200
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403745900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.BusySrcReqChk_A 001064255403693336100
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcAckBusyChk_A 001064255403756800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403756800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718756800
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718750700
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403757900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.BusySrcReqChk_A 001064255403660450000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcAckBusyChk_A 001064255403739800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403739800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718739800
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718733000
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403740800
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.BusySrcReqChk_A 001064255403651714600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcAckBusyChk_A 001064255403729600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403729600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718729600
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718723100
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403730900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.BusySrcReqChk_A 001064255403751051500
tb.dut.u_reg.u_com_sel_ctl_0_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcAckBusyChk_A 001064255403810900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403810900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718810900
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718804500
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403811900
tb.dut.u_reg.u_com_sel_ctl_1_cdc.BusySrcReqChk_A 001064255403754586200
tb.dut.u_reg.u_com_sel_ctl_1_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcAckBusyChk_A 001064255403818800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403818800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718818800
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718812100
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403819900
tb.dut.u_reg.u_com_sel_ctl_2_cdc.BusySrcReqChk_A 001064255403719958300
tb.dut.u_reg.u_com_sel_ctl_2_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcAckBusyChk_A 001064255403796400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403796400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718796400
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718790100
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403797500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.BusySrcReqChk_A 001064255403717252500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcAckBusyChk_A 001064255403795800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403795800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718795800
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718789200
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403796800
tb.dut.u_reg.u_ec_rst_ctl_cdc.BusySrcReqChk_A 001064255403185965100
tb.dut.u_reg.u_ec_rst_ctl_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcAckBusyChk_A 001064255403200300
tb.dut.u_reg.u_ec_rst_ctl_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403200300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718200300
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A 007081718194000
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M 001064255403201300
tb.dut.u_reg.u_key_intr_ctl_cdc.BusySrcReqChk_A 001064255403109316100
tb.dut.u_reg.u_key_intr_ctl_cdc.DstReqKnown_A 007081718641132500
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcAckBusyChk_A 001064255403110700
tb.dut.u_reg.u_key_intr_ctl_cdc.SrcBusyKnown_A 001064255403106380981900
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A 001064255403110700
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M 007081718110700
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