Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.35 99.35 98.00 100.00 97.44 99.59 99.61 80.48


Total tests in report: 923
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
47.00 47.00 63.49 63.49 48.87 48.87 85.96 85.96 0.00 0.00 67.72 67.72 49.71 49.71 13.26 13.26 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1478952179
69.55 22.55 82.95 19.46 72.39 23.51 87.33 1.37 65.38 65.38 84.54 16.83 79.09 29.38 15.15 1.89 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.480078308
79.52 9.97 89.61 6.66 82.28 9.89 91.32 4.00 78.21 12.82 90.66 6.12 91.23 12.14 33.30 18.14 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1219423197
82.46 2.95 94.89 5.28 87.51 5.23 92.58 1.26 78.85 0.64 94.89 4.23 94.99 3.76 33.52 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1136660738
84.41 1.95 95.23 0.34 87.74 0.23 94.86 2.28 79.49 0.64 94.96 0.07 94.99 0.00 43.63 10.10 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3841303271
86.30 1.88 97.17 1.95 92.36 4.63 95.55 0.68 80.77 1.28 97.78 2.82 95.95 0.96 44.49 0.86 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.151292222
87.76 1.47 97.87 0.69 92.41 0.05 95.55 0.00 89.74 8.97 98.33 0.56 95.95 0.00 44.49 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.3437963898
89.03 1.27 97.89 0.02 93.48 1.06 96.23 0.68 89.74 0.00 98.37 0.04 95.95 0.00 51.55 7.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.284793859
89.98 0.95 98.09 0.21 94.06 0.58 96.23 0.00 89.74 0.00 98.44 0.07 95.95 0.00 57.35 5.80 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3369215913
90.77 0.78 98.24 0.15 94.54 0.48 96.23 0.00 89.74 0.00 98.44 0.00 96.05 0.10 62.11 4.76 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.505197444
91.24 0.47 98.28 0.04 94.54 0.00 96.23 0.00 89.74 0.00 98.44 0.00 96.05 0.00 65.38 3.27 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3309041974
91.66 0.42 98.37 0.09 95.07 0.53 96.23 0.00 91.03 1.28 98.52 0.07 96.82 0.77 65.56 0.17 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.1324266284
92.01 0.36 98.37 0.00 95.12 0.05 98.29 2.05 91.03 0.00 98.52 0.00 96.92 0.10 65.84 0.29 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.4239844393
92.35 0.34 98.48 0.11 95.47 0.35 98.52 0.23 92.31 1.28 98.67 0.15 97.11 0.19 65.90 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3203650586
92.65 0.30 98.52 0.04 96.26 0.78 98.52 0.00 92.31 0.00 98.67 0.00 97.40 0.29 66.88 0.98 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.598236663
92.94 0.29 98.63 0.11 96.41 0.15 98.52 0.00 93.59 1.28 98.78 0.11 97.69 0.29 66.99 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.2421014867
93.21 0.27 98.67 0.04 96.46 0.05 98.52 0.00 93.59 0.00 98.78 0.00 97.69 0.00 68.77 1.78 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3250577744
93.43 0.22 98.67 0.00 96.49 0.03 99.77 1.26 93.59 0.00 98.78 0.00 97.69 0.00 69.00 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4047719599
93.63 0.21 98.71 0.04 96.59 0.10 99.77 0.00 93.59 0.00 98.78 0.00 97.78 0.10 70.21 1.21 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.4126262125
93.82 0.19 98.75 0.04 96.79 0.20 99.77 0.00 94.23 0.64 98.81 0.04 98.17 0.39 70.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.3989018581
93.98 0.16 98.82 0.07 96.89 0.10 99.77 0.00 94.87 0.64 98.93 0.11 98.36 0.19 70.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1421022692
94.14 0.16 98.82 0.00 96.99 0.10 99.77 0.00 94.87 0.00 98.93 0.00 99.04 0.67 70.55 0.34 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1489292039
94.28 0.14 98.88 0.06 97.04 0.05 99.77 0.00 95.51 0.64 99.00 0.07 99.13 0.10 70.61 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4282999933
94.41 0.13 98.88 0.00 97.04 0.00 99.77 0.00 95.51 0.00 99.00 0.00 99.13 0.00 71.53 0.92 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.993252289
94.54 0.13 98.88 0.00 97.04 0.00 99.77 0.00 95.51 0.00 99.00 0.00 99.13 0.00 72.45 0.92 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1660431651
94.67 0.13 98.93 0.06 97.07 0.03 99.77 0.00 96.15 0.64 99.07 0.07 99.23 0.10 72.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.223526155
94.80 0.13 98.99 0.06 97.09 0.03 99.77 0.00 96.79 0.64 99.15 0.07 99.33 0.10 72.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3226465152
94.91 0.12 99.03 0.04 97.12 0.03 99.77 0.00 97.44 0.64 99.18 0.04 99.42 0.10 72.45 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.3654854472
95.02 0.11 99.06 0.04 97.14 0.03 99.77 0.00 97.44 0.00 99.18 0.00 99.42 0.00 73.13 0.69 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.640764652
95.13 0.11 99.06 0.00 97.14 0.00 99.77 0.00 97.44 0.00 99.18 0.00 99.42 0.00 73.88 0.75 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.2670808582
95.21 0.08 99.08 0.02 97.14 0.00 99.77 0.00 97.44 0.00 99.18 0.00 99.42 0.00 74.45 0.57 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2991338033
95.30 0.08 99.08 0.00 97.14 0.00 99.77 0.00 97.44 0.00 99.18 0.00 99.42 0.00 75.03 0.57 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.564737094
95.37 0.08 99.14 0.06 97.40 0.25 99.77 0.00 97.44 0.00 99.33 0.15 99.52 0.10 75.03 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.805772538
95.45 0.08 99.14 0.00 97.45 0.05 99.77 0.00 97.44 0.00 99.37 0.04 99.52 0.00 75.49 0.46 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3217868044
95.53 0.07 99.14 0.00 97.45 0.00 99.77 0.00 97.44 0.00 99.37 0.00 99.52 0.00 76.00 0.52 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2429312857
95.60 0.07 99.14 0.00 97.45 0.00 99.77 0.00 97.44 0.00 99.37 0.00 99.52 0.00 76.52 0.52 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2296220934
95.67 0.07 99.14 0.00 97.45 0.00 99.77 0.00 97.44 0.00 99.37 0.00 99.52 0.00 76.98 0.46 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3461728674
95.72 0.06 99.14 0.00 97.45 0.00 99.77 0.00 97.44 0.00 99.37 0.00 99.52 0.00 77.38 0.40 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.314025286
95.77 0.05 99.20 0.06 97.52 0.08 100.00 0.23 97.44 0.00 99.37 0.00 99.52 0.00 77.38 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.43502276
95.82 0.05 99.20 0.00 97.52 0.00 100.00 0.00 97.44 0.00 99.37 0.00 99.52 0.00 77.73 0.34 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2817375871
95.87 0.04 99.20 0.00 97.83 0.30 100.00 0.00 97.44 0.00 99.37 0.00 99.52 0.00 77.73 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1904736375
95.91 0.04 99.21 0.02 97.83 0.00 100.00 0.00 97.44 0.00 99.41 0.04 99.52 0.00 77.96 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.4091014581
95.94 0.03 99.21 0.00 97.83 0.00 100.00 0.00 97.44 0.00 99.41 0.00 99.52 0.00 78.19 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.811795563
95.97 0.03 99.21 0.00 97.83 0.00 100.00 0.00 97.44 0.00 99.41 0.00 99.52 0.00 78.42 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3870862177
96.01 0.03 99.21 0.00 97.83 0.00 100.00 0.00 97.44 0.00 99.41 0.00 99.52 0.00 78.65 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.303957449
96.04 0.03 99.21 0.00 97.83 0.00 100.00 0.00 97.44 0.00 99.41 0.00 99.52 0.00 78.87 0.23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.3785407664
96.07 0.03 99.23 0.02 97.88 0.05 100.00 0.00 97.44 0.00 99.44 0.04 99.61 0.10 78.87 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2191403187
96.09 0.02 99.25 0.02 97.90 0.03 100.00 0.00 97.44 0.00 99.44 0.00 99.61 0.00 78.99 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1428478600
96.11 0.02 99.25 0.00 97.90 0.00 100.00 0.00 97.44 0.00 99.44 0.00 99.61 0.00 79.10 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.944999464
96.12 0.02 99.25 0.00 97.90 0.00 100.00 0.00 97.44 0.00 99.44 0.00 99.61 0.00 79.22 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3040188144
96.14 0.02 99.25 0.00 97.90 0.00 100.00 0.00 97.44 0.00 99.44 0.00 99.61 0.00 79.33 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3252874908
96.16 0.02 99.25 0.00 97.90 0.00 100.00 0.00 97.44 0.00 99.44 0.00 99.61 0.00 79.45 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2923190717
96.17 0.02 99.25 0.00 97.90 0.00 100.00 0.00 97.44 0.00 99.44 0.00 99.61 0.00 79.56 0.11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1277594334
96.19 0.02 99.29 0.04 97.90 0.00 100.00 0.00 97.44 0.00 99.52 0.07 99.61 0.00 79.56 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.481582323
96.20 0.02 99.29 0.00 97.95 0.05 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.62 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.572492074
96.22 0.01 99.29 0.00 97.98 0.03 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.68 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.169573361
96.22 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.74 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1627175904
96.23 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.79 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.439853096
96.24 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.85 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2523334666
96.25 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.91 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3747436722
96.26 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 79.97 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.3693053509
96.27 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.02 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1917070823
96.27 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.08 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1625476485
96.28 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.14 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3941330817
96.29 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.20 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.896678763
96.30 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.25 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2723855172
96.31 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.31 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4015809697
96.31 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.37 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1384680515
96.32 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.42 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.4087083863
96.33 0.01 99.29 0.00 97.98 0.00 100.00 0.00 97.44 0.00 99.52 0.00 99.61 0.00 80.48 0.06 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1157332983
96.34 0.01 99.31 0.02 97.98 0.00 100.00 0.00 97.44 0.00 99.56 0.04 99.61 0.00 80.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.268261492
96.35 0.01 99.33 0.02 97.98 0.00 100.00 0.00 97.44 0.00 99.59 0.04 99.61 0.00 80.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.2769241945
96.35 0.01 99.33 0.00 98.00 0.03 100.00 0.00 97.44 0.00 99.59 0.00 99.61 0.00 80.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.661158870
96.35 0.01 99.35 0.02 98.00 0.00 100.00 0.00 97.44 0.00 99.59 0.00 99.61 0.00 80.48 0.00 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3706073508

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3691160699
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2117272204
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Total test records in report: 923
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.1478952179 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:31 AM UTC 24 2525212601 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4208000125 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:34 AM UTC 24 2108047853 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1651890407 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:34 AM UTC 24 2298833762 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.993252289 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:34 AM UTC 24 2105038341 ps
T1 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1136660738 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:35 AM UTC 24 2432582282 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3979492393 Oct 12 12:56:27 AM UTC 24 Oct 12 12:56:35 AM UTC 24 2471443553 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.3137998270 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:37 AM UTC 24 2230837132 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3689207873 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:38 AM UTC 24 4458001601 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.496073939 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:38 AM UTC 24 2636619376 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.2473550373 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:39 AM UTC 24 2117553577 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3133642789 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:39 AM UTC 24 2237549220 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1936116936 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:39 AM UTC 24 3672773996 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2769523429 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:39 AM UTC 24 2622888570 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.371316167 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:40 AM UTC 24 2022078784 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3863814473 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:40 AM UTC 24 3506796788 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.327517206 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:41 AM UTC 24 5261303408 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.1194963877 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:41 AM UTC 24 2117573794 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.151292222 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:41 AM UTC 24 14421168373 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1732291265 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:41 AM UTC 24 2463709715 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.43502276 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:42 AM UTC 24 2013110013 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.572492074 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:43 AM UTC 24 14903641205 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1476280835 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:43 AM UTC 24 5291511180 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.37201351 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:43 AM UTC 24 2246650761 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.945816324 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:43 AM UTC 24 2512174679 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1400772691 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:43 AM UTC 24 3281144369 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.644936471 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:43 AM UTC 24 2474634970 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.33585159 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:44 AM UTC 24 2028052827 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.873355841 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:44 AM UTC 24 2317932597 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1547191073 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:44 AM UTC 24 2531607755 ps
T93 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2835435899 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:44 AM UTC 24 2635637300 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.4092396380 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:45 AM UTC 24 2133256642 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2062366870 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:45 AM UTC 24 2475899053 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2385614074 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:55 AM UTC 24 3252686948 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2718555700 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:46 AM UTC 24 2225998174 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2041650885 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:46 AM UTC 24 2522523337 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.595779313 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:47 AM UTC 24 2389723003 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2927804780 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:47 AM UTC 24 3200285389 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.4047719599 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:47 AM UTC 24 3037273054 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.3387311128 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:48 AM UTC 24 2475798402 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3127314194 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:48 AM UTC 24 6139005133 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.233859472 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:48 AM UTC 24 5685592589 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2912787548 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:49 AM UTC 24 2186419395 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2633186249 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:49 AM UTC 24 2987803517 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.3776304311 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:49 AM UTC 24 2096111544 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3036549224 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:50 AM UTC 24 2657404501 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1486530643 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:50 AM UTC 24 6791975515 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.324049001 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:50 AM UTC 24 2765707066 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.334599477 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:51 AM UTC 24 2481853918 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3138025342 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:51 AM UTC 24 2467526492 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2186956295 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:51 AM UTC 24 2220020355 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.1451726534 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:52 AM UTC 24 2525072188 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1897161805 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:52 AM UTC 24 2198054688 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.4239844393 Oct 12 12:56:35 AM UTC 24 Oct 12 12:56:52 AM UTC 24 22041982941 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2401012406 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:52 AM UTC 24 2511359625 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1824318783 Oct 12 12:56:41 AM UTC 24 Oct 12 12:56:52 AM UTC 24 3362897820 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.4029988258 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:53 AM UTC 24 5369075277 ps
T281 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2689413926 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:53 AM UTC 24 22077763750 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2618621954 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:54 AM UTC 24 3056360002 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.830096313 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:54 AM UTC 24 2609233272 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.175146617 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:54 AM UTC 24 2117539672 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.434303522 Oct 12 12:56:50 AM UTC 24 Oct 12 12:56:54 AM UTC 24 2032135933 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3600449021 Oct 12 12:56:50 AM UTC 24 Oct 12 12:56:55 AM UTC 24 2493686025 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2544572242 Oct 12 12:56:52 AM UTC 24 Oct 12 12:56:56 AM UTC 24 4272445034 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.215179605 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:56 AM UTC 24 2262028132 ps
T433 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1880344223 Oct 12 12:56:47 AM UTC 24 Oct 12 12:56:56 AM UTC 24 2610284233 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2470478289 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:56 AM UTC 24 7060648790 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.288995149 Oct 12 12:56:54 AM UTC 24 Oct 12 12:56:57 AM UTC 24 2142640314 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3912542696 Oct 12 12:56:50 AM UTC 24 Oct 12 12:56:57 AM UTC 24 2116839260 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3281549715 Oct 12 12:56:36 AM UTC 24 Oct 12 12:56:57 AM UTC 24 6471542032 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1497517831 Oct 12 12:56:51 AM UTC 24 Oct 12 12:56:57 AM UTC 24 2516922676 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2980764345 Oct 12 12:56:50 AM UTC 24 Oct 12 12:56:58 AM UTC 24 2126654183 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1219423197 Oct 12 12:56:44 AM UTC 24 Oct 12 12:56:59 AM UTC 24 47401043052 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3638488194 Oct 12 12:56:51 AM UTC 24 Oct 12 12:56:59 AM UTC 24 2449066216 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.166783149 Oct 12 12:56:55 AM UTC 24 Oct 12 12:57:00 AM UTC 24 2144271165 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.1613013122 Oct 12 12:56:55 AM UTC 24 Oct 12 12:57:00 AM UTC 24 2534491668 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.2421014867 Oct 12 12:56:49 AM UTC 24 Oct 12 12:57:00 AM UTC 24 5154578839 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3337168461 Oct 12 12:56:55 AM UTC 24 Oct 12 12:57:01 AM UTC 24 2634021541 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.1788315546 Oct 12 12:56:53 AM UTC 24 Oct 12 12:57:01 AM UTC 24 2496213649 ps
T165 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2040145511 Oct 12 12:56:55 AM UTC 24 Oct 12 12:57:01 AM UTC 24 3621177535 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1956630342 Oct 12 12:56:47 AM UTC 24 Oct 12 12:57:01 AM UTC 24 3828790610 ps
T166 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1564730160 Oct 12 12:56:54 AM UTC 24 Oct 12 12:57:02 AM UTC 24 2010934123 ps
T167 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1996415217 Oct 12 12:56:51 AM UTC 24 Oct 12 12:57:02 AM UTC 24 2611603647 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.669098693 Oct 12 12:56:56 AM UTC 24 Oct 12 12:57:02 AM UTC 24 3232187575 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2720433331 Oct 12 12:56:58 AM UTC 24 Oct 12 12:57:03 AM UTC 24 2732277567 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3655797618 Oct 12 12:57:00 AM UTC 24 Oct 12 12:57:03 AM UTC 24 2541457776 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1882419853 Oct 12 12:56:41 AM UTC 24 Oct 12 12:57:04 AM UTC 24 26353438665 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.871552257 Oct 12 12:56:55 AM UTC 24 Oct 12 12:57:05 AM UTC 24 2483600142 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.2746584830 Oct 12 12:56:59 AM UTC 24 Oct 12 12:57:05 AM UTC 24 2019190553 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.4120442004 Oct 12 12:56:59 AM UTC 24 Oct 12 12:57:08 AM UTC 24 2111036845 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2617623291 Oct 12 12:57:01 AM UTC 24 Oct 12 12:57:08 AM UTC 24 3577602197 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.861829878 Oct 12 12:57:05 AM UTC 24 Oct 12 12:57:08 AM UTC 24 2213596086 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2753719675 Oct 12 12:57:00 AM UTC 24 Oct 12 12:57:08 AM UTC 24 2189797320 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.799725369 Oct 12 12:57:04 AM UTC 24 Oct 12 12:57:09 AM UTC 24 2118190411 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2138784105 Oct 12 12:56:58 AM UTC 24 Oct 12 12:57:09 AM UTC 24 9140112108 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3628067942 Oct 12 12:57:00 AM UTC 24 Oct 12 12:57:09 AM UTC 24 2608957378 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.61070328 Oct 12 12:57:05 AM UTC 24 Oct 12 12:57:10 AM UTC 24 2464325974 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1000458349 Oct 12 12:57:06 AM UTC 24 Oct 12 12:57:10 AM UTC 24 2632475462 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.3785407664 Oct 12 12:57:05 AM UTC 24 Oct 12 12:57:10 AM UTC 24 2536237610 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.564737094 Oct 12 12:56:49 AM UTC 24 Oct 12 12:57:10 AM UTC 24 22268949945 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3218534116 Oct 12 12:56:54 AM UTC 24 Oct 12 12:57:11 AM UTC 24 21535012413 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.902706693 Oct 12 12:57:02 AM UTC 24 Oct 12 12:57:12 AM UTC 24 8983845290 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2966363233 Oct 12 12:57:06 AM UTC 24 Oct 12 12:57:12 AM UTC 24 4389090510 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.549271877 Oct 12 12:56:59 AM UTC 24 Oct 12 12:57:12 AM UTC 24 2486867981 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.877775011 Oct 12 12:57:04 AM UTC 24 Oct 12 12:57:12 AM UTC 24 2010259513 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3706073508 Oct 12 12:56:35 AM UTC 24 Oct 12 12:57:12 AM UTC 24 26338507988 ps
T432 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.761712524 Oct 12 12:57:11 AM UTC 24 Oct 12 12:57:14 AM UTC 24 2593709023 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.2502543 Oct 12 12:57:10 AM UTC 24 Oct 12 12:57:14 AM UTC 24 2015210116 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.3049020925 Oct 12 12:57:11 AM UTC 24 Oct 12 12:57:15 AM UTC 24 2527904496 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1674042750 Oct 12 12:57:29 AM UTC 24 Oct 12 12:57:31 AM UTC 24 2055029980 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3157449805 Oct 12 12:57:01 AM UTC 24 Oct 12 12:57:15 AM UTC 24 12874925934 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.3714160251 Oct 12 12:57:11 AM UTC 24 Oct 12 12:57:16 AM UTC 24 2136716507 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2292827044 Oct 12 12:57:03 AM UTC 24 Oct 12 12:57:17 AM UTC 24 5588109810 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.88935706 Oct 12 12:57:13 AM UTC 24 Oct 12 12:57:17 AM UTC 24 2842300300 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.833343297 Oct 12 12:57:11 AM UTC 24 Oct 12 12:57:17 AM UTC 24 2249597228 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1575388075 Oct 12 12:56:47 AM UTC 24 Oct 12 12:57:17 AM UTC 24 42192682616 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.649430043 Oct 12 12:57:13 AM UTC 24 Oct 12 12:57:18 AM UTC 24 3573630539 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.2464547917 Oct 12 12:57:13 AM UTC 24 Oct 12 12:57:18 AM UTC 24 2390580066 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1105439624 Oct 12 12:57:03 AM UTC 24 Oct 12 12:57:19 AM UTC 24 28838568724 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.122383314 Oct 12 12:57:13 AM UTC 24 Oct 12 12:57:19 AM UTC 24 2617900900 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.938628466 Oct 12 12:57:08 AM UTC 24 Oct 12 12:57:19 AM UTC 24 3234473527 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.1442999466 Oct 12 12:57:15 AM UTC 24 Oct 12 12:57:19 AM UTC 24 2132470680 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1280409955 Oct 12 12:57:16 AM UTC 24 Oct 12 12:57:19 AM UTC 24 2284099717 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.1324266284 Oct 12 12:56:41 AM UTC 24 Oct 12 12:57:20 AM UTC 24 15645049764 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.988048774 Oct 12 12:57:10 AM UTC 24 Oct 12 12:57:20 AM UTC 24 3862048506 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.3156415813 Oct 12 12:57:15 AM UTC 24 Oct 12 12:57:20 AM UTC 24 2023276796 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.796468928 Oct 12 12:57:18 AM UTC 24 Oct 12 12:57:22 AM UTC 24 3394395382 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1004709537 Oct 12 12:56:44 AM UTC 24 Oct 12 12:57:22 AM UTC 24 18654795184 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.237962738 Oct 12 12:57:18 AM UTC 24 Oct 12 12:57:22 AM UTC 24 2531778329 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3203650586 Oct 12 12:57:10 AM UTC 24 Oct 12 12:57:22 AM UTC 24 7153854409 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.2561529174 Oct 12 12:56:41 AM UTC 24 Oct 12 12:57:25 AM UTC 24 56173982481 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4057098532 Oct 12 12:57:22 AM UTC 24 Oct 12 12:57:26 AM UTC 24 2646754224 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3490126308 Oct 12 12:57:20 AM UTC 24 Oct 12 12:57:26 AM UTC 24 3777860886 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1909268649 Oct 12 12:57:13 AM UTC 24 Oct 12 12:57:26 AM UTC 24 3303071916 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.413513624 Oct 12 12:57:18 AM UTC 24 Oct 12 12:57:27 AM UTC 24 2609175071 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2957518292 Oct 12 12:57:21 AM UTC 24 Oct 12 12:57:27 AM UTC 24 2122411541 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1430894478 Oct 12 12:57:15 AM UTC 24 Oct 12 12:57:28 AM UTC 24 3361776131 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.176511702 Oct 12 12:57:16 AM UTC 24 Oct 12 12:57:29 AM UTC 24 2451806444 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.400103572 Oct 12 12:57:18 AM UTC 24 Oct 12 12:57:29 AM UTC 24 3950170691 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2192997872 Oct 12 12:57:21 AM UTC 24 Oct 12 12:57:29 AM UTC 24 2015051273 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2112810946 Oct 12 12:57:21 AM UTC 24 Oct 12 12:57:29 AM UTC 24 2508938286 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.578697086 Oct 12 12:57:24 AM UTC 24 Oct 12 12:57:29 AM UTC 24 6059950391 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2491643459 Oct 12 12:57:20 AM UTC 24 Oct 12 12:57:30 AM UTC 24 3109908635 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.2270846856 Oct 12 12:57:21 AM UTC 24 Oct 12 12:57:30 AM UTC 24 2087713933 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.235605342 Oct 12 12:57:24 AM UTC 24 Oct 12 12:57:31 AM UTC 24 3631157231 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.2327183838 Oct 12 12:56:59 AM UTC 24 Oct 12 12:57:31 AM UTC 24 12176270666 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.241612215 Oct 12 12:57:29 AM UTC 24 Oct 12 12:57:32 AM UTC 24 2128844457 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2287385588 Oct 12 12:57:18 AM UTC 24 Oct 12 12:57:32 AM UTC 24 6227974498 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.804807675 Oct 12 12:57:30 AM UTC 24 Oct 12 12:57:33 AM UTC 24 2545559967 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1657165888 Oct 12 12:56:49 AM UTC 24 Oct 12 12:57:34 AM UTC 24 22015782530 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2770683346 Oct 12 12:57:29 AM UTC 24 Oct 12 12:57:35 AM UTC 24 2470175748 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.498112035 Oct 12 12:57:30 AM UTC 24 Oct 12 12:57:35 AM UTC 24 2144336220 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3567008116 Oct 12 12:57:21 AM UTC 24 Oct 12 12:57:35 AM UTC 24 2464828408 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.415608815 Oct 12 12:57:30 AM UTC 24 Oct 12 12:57:35 AM UTC 24 2619735741 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4180185991 Oct 12 12:57:10 AM UTC 24 Oct 12 12:57:36 AM UTC 24 24725473333 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4278539375 Oct 12 12:57:31 AM UTC 24 Oct 12 12:57:37 AM UTC 24 2664365060 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.2553950074 Oct 12 12:57:31 AM UTC 24 Oct 12 12:57:37 AM UTC 24 2586391269 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.3372063428 Oct 12 12:57:33 AM UTC 24 Oct 12 12:57:37 AM UTC 24 2136977922 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.222446984 Oct 12 12:57:34 AM UTC 24 Oct 12 12:57:38 AM UTC 24 2487377399 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2670853216 Oct 12 12:57:27 AM UTC 24 Oct 12 12:57:39 AM UTC 24 9118600487 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.3748521574 Oct 12 12:57:35 AM UTC 24 Oct 12 12:57:39 AM UTC 24 2066432438 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3841303271 Oct 12 12:57:13 AM UTC 24 Oct 12 12:57:39 AM UTC 24 140858882350 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.448969733 Oct 12 12:57:35 AM UTC 24 Oct 12 12:57:40 AM UTC 24 2624734979 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1318248955 Oct 12 12:57:25 AM UTC 24 Oct 12 12:57:40 AM UTC 24 2896958836 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1698386295 Oct 12 12:57:20 AM UTC 24 Oct 12 12:57:40 AM UTC 24 26594388002 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.3369215913 Oct 12 12:56:53 AM UTC 24 Oct 12 12:57:41 AM UTC 24 157612650862 ps
T251 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.2922294242 Oct 12 12:57:33 AM UTC 24 Oct 12 12:57:41 AM UTC 24 2012294321 ps
T252 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3984450554 Oct 12 12:57:30 AM UTC 24 Oct 12 12:57:42 AM UTC 24 3362506826 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.4257051412 Oct 12 12:57:19 AM UTC 24 Oct 12 12:57:42 AM UTC 24 53791125030 ps
T253 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2489822686 Oct 12 12:56:41 AM UTC 24 Oct 12 12:57:42 AM UTC 24 42019844535 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2975913264 Oct 12 12:57:21 AM UTC 24 Oct 12 12:58:02 AM UTC 24 45508496473 ps
T260 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2772457210 Oct 12 12:57:27 AM UTC 24 Oct 12 12:57:42 AM UTC 24 12722922574 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.480078308 Oct 12 12:56:36 AM UTC 24 Oct 12 12:57:42 AM UTC 24 39482461017 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2661604473 Oct 12 12:57:37 AM UTC 24 Oct 12 12:57:42 AM UTC 24 4102220651 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.4126262125 Oct 12 12:57:10 AM UTC 24 Oct 12 12:57:42 AM UTC 24 54264707379 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2227622381 Oct 12 12:57:36 AM UTC 24 Oct 12 12:57:42 AM UTC 24 3898472620 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1694452551 Oct 12 12:57:24 AM UTC 24 Oct 12 12:57:43 AM UTC 24 4804566770 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.3530820676 Oct 12 12:57:38 AM UTC 24 Oct 12 12:57:43 AM UTC 24 3800147666 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3443747468 Oct 12 12:57:40 AM UTC 24 Oct 12 12:57:43 AM UTC 24 2148971260 ps
T221 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1207871186 Oct 12 12:57:40 AM UTC 24 Oct 12 12:57:43 AM UTC 24 2032051982 ps
T222 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.4159540036 Oct 12 12:57:40 AM UTC 24 Oct 12 12:57:44 AM UTC 24 2233414965 ps
T223 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2813604290 Oct 12 12:57:40 AM UTC 24 Oct 12 12:57:45 AM UTC 24 2475184382 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3786449125 Oct 12 12:57:33 AM UTC 24 Oct 12 12:57:46 AM UTC 24 16395478954 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1943821560 Oct 12 12:57:42 AM UTC 24 Oct 12 12:57:46 AM UTC 24 4653255119 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.944999464 Oct 12 12:57:33 AM UTC 24 Oct 12 12:57:46 AM UTC 24 15187599139 ps
T227 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.399321632 Oct 12 12:57:43 AM UTC 24 Oct 12 12:57:47 AM UTC 24 2054287147 ps
T228 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2705248674 Oct 12 12:57:35 AM UTC 24 Oct 12 12:57:47 AM UTC 24 2514747150 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3644839890 Oct 12 12:57:37 AM UTC 24 Oct 12 12:57:47 AM UTC 24 6182931540 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.25997739 Oct 12 12:57:43 AM UTC 24 Oct 12 12:57:48 AM UTC 24 6733081707 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.640764652 Oct 12 12:56:58 AM UTC 24 Oct 12 12:57:49 AM UTC 24 71293608855 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.772712581 Oct 12 12:57:30 AM UTC 24 Oct 12 12:57:49 AM UTC 24 4236922439 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3527636590 Oct 12 12:57:39 AM UTC 24 Oct 12 12:57:49 AM UTC 24 7752827966 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.1264570370 Oct 12 12:57:15 AM UTC 24 Oct 12 12:57:49 AM UTC 24 7901652071 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3224915441 Oct 12 12:57:46 AM UTC 24 Oct 12 12:57:50 AM UTC 24 2712573519 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.323731395 Oct 12 12:57:44 AM UTC 24 Oct 12 12:57:50 AM UTC 24 2180966725 ps
T184 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2913599650 Oct 12 12:57:43 AM UTC 24 Oct 12 12:57:51 AM UTC 24 3419560880 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3786594742 Oct 12 12:57:44 AM UTC 24 Oct 12 12:57:52 AM UTC 24 2118067455 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1266844639 Oct 12 12:57:42 AM UTC 24 Oct 12 12:57:52 AM UTC 24 2611468551 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2575877852 Oct 12 12:57:45 AM UTC 24 Oct 12 12:57:52 AM UTC 24 2611260298 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1559989775 Oct 12 12:57:44 AM UTC 24 Oct 12 12:57:54 AM UTC 24 2463039639 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2441266355 Oct 12 12:57:50 AM UTC 24 Oct 12 12:57:54 AM UTC 24 2494812893 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.700145884 Oct 12 12:57:42 AM UTC 24 Oct 12 12:57:54 AM UTC 24 2508440609 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3638106304 Oct 12 12:57:51 AM UTC 24 Oct 12 12:57:54 AM UTC 24 2528839927 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2355402917 Oct 12 12:57:43 AM UTC 24 Oct 12 12:57:54 AM UTC 24 3572447015 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2011129761 Oct 12 12:57:53 AM UTC 24 Oct 12 12:58:01 AM UTC 24 3543739062 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2617239959 Oct 12 12:57:47 AM UTC 24 Oct 12 12:57:55 AM UTC 24 3607441144 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.1733765491 Oct 12 12:57:49 AM UTC 24 Oct 12 12:57:56 AM UTC 24 2118908973 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.3562993996 Oct 12 12:57:45 AM UTC 24 Oct 12 12:57:57 AM UTC 24 2512994974 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3668590172 Oct 12 12:57:52 AM UTC 24 Oct 12 12:57:57 AM UTC 24 3025705484 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.1453179633 Oct 12 12:57:48 AM UTC 24 Oct 12 12:57:57 AM UTC 24 11653255963 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.241319742 Oct 12 12:57:48 AM UTC 24 Oct 12 12:57:58 AM UTC 24 4476241945 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3644448630 Oct 12 12:57:27 AM UTC 24 Oct 12 12:57:59 AM UTC 24 22592067539 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3012739698 Oct 12 12:57:53 AM UTC 24 Oct 12 12:57:59 AM UTC 24 8249232538 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.1281295511 Oct 12 12:57:56 AM UTC 24 Oct 12 12:57:59 AM UTC 24 2130339325 ps
T422 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2429312857 Oct 12 12:57:48 AM UTC 24 Oct 12 12:58:00 AM UTC 24 7852366127 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1824631011 Oct 12 12:57:54 AM UTC 24 Oct 12 12:58:00 AM UTC 24 3619271178 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3963910210 Oct 12 12:57:57 AM UTC 24 Oct 12 12:58:00 AM UTC 24 2171330843 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1319503391 Oct 12 12:57:49 AM UTC 24 Oct 12 12:58:01 AM UTC 24 2013615127 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.611740963 Oct 12 12:57:56 AM UTC 24 Oct 12 12:58:03 AM UTC 24 2013767581 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3606885540 Oct 12 12:57:51 AM UTC 24 Oct 12 12:58:02 AM UTC 24 2140713281 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3729028584 Oct 12 12:57:58 AM UTC 24 Oct 12 12:58:03 AM UTC 24 2633794721 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1064613141 Oct 12 12:57:55 AM UTC 24 Oct 12 12:58:04 AM UTC 24 8616775322 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3622761241 Oct 12 12:57:51 AM UTC 24 Oct 12 12:58:04 AM UTC 24 2610290208 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.494924039 Oct 12 12:58:01 AM UTC 24 Oct 12 12:58:04 AM UTC 24 4251222931 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.242644505 Oct 12 12:57:43 AM UTC 24 Oct 12 12:58:05 AM UTC 24 7026900981 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4100601355 Oct 12 12:57:55 AM UTC 24 Oct 12 12:58:05 AM UTC 24 9880781852 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3125048681 Oct 12 12:58:01 AM UTC 24 Oct 12 12:58:05 AM UTC 24 5334354780 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2724404024 Oct 12 12:58:01 AM UTC 24 Oct 12 12:58:07 AM UTC 24 3515064524 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.187658333 Oct 12 12:57:58 AM UTC 24 Oct 12 12:58:07 AM UTC 24 2511038180 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1210095492 Oct 12 12:58:03 AM UTC 24 Oct 12 12:58:07 AM UTC 24 2489027542 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.4257320171 Oct 12 12:57:57 AM UTC 24 Oct 12 12:58:07 AM UTC 24 2461848308 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2305106633 Oct 12 12:57:58 AM UTC 24 Oct 12 12:58:08 AM UTC 24 3875192505 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1745637435 Oct 12 12:58:05 AM UTC 24 Oct 12 12:58:09 AM UTC 24 4333155700 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3040962323 Oct 12 12:58:05 AM UTC 24 Oct 12 12:58:09 AM UTC 24 6603186213 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3842876593 Oct 12 12:58:05 AM UTC 24 Oct 12 12:58:09 AM UTC 24 2624685717 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1148871429 Oct 12 12:58:03 AM UTC 24 Oct 12 12:58:09 AM UTC 24 2115313484 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3207225533 Oct 12 12:58:50 AM UTC 24 Oct 12 12:58:57 AM UTC 24 2114445934 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3822377502 Oct 12 12:58:05 AM UTC 24 Oct 12 12:58:11 AM UTC 24 2512369283 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.4018565603 Oct 12 12:58:07 AM UTC 24 Oct 12 12:58:11 AM UTC 24 2470484132 ps
T493 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.2045949183 Oct 12 12:58:02 AM UTC 24 Oct 12 12:58:11 AM UTC 24 2012338617 ps
T494 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2052081583 Oct 12 12:58:10 AM UTC 24 Oct 12 12:58:13 AM UTC 24 2768046907 ps
T495 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1243383670 Oct 12 12:58:05 AM UTC 24 Oct 12 12:58:13 AM UTC 24 2243325607 ps
T496 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.3475202971 Oct 12 12:58:48 AM UTC 24 Oct 12 12:58:52 AM UTC 24 2031710636 ps
T497 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.1939264389 Oct 12 12:58:10 AM UTC 24 Oct 12 12:58:14 AM UTC 24 2045131180 ps
T498 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.222301656 Oct 12 12:58:10 AM UTC 24 Oct 12 12:58:14 AM UTC 24 2116748599 ps
T499 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1651357292 Oct 12 12:58:10 AM UTC 24 Oct 12 12:58:15 AM UTC 24 2624163574 ps
T500 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1513927577 Oct 12 12:58:10 AM UTC 24 Oct 12 12:58:15 AM UTC 24 2467315224 ps
T501 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2774863467 Oct 12 12:58:12 AM UTC 24 Oct 12 12:58:16 AM UTC 24 5782022364 ps
T502 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.2723917146 Oct 12 12:58:10 AM UTC 24 Oct 12 12:58:17 AM UTC 24 2125360813 ps
T503 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1128820231 Oct 12 12:58:12 AM UTC 24 Oct 12 12:58:18 AM UTC 24 3609104076 ps
T504 /workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1226782620 Oct 12 12:58:05 AM UTC 24 Oct 12 12:58:18 AM UTC 24 3842123678 ps
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