Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1216

1

T35

14

T60

10

T41

11

auto[1]

1642

1

T35

6

T60

18

T41

13

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2301

1

T35

20

T60

13

T41

19

auto[1]

557

1

T60

15

T41

5

T108

2

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2707

1

T35

20

T60

28

T41

20

auto[1]

151

1

T41

4

T42

3

T43

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2671

1

T35

20

T60

28

T41

20

auto[1]

187

1

T41

4

T44

1

T45

6

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2713

1

T35

20

T60

28

T41

24

auto[1]

145

1

T45

5

T46

1

T47

4

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1735

1

T35

1

T60

1

T41

4

auto[1]

1123

1

T35

19

T60

27

T41

20

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T35

9

T60

8

T41

11

auto[1]

1796

1

T35

11

T60

20

T41

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1152

1

T35

10

T60

12

T41

10

auto[1]

1706

1

T35

10

T60

16

T41

14

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T35

8

T60

11

T41

8

auto[1]

1807

1

T35

12

T60

17

T41

16

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T35

7

T60

11

T41

11

auto[1]

1666

1

T35

13

T60

17

T41

13

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T42

1

T245

3

T312

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T35

2

T254

1

T179

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T59

1

T44

1

T46

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T60

1

T108

1

T277

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

28

1

T42

1

T43

1

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T41

1

T249

1

T261

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T59

2

T63

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T60

1

T249

1

T261

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T42

1

T43

2

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T41

1

T249

3

T280

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

49

1

T59

1

T46

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T41

1

T108

1

T280

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T47

1

T241

1

T112

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T60

2

T108

1

T280

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T270

1

T360

1

T361

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

21

1

T35

2

T261

1

T254

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

36

1

T59

1

T42

1

T63

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T41

1

T257

1

T362

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T59

2

T42

1

T63

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T108

1

T45

2

T249

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

23

1

T59

1

T42

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T249

1

T261

1

T254

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T42

1

T47

3

T231

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T35

1

T108

1

T47

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T43

1

T245

1

T112

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5

1

T41

1

T280

1

T363

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

34

1

T35

1

T63

5

T247

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T41

2

T108

1

T364

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T42

1

T240

11

T365

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

49

1

T35

2

T60

1

T108

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T59

1

T44

1

T280

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

63

1

T35

1

T108

1

T44

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T241

2

T248

2

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T35

1

T60

1

T179

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T41

1

T241

2

T270

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T35

1

T60

1

T249

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

24

1

T43

2

T241

1

T246

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T35

1

T366

2

T236

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T59

2

T42

1

T61

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T60

1

T41

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46

1

T60

1

T59

1

T42

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T35

1

T249

2

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T42

1

T61

1

T63

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T234

1

T236

1

T263

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T43

6

T63

1

T46

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T35

2

T41

1

T367

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T59

1

T42

1

T63

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

57

1

T41

2

T108

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T59

1

T43

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T35

1

T41

1

T108

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T59

2

T108

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T60

1

T108

1

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25

1

T59

1

T247

2

T270

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T35

1

T45

1

T249

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T61

1

T248

1

T262

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

54

1

T41

1

T108

1

T254

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T42

1

T312

1

T368

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T60

2

T41

1

T45

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T61

10

T270

1

T369

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

44

1

T41

1

T108

1

T249

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

94

1

T59

2

T42

2

T43

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

67

1

T35

3

T45

1

T47

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

290

1

T41

3

T59

1

T42

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T60

1

T254

1

T179

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T41

1

T45

1

T261

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T60

1

T261

2

T366

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T277

1

T366

1

T370

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T108

1

T280

1

T363

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T45

1

T263

1

T258

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T261

1

T280

1

T254

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T41

1

T254

1

T236

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T45

1

T254

1

T112

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4

1

T255

1

T371

1

T258

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T60

1

T45

1

T254

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T41

1

T277

1

T255

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T60

1

T47

5

T280

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T45

1

T261

1

T254

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T45

1

T280

1

T263

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T41

1

T45

1

T280

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T261

1

T247

3

T234

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T277

1

T371

1

T363

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T45

1

T261

1

T362

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T60

1

T277

1

T366

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T366

1

T234

1

T372

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T278

1

T257

1

T363

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T60

1

T45

1

T256

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T60

1

T364

2

T367

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T112

2

T256

2

T257

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T60

1

T261

1

T366

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T261

1

T236

1

T373

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T277

1

T236

1

T256

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T236

1

T256

1

T374

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T246

1

T255

1

T366

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T179

1

T257

1

T375

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T277

1

T263

1

T376

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

129

1

T60

8

T41

1

T108

1

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T42

1

T245

3

T312

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T35

2

T41

1

T45

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

51

1

T59

1

T44

1

T46

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T60

2

T108

1

T261

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T42

1

T43

1

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T41

1

T249

1

T261

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T59

2

T63

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T60

1

T108

1

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T42

1

T43

2

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T41

1

T45

1

T249

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T59

1

T46

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T41

1

T108

1

T261

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T47

1

T241

1

T112

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T60

2

T41

1

T108

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T270

1

T360

1

T361

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T35

2

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T59

1

T42

1

T63

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T41

1

T255

1

T257

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T59

2

T42

1

T63

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T60

1

T108

1

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T59

1

T42

2

T46

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T41

1

T249

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T42

1

T47

3

T262

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T35

1

T60

1

T108

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T43

1

T46

1

T245

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T41

1

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T35

1

T63

5

T312

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T41

2

T108

1

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T42

1

T240

11

T248

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T35

2

T60

1

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

35

1

T59

1

T44

1

T280

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T35

1

T108

1

T44

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T241

1

T248

2

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T35

1

T60

1

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

39

1

T41

1

T46

1

T241

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T35

1

T60

1

T45

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T43

2

T46

2

T241

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T35

1

T60

1

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T59

2

T42

1

T61

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T60

1

T41

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T60

1

T59

1

T42

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T35

1

T249

2

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T42

2

T61

1

T63

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T60

1

T45

1

T234

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

70

1

T43

5

T63

1

T46

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T35

2

T60

1

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

62

1

T59

1

T42

1

T63

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T41

2

T108

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T59

1

T43

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T35

1

T60

1

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T59

2

T108

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T60

1

T108

1

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T59

1

T247

2

T262

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T35

1

T45

1

T249

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T61

1

T248

1

T262

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

64

1

T41

1

T108

1

T254

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T42

1

T312

1

T368

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T60

2

T41

1

T45

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

86

1

T61

10

T46

1

T248

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

51

1

T41

1

T108

1

T249

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

96

1

T59

2

T42

2

T43

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

75

1

T35

3

T45

1

T47

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

177

1

T59

1

T42

2

T45

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

121

1

T60

9

T108

1

T45

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T377

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T41

1

T366

1

T370

2

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T42

1

T245

3

T312

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T35

2

T41

1

T45

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T59

1

T44

1

T46

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T60

2

T108

1

T261

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T42

1

T43

1

T44

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T41

1

T249

1

T261

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T59

2

T63

1

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T60

1

T108

1

T249

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T42

1

T43

2

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T41

1

T45

1

T249

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

53

1

T59

1

T46

1

T248

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T41

1

T108

1

T261

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T47

1

T241

1

T112

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T60

2

T41

1

T108

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T270

1

T360

1

T361

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

29

1

T35

2

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T59

1

T42

1

T63

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T41

1

T255

1

T257

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T59

2

T42

1

T63

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T60

1

T108

1

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T59

1

T42

2

T46

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T41

1

T249

1

T261

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T42

1

T47

3

T262

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T35

1

T60

1

T108

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T43

1

T46

1

T245

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T41

1

T45

1

T261

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T35

1

T63

5

T312

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T41

2

T108

1

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T42

1

T240

11

T248

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

59

1

T35

2

T60

1

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T59

1

T280

1

T312

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T35

1

T108

1

T44

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T241

1

T248

2

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T35

1

T60

1

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T41

1

T46

1

T241

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T35

1

T60

1

T45

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T43

2

T46

2

T241

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T35

1

T60

1

T277

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T59

2

T42

1

T61

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29

1

T60

1

T41

1

T108

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T60

1

T59

1

T42

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T35

1

T249

2

T261

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T42

2

T61

1

T63

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T60

1

T45

1

T234

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

70

1

T43

6

T63

1

T46

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T35

2

T60

1

T41

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T59

1

T42

1

T63

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

71

1

T41

2

T108

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T59

1

T43

2

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T35

1

T60

1

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T59

2

T108

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T60

1

T108

1

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

25

1

T59

1

T247

1

T262

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T35

1

T45

1

T249

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T61

1

T248

1

T262

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

64

1

T41

1

T108

1

T254

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T42

1

T312

1

T368

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T60

2

T41

1

T45

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

86

1

T61

10

T46

1

T248

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

51

1

T41

1

T108

1

T249

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

91

1

T59

2

T42

2

T43

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

75

1

T35

3

T45

1

T47

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

173

1

T59

1

T42

5

T45

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

124

1

T60

9

T108

1

T45

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T378

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T112

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T379

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T246

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T41

1

T261

5

T234

1

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded