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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 29 67 69.79 29
Automatically Generated Cross Bins 96 29 67 69.79 29
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] [auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 48 1 T42 1 T245 3 T312 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 20 1 T35 2 T41 1 T45 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 51 1 T59 1 T44 1 T46 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 20 1 T60 2 T108 1 T261 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 32 1 T42 1 T43 1 T44 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 23 1 T41 1 T249 1 T261 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 38 1 T59 2 T63 1 T47 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 16 1 T60 1 T108 1 T249 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 56 1 T42 1 T43 2 T44 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 20 1 T41 1 T45 1 T249 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 54 1 T59 1 T46 1 T248 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 23 1 T41 1 T108 1 T261 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 34 1 T47 1 T241 1 T112 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 19 1 T60 2 T41 1 T108 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 19 1 T270 1 T360 1 T361 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 30 1 T35 2 T45 1 T261 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 42 1 T59 1 T42 1 T63 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 8 1 T41 1 T255 1 T257 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 42 1 T59 2 T42 1 T63 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 27 1 T60 1 T108 1 T45 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 33 1 T59 1 T42 2 T46 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 19 1 T41 1 T249 1 T261 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 28 1 T42 1 T47 3 T262 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 33 1 T35 1 T60 1 T108 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 43 1 T43 1 T46 1 T245 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 13 1 T41 1 T45 1 T261 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 38 1 T35 1 T63 5 T312 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 21 1 T41 2 T108 1 T45 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 33 1 T42 1 T240 11 T248 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 59 1 T35 2 T60 1 T41 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 35 1 T59 1 T44 1 T280 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 71 1 T35 1 T108 1 T44 8
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 54 1 T241 2 T248 2 T277 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 17 1 T35 1 T60 1 T277 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 39 1 T41 1 T46 1 T241 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 17 1 T35 1 T60 1 T45 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 31 1 T43 2 T46 2 T241 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 15 1 T35 1 T60 1 T277 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 50 1 T59 2 T42 1 T61 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 29 1 T60 1 T41 1 T108 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 49 1 T60 1 T59 1 T42 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 29 1 T35 1 T249 2 T261 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 37 1 T42 2 T61 1 T63 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 27 1 T60 1 T45 1 T234 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 69 1 T43 6 T63 1 T46 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 43 1 T35 2 T60 1 T41 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 60 1 T59 1 T42 1 T63 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 71 1 T41 2 T108 4 T45 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 53 1 T59 1 T43 2 T47 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 28 1 T35 1 T60 1 T41 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 41 1 T59 2 T108 1 T46 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 36 1 T60 1 T108 1 T45 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 27 1 T59 1 T247 1 T262 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 17 1 T35 1 T45 1 T249 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 43 1 T61 1 T248 1 T262 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 64 1 T41 1 T108 1 T254 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 49 1 T42 1 T312 1 T368 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 44 1 T60 2 T41 1 T45 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 84 1 T61 10 T46 1 T248 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 51 1 T41 1 T108 1 T249 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 90 1 T59 2 T42 2 T43 6
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 75 1 T35 3 T45 1 T47 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 214 1 T41 3 T59 1 T42 5
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 112 1 T60 9 T41 1 T108 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 1 1 T380 1 - - - -
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 1 1 T379 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 24 1 T366 2 T256 1 T263 3


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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